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2179 lines
64 KiB
ObjectPascal
2179 lines
64 KiB
ObjectPascal
{
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Copyright (c) 2003-2012 by Florian Klaempfl and others
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Contains the assembler object for ARM64
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit aasmcpu;
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{$i fpcdefs.inc}
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interface
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uses
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cclasses,globtype,globals,verbose,
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aasmbase,aasmtai,aasmdata,aasmsym,
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ogbase,
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symtype,
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cpubase,cpuinfo,cgbase,cgutils;
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const
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{ "mov reg,reg" source operand number }
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O_MOV_SOURCE = 1;
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{ "mov reg,reg" source operand number }
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O_MOV_DEST = 0;
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{ Operand types }
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OT_NONE = $00000000;
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OT_BITS8 = $00000001; { size, and other attributes, of the operand }
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OT_BITS16 = $00000002;
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OT_BITS32 = $00000004;
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OT_BITS64 = $00000008; { FPU only }
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OT_BITS80 = $00000010;
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OT_FAR = $00000020; { this means 16:16 or 16:32, like in CALL/JMP }
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OT_NEAR = $00000040;
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OT_SHORT = $00000080;
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OT_BITSTINY = $00000100; { fpu constant }
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OT_BITSSHIFTER =
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$00000200;
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OT_SIZE_MASK = $000003FF; { all the size attributes }
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OT_NON_SIZE = longint(not OT_SIZE_MASK);
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OT_SIGNED = $00000100; { the operand need to be signed -128-127 }
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OT_TO = $00000200; { operand is followed by a colon }
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{ reverse effect in FADD, FSUB &c }
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OT_COLON = $00000400;
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OT_SHIFTEROP = $00000800;
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OT_REGISTER = $00001000;
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OT_IMMEDIATE = $00002000;
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OT_REGLIST = $00008000;
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OT_IMM8 = $00002001;
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OT_IMM24 = $00002002;
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OT_IMM32 = $00002004;
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OT_IMM64 = $00002008;
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OT_IMM80 = $00002010;
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OT_IMMTINY = $00002100;
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OT_IMMSHIFTER= $00002200;
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OT_IMMEDIATE24 = OT_IMM24;
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OT_SHIFTIMM = OT_SHIFTEROP or OT_IMMSHIFTER;
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OT_SHIFTIMMEDIATE = OT_SHIFTIMM;
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OT_IMMEDIATESHIFTER = OT_IMMSHIFTER;
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OT_IMMEDIATEFPU = OT_IMMTINY;
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OT_REGMEM = $00200000; { for r/m, ie EA, operands }
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OT_REGNORM = $00201000; { 'normal' reg, qualifies as EA }
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OT_REG8 = $00201001;
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OT_REG16 = $00201002;
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OT_REG32 = $00201004;
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OT_REG64 = $00201008;
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OT_VREG = $00201010; { vector register }
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OT_REGF = $00201020; { coproc register }
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OT_MEMORY = $00204000; { register number in 'basereg' }
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OT_MEM8 = $00204001;
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OT_MEM16 = $00204002;
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OT_MEM32 = $00204004;
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OT_MEM64 = $00204008;
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OT_MEM80 = $00204010;
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{ word/byte load/store }
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OT_AM2 = $00010000;
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{ misc ld/st operations }
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OT_AM3 = $00020000;
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{ multiple ld/st operations }
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OT_AM4 = $00040000;
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{ co proc. ld/st operations }
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OT_AM5 = $00080000;
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OT_AMMASK = $000f0000;
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{ IT instruction }
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OT_CONDITION = $00100000;
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OT_MEMORYAM2 = OT_MEMORY or OT_AM2;
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OT_MEMORYAM3 = OT_MEMORY or OT_AM3;
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OT_MEMORYAM4 = OT_MEMORY or OT_AM4;
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OT_MEMORYAM5 = OT_MEMORY or OT_AM5;
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OT_FPUREG = $01000000; { floating point stack registers }
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OT_REG_SMASK = $00070000; { special register operands: these may be treated differently }
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{ a mask for the following }
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OT_MEM_OFFS = $00604000; { special type of EA }
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{ simple [address] offset }
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OT_ONENESS = $00800000; { special type of immediate operand }
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{ so UNITY == IMMEDIATE | ONENESS }
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OT_UNITY = $00802000; { for shift/rotate instructions }
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instabentries = {$i a64nop.inc}
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maxinfolen = 5;
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IF_NONE = $00000000;
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IF_ARMMASK = $000F0000;
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IF_ARM7 = $00070000;
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IF_FPMASK = $00F00000;
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IF_FPA = $00100000;
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{ if the instruction can change in a second pass }
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IF_PASS2 = longint($80000000);
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type
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TInsTabCache=array[TasmOp] of longint;
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PInsTabCache=^TInsTabCache;
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tinsentry = record
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opcode : tasmop;
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ops : byte;
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optypes : array[0..3] of longint;
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code : array[0..maxinfolen] of char;
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flags : longint;
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end;
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pinsentry=^tinsentry;
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{ const
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InsTab : array[0..instabentries-1] of TInsEntry={$i a64tab.inc} }
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var
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InsTabCache : PInsTabCache;
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type
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taicpu = class(tai_cpu_abstract_sym)
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oppostfix : TOpPostfix;
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procedure loadshifterop(opidx:longint;const so:tshifterop);
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constructor op_none(op : tasmop);
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constructor op_reg(op : tasmop;_op1 : tregister);
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constructor op_ref(op : tasmop;const _op1 : treference);
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constructor op_const(op : tasmop;_op1 : longint);
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constructor op_reg_reg(op : tasmop;_op1,_op2 : tregister);
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constructor op_reg_ref(op : tasmop;_op1 : tregister;const _op2 : treference);
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constructor op_reg_const(op:tasmop; _op1: tregister; _op2: aint);
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constructor op_reg_reg_reg(op : tasmop;_op1,_op2,_op3 : tregister);
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constructor op_reg_reg_reg_reg(op : tasmop;_op1,_op2,_op3,_op4 : tregister);
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constructor op_reg_reg_const(op : tasmop;_op1,_op2 : tregister; _op3: aint);
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constructor op_reg_reg_sym_ofs(op : tasmop;_op1,_op2 : tregister; _op3: tasmsymbol;_op3ofs: longint);
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constructor op_reg_reg_ref(op : tasmop;_op1,_op2 : tregister; const _op3: treference);
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constructor op_reg_reg_shifterop(op : tasmop;_op1,_op2 : tregister;_op3 : tshifterop);
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constructor op_reg_reg_reg_shifterop(op : tasmop;_op1,_op2,_op3 : tregister;_op4 : tshifterop);
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{ this is for Jmp instructions }
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constructor op_cond_sym(op : tasmop;cond:TAsmCond;_op1 : tasmsymbol);
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constructor op_sym(op : tasmop;_op1 : tasmsymbol);
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constructor op_sym_ofs(op : tasmop;_op1 : tasmsymbol;_op1ofs:longint);
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constructor op_reg_sym_ofs(op : tasmop;_op1 : tregister;_op2:tasmsymbol;_op2ofs : longint);
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constructor op_sym_ofs_ref(op : tasmop;_op1 : tasmsymbol;_op1ofs:longint;const _op2 : treference);
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function is_same_reg_move(regtype: Tregistertype):boolean; override;
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function spilling_get_operation_type(opnr: longint): topertype;override;
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{ assembler }
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public
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{ the next will reset all instructions that can change in pass 2 }
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procedure ResetPass1;override;
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procedure ResetPass2;override;
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function CheckIfValid:boolean;
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function GetString:string;
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function Pass1(objdata:TObjData):longint;override;
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procedure Pass2(objdata:TObjData);override;
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protected
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procedure ppuloadoper(ppufile:tcompilerppufile;var o:toper);override;
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procedure ppuwriteoper(ppufile:tcompilerppufile;const o:toper);override;
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procedure ppubuildderefimploper(var o:toper);override;
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procedure ppuderefoper(var o:toper);override;
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private
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{ next fields are filled in pass1, so pass2 is faster }
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inssize : shortint;
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insoffset : longint;
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LastInsOffset : longint; { need to be public to be reset }
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insentry : PInsEntry;
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function InsEnd:longint;
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procedure create_ot(objdata:TObjData);
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function Matches(p:PInsEntry):longint;
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function calcsize(p:PInsEntry):shortint;
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procedure gencode(objdata:TObjData);
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function NeedAddrPrefix(opidx:byte):boolean;
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procedure Swapoperands;
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function FindInsentry(objdata:TObjData):boolean;
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end;
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tai_align = class(tai_align_abstract)
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{ nothing to add }
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end;
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function spilling_create_load(const ref:treference;r:tregister):Taicpu;
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function spilling_create_store(r:tregister; const ref:treference):Taicpu;
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function setoppostfix(i : taicpu;pf : toppostfix) : taicpu;
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function setcondition(i : taicpu;c : tasmcond) : taicpu;
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{ inserts pc relative symbols at places where they are reachable
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and transforms special instructions to valid instruction encodings }
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procedure finalizearmcode(list,listtoinsert : TAsmList);
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{ inserts .pdata section and dummy function prolog needed for arm-wince exception handling }
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procedure InsertPData;
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procedure InitAsm;
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procedure DoneAsm;
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implementation
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uses
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cutils,rgobj,itcpugas,aoptcpu;
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procedure taicpu.loadshifterop(opidx:longint;const so:tshifterop);
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begin
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allocate_oper(opidx+1);
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with oper[opidx]^ do
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begin
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if typ<>top_shifterop then
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begin
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clearop(opidx);
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new(shifterop);
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end;
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shifterop^:=so;
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typ:=top_shifterop;
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end;
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end;
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{*****************************************************************************
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taicpu Constructors
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*****************************************************************************}
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constructor taicpu.op_none(op : tasmop);
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begin
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inherited create(op);
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end;
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{ for pld }
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constructor taicpu.op_ref(op : tasmop;const _op1 : treference);
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begin
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inherited create(op);
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ops:=1;
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loadref(0,_op1);
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end;
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constructor taicpu.op_reg(op : tasmop;_op1 : tregister);
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begin
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inherited create(op);
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ops:=1;
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loadreg(0,_op1);
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end;
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constructor taicpu.op_const(op : tasmop;_op1 : longint);
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begin
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inherited create(op);
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ops:=1;
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loadconst(0,aint(_op1));
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end;
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constructor taicpu.op_reg_reg(op : tasmop;_op1,_op2 : tregister);
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begin
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inherited create(op);
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ops:=2;
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loadreg(0,_op1);
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loadreg(1,_op2);
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end;
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constructor taicpu.op_reg_const(op:tasmop; _op1: tregister; _op2: aint);
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begin
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inherited create(op);
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ops:=2;
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loadreg(0,_op1);
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loadconst(1,aint(_op2));
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end;
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constructor taicpu.op_reg_ref(op : tasmop;_op1 : tregister;const _op2 : treference);
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begin
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inherited create(op);
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ops:=2;
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loadreg(0,_op1);
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loadref(1,_op2);
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end;
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constructor taicpu.op_reg_reg_reg(op : tasmop;_op1,_op2,_op3 : tregister);
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begin
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inherited create(op);
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ops:=3;
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loadreg(0,_op1);
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loadreg(1,_op2);
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loadreg(2,_op3);
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end;
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constructor taicpu.op_reg_reg_reg_reg(op : tasmop;_op1,_op2,_op3,_op4 : tregister);
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begin
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inherited create(op);
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ops:=4;
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loadreg(0,_op1);
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loadreg(1,_op2);
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loadreg(2,_op3);
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loadreg(3,_op4);
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end;
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constructor taicpu.op_reg_reg_const(op : tasmop;_op1,_op2 : tregister; _op3: aint);
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begin
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inherited create(op);
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ops:=3;
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loadreg(0,_op1);
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loadreg(1,_op2);
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loadconst(2,aint(_op3));
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end;
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constructor taicpu.op_reg_reg_sym_ofs(op : tasmop;_op1,_op2 : tregister; _op3: tasmsymbol;_op3ofs: longint);
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begin
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inherited create(op);
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ops:=3;
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loadreg(0,_op1);
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loadreg(1,_op2);
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loadsymbol(0,_op3,_op3ofs);
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end;
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constructor taicpu.op_reg_reg_ref(op : tasmop;_op1,_op2 : tregister; const _op3: treference);
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begin
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inherited create(op);
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ops:=3;
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loadreg(0,_op1);
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loadreg(1,_op2);
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loadref(2,_op3);
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end;
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constructor taicpu.op_reg_reg_shifterop(op : tasmop;_op1,_op2 : tregister;_op3 : tshifterop);
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begin
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inherited create(op);
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ops:=3;
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loadreg(0,_op1);
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loadreg(1,_op2);
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loadshifterop(2,_op3);
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end;
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constructor taicpu.op_reg_reg_reg_shifterop(op : tasmop;_op1,_op2,_op3 : tregister;_op4 : tshifterop);
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begin
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inherited create(op);
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ops:=4;
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loadreg(0,_op1);
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loadreg(1,_op2);
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loadreg(2,_op3);
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loadshifterop(3,_op4);
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end;
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constructor taicpu.op_cond_sym(op : tasmop;cond:TAsmCond;_op1 : tasmsymbol);
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begin
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inherited create(op);
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condition:=cond;
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ops:=1;
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loadsymbol(0,_op1,0);
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end;
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constructor taicpu.op_sym(op : tasmop;_op1 : tasmsymbol);
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begin
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inherited create(op);
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ops:=1;
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loadsymbol(0,_op1,0);
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end;
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constructor taicpu.op_sym_ofs(op : tasmop;_op1 : tasmsymbol;_op1ofs:longint);
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begin
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inherited create(op);
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ops:=1;
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loadsymbol(0,_op1,_op1ofs);
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end;
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constructor taicpu.op_reg_sym_ofs(op : tasmop;_op1 : tregister;_op2:tasmsymbol;_op2ofs : longint);
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begin
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inherited create(op);
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ops:=2;
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loadreg(0,_op1);
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loadsymbol(1,_op2,_op2ofs);
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end;
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constructor taicpu.op_sym_ofs_ref(op : tasmop;_op1 : tasmsymbol;_op1ofs:longint;const _op2 : treference);
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begin
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inherited create(op);
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ops:=2;
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loadsymbol(0,_op1,_op1ofs);
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loadref(1,_op2);
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end;
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function taicpu.is_same_reg_move(regtype: Tregistertype):boolean;
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begin
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{ allow the register allocator to remove unnecessary moves }
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result:=(
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((opcode=A_MOV) and (regtype = R_INTREGISTER)) or
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((opcode=A_FMOV) and (regtype = R_MMREGISTER))
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) and
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(oppostfix in [PF_None]) and
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(condition=C_None) and
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(ops=2) and
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(oper[0]^.typ=top_reg) and
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(oper[1]^.typ=top_reg) and
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(oper[0]^.reg=oper[1]^.reg);
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end;
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function spilling_create_load(const ref:treference;r:tregister):Taicpu;
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var
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op: tasmop;
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begin
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case getregtype(r) of
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R_INTREGISTER :
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result:=taicpu.op_reg_ref(A_LDR,r,ref);
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R_MMREGISTER :
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begin
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case getsubreg(r) of
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R_SUBFD:
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op:=A_LDR;
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R_SUBFS:
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op:=A_LDR;
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else
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internalerror(2009112905);
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end;
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result:=taicpu.op_reg_ref(op,r,ref);
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end;
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else
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internalerror(200401041);
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end;
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end;
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function spilling_create_store(r:tregister; const ref:treference):Taicpu;
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var
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op: tasmop;
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begin
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case getregtype(r) of
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R_INTREGISTER :
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result:=taicpu.op_reg_ref(A_STR,r,ref);
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R_MMREGISTER :
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begin
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case getsubreg(r) of
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R_SUBFD:
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op:=A_STR;
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R_SUBFS:
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op:=A_STR;
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else
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internalerror(2009112904);
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end;
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result:=taicpu.op_reg_ref(op,r,ref);
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end;
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else
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internalerror(200401041);
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end;
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end;
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function taicpu.spilling_get_operation_type(opnr: longint): topertype;
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begin
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case opcode of
|
|
A_ADC,A_ADD,A_AND,A_BIC,
|
|
A_EOR,A_CLZ,A_RBIT,
|
|
A_LDR,
|
|
A_MOV,A_MVN,A_MUL,
|
|
A_ORR,A_SBC,A_SUB,
|
|
A_UXT,A_SXT:
|
|
if opnr=0 then
|
|
result:=operand_write
|
|
else
|
|
result:=operand_read;
|
|
A_B,A_BL,
|
|
A_CMN,A_CMP,A_TST:
|
|
result:=operand_read;
|
|
A_STR:
|
|
{ important is what happens with the involved registers }
|
|
if opnr=0 then
|
|
result := operand_read
|
|
else
|
|
{ check for pre/post indexed }
|
|
result := operand_read;
|
|
else
|
|
internalerror(200403151);
|
|
end;
|
|
end;
|
|
|
|
|
|
procedure BuildInsTabCache;
|
|
var
|
|
i : longint;
|
|
begin
|
|
(* new(instabcache);
|
|
FillChar(instabcache^,sizeof(tinstabcache),$ff);
|
|
i:=0;
|
|
while (i<InsTabEntries) do
|
|
begin
|
|
if InsTabCache^[InsTab[i].Opcode]=-1 then
|
|
InsTabCache^[InsTab[i].Opcode]:=i;
|
|
inc(i);
|
|
end; *)
|
|
end;
|
|
|
|
|
|
procedure InitAsm;
|
|
begin
|
|
if not assigned(instabcache) then
|
|
BuildInsTabCache;
|
|
end;
|
|
|
|
|
|
procedure DoneAsm;
|
|
begin
|
|
if assigned(instabcache) then
|
|
begin
|
|
dispose(instabcache);
|
|
instabcache:=nil;
|
|
end;
|
|
end;
|
|
|
|
|
|
function setoppostfix(i : taicpu;pf : toppostfix) : taicpu;
|
|
begin
|
|
i.oppostfix:=pf;
|
|
result:=i;
|
|
end;
|
|
|
|
|
|
function setcondition(i : taicpu;c : tasmcond) : taicpu;
|
|
begin
|
|
i.condition:=c;
|
|
result:=i;
|
|
end;
|
|
|
|
|
|
Function SimpleGetNextInstruction(Current: tai; Var Next: tai): Boolean;
|
|
Begin
|
|
Current:=tai(Current.Next);
|
|
While Assigned(Current) And (Current.typ In SkipInstr) Do
|
|
Current:=tai(Current.Next);
|
|
Next:=Current;
|
|
If Assigned(Next) And Not(Next.typ In SkipInstr) Then
|
|
Result:=True
|
|
Else
|
|
Begin
|
|
Next:=Nil;
|
|
Result:=False;
|
|
End;
|
|
End;
|
|
|
|
|
|
(*
|
|
function armconstequal(hp1,hp2: tai): boolean;
|
|
begin
|
|
result:=false;
|
|
if hp1.typ<>hp2.typ then
|
|
exit;
|
|
case hp1.typ of
|
|
tai_const:
|
|
result:=
|
|
(tai_const(hp2).sym=tai_const(hp).sym) and
|
|
(tai_const(hp2).value=tai_const(hp).value) and
|
|
(tai(hp2.previous).typ=ait_label);
|
|
tai_const:
|
|
result:=
|
|
(tai_const(hp2).sym=tai_const(hp).sym) and
|
|
(tai_const(hp2).value=tai_const(hp).value) and
|
|
(tai(hp2.previous).typ=ait_label);
|
|
end;
|
|
end;
|
|
*)
|
|
|
|
procedure insertpcrelativedata(list,listtoinsert : TAsmList);
|
|
var
|
|
curinspos,
|
|
penalty,
|
|
lastinspos,
|
|
{ increased for every data element > 4 bytes inserted }
|
|
currentsize,
|
|
extradataoffset,
|
|
limit: longint;
|
|
curop : longint;
|
|
curtai : tai;
|
|
curdatatai,hp,hp2 : tai;
|
|
curdata : TAsmList;
|
|
l : tasmlabel;
|
|
doinsert,
|
|
removeref : boolean;
|
|
begin
|
|
(*
|
|
curdata:=TAsmList.create;
|
|
lastinspos:=-1;
|
|
curinspos:=0;
|
|
extradataoffset:=0;
|
|
limit:=1016;
|
|
curtai:=tai(list.first);
|
|
doinsert:=false;
|
|
while assigned(curtai) do
|
|
begin
|
|
{ instruction? }
|
|
case curtai.typ of
|
|
ait_instruction:
|
|
begin
|
|
{ walk through all operand of the instruction }
|
|
for curop:=0 to taicpu(curtai).ops-1 do
|
|
begin
|
|
{ reference? }
|
|
if (taicpu(curtai).oper[curop]^.typ=top_ref) then
|
|
begin
|
|
{ pc relative symbol? }
|
|
curdatatai:=tai(taicpu(curtai).oper[curop]^.ref^.symboldata);
|
|
if assigned(curdatatai) and
|
|
{ move only if we're at the first reference of a label }
|
|
not(tai_label(curdatatai).moved) then
|
|
begin
|
|
tai_label(curdatatai).moved:=true;
|
|
{ check if symbol already used. }
|
|
{ if yes, reuse the symbol }
|
|
hp:=tai(curdatatai.next);
|
|
removeref:=false;
|
|
if assigned(hp) then
|
|
begin
|
|
case hp.typ of
|
|
ait_const:
|
|
begin
|
|
if (tai_const(hp).consttype=aitconst_64bit) then
|
|
inc(extradataoffset);
|
|
end;
|
|
ait_comp_64bit,
|
|
ait_real_64bit:
|
|
begin
|
|
inc(extradataoffset);
|
|
end;
|
|
ait_real_80bit:
|
|
begin
|
|
inc(extradataoffset,2);
|
|
end;
|
|
end;
|
|
if (hp.typ=ait_const) then
|
|
begin
|
|
hp2:=tai(curdata.first);
|
|
while assigned(hp2) do
|
|
begin
|
|
{ if armconstequal(hp2,hp) then }
|
|
if (hp2.typ=ait_const) and (tai_const(hp2).sym=tai_const(hp).sym)
|
|
and (tai_const(hp2).value=tai_const(hp).value) and (tai(hp2.previous).typ=ait_label)
|
|
then
|
|
begin
|
|
with taicpu(curtai).oper[curop]^.ref^ do
|
|
begin
|
|
symboldata:=hp2.previous;
|
|
symbol:=tai_label(hp2.previous).labsym;
|
|
end;
|
|
removeref:=true;
|
|
break;
|
|
end;
|
|
hp2:=tai(hp2.next);
|
|
end;
|
|
end;
|
|
end;
|
|
{ move or remove symbol reference }
|
|
repeat
|
|
hp:=tai(curdatatai.next);
|
|
listtoinsert.remove(curdatatai);
|
|
if removeref then
|
|
curdatatai.free
|
|
else
|
|
curdata.concat(curdatatai);
|
|
curdatatai:=hp;
|
|
until (curdatatai=nil) or (curdatatai.typ=ait_label);
|
|
if lastinspos=-1 then
|
|
lastinspos:=curinspos;
|
|
end;
|
|
end;
|
|
end;
|
|
inc(curinspos);
|
|
end;
|
|
ait_align:
|
|
begin
|
|
{ code is always 4 byte aligned, so we don't have to take care of .align 2 which would
|
|
requires also incrementing curinspos by 1 }
|
|
inc(curinspos,(tai_align(curtai).aligntype div 4));
|
|
end;
|
|
ait_const:
|
|
begin
|
|
inc(curinspos);
|
|
if (tai_const(curtai).consttype=aitconst_64bit) then
|
|
inc(curinspos);
|
|
end;
|
|
ait_real_32bit:
|
|
begin
|
|
inc(curinspos);
|
|
end;
|
|
ait_comp_64bit,
|
|
ait_real_64bit:
|
|
begin
|
|
inc(curinspos,2);
|
|
end;
|
|
ait_real_80bit:
|
|
begin
|
|
inc(curinspos,3);
|
|
end;
|
|
end;
|
|
{ special case for case jump tables }
|
|
if SimpleGetNextInstruction(curtai,hp) and
|
|
(tai(hp).typ=ait_instruction) and
|
|
(taicpu(hp).opcode=A_LDR) and
|
|
(taicpu(hp).oper[0]^.typ=top_reg) and
|
|
(taicpu(hp).oper[0]^.reg=NR_PC) then
|
|
begin
|
|
penalty:=1;
|
|
hp:=tai(hp.next);
|
|
{ skip register allocations and comments inserted by the optimizer }
|
|
while assigned(hp) and (hp.typ in [ait_comment,ait_regalloc]) do
|
|
hp:=tai(hp.next);
|
|
while assigned(hp) and (hp.typ=ait_const) do
|
|
begin
|
|
inc(penalty);
|
|
hp:=tai(hp.next);
|
|
end;
|
|
end
|
|
else
|
|
penalty:=0;
|
|
|
|
{ FLD/FST VFP instructions have a limit of +/- 1024, not 4096 }
|
|
if SimpleGetNextInstruction(curtai,hp) and
|
|
(tai(hp).typ=ait_instruction) and
|
|
((taicpu(hp).opcode=A_FLDS) or
|
|
(taicpu(hp).opcode=A_FLDD)) then
|
|
limit:=254;
|
|
|
|
{ don't miss an insert }
|
|
doinsert:=doinsert or
|
|
(not(curdata.empty) and
|
|
(curinspos-lastinspos+penalty+extradataoffset>limit));
|
|
|
|
{ split only at real instructions else the test below fails }
|
|
if doinsert and (curtai.typ=ait_instruction) and
|
|
(
|
|
{ don't split loads of pc to lr and the following move }
|
|
not(
|
|
(taicpu(curtai).opcode=A_MOV) and
|
|
(taicpu(curtai).oper[0]^.typ=top_reg) and
|
|
(taicpu(curtai).oper[0]^.reg=NR_R14) and
|
|
(taicpu(curtai).oper[1]^.typ=top_reg) and
|
|
(taicpu(curtai).oper[1]^.reg=NR_PC)
|
|
)
|
|
) then
|
|
begin
|
|
lastinspos:=-1;
|
|
extradataoffset:=0;
|
|
limit:=1016;
|
|
doinsert:=false;
|
|
hp:=tai(curtai.next);
|
|
current_asmdata.getjumplabel(l);
|
|
curdata.insert(taicpu.op_sym(A_B,l));
|
|
curdata.concat(tai_label.create(l));
|
|
list.insertlistafter(curtai,curdata);
|
|
curtai:=hp;
|
|
end
|
|
else
|
|
curtai:=tai(curtai.next);
|
|
end;
|
|
list.concatlist(curdata);
|
|
curdata.free;
|
|
*)
|
|
end;
|
|
|
|
|
|
procedure finalizearmcode(list, listtoinsert: TAsmList);
|
|
begin
|
|
insertpcrelativedata(list, listtoinsert);
|
|
end;
|
|
|
|
procedure InsertPData;
|
|
var
|
|
prolog: TAsmList;
|
|
begin
|
|
prolog:=TAsmList.create;
|
|
new_section(prolog,sec_code,'FPC_EH_PROLOG',sizeof(pint),secorder_begin);
|
|
prolog.concat(Tai_const.Createname('_ARM_ExceptionHandler', 0));
|
|
prolog.concat(Tai_const.Create_32bit(0));
|
|
prolog.concat(Tai_symbol.Createname_global('FPC_EH_CODE_START',AT_DATA,0));
|
|
{ dummy function }
|
|
prolog.concat(taicpu.op_reg(A_BR,NR_X29));
|
|
current_asmdata.asmlists[al_start].insertList(prolog);
|
|
prolog.Free;
|
|
new_section(current_asmdata.asmlists[al_end],sec_pdata,'',sizeof(pint));
|
|
current_asmdata.asmlists[al_end].concat(Tai_const.Createname('FPC_EH_CODE_START', 0));
|
|
current_asmdata.asmlists[al_end].concat(Tai_const.Create_32bit(longint($ffffff01)));
|
|
end;
|
|
|
|
(*
|
|
Floating point instruction format information, taken from the linux kernel
|
|
ARM Floating Point Instruction Classes
|
|
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
|
|
|c o n d|1 1 0 P|U|u|W|L| Rn |v| Fd |0|0|0|1| o f f s e t | CPDT
|
|
|c o n d|1 1 0 P|U|w|W|L| Rn |x| Fd |0|0|1|0| o f f s e t | CPDT (copro 2)
|
|
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
|
|
|c o n d|1 1 1 0|a|b|c|d|e| Fn |j| Fd |0|0|0|1|f|g|h|0|i| Fm | CPDO
|
|
|c o n d|1 1 1 0|a|b|c|L|e| Fn | Rd |0|0|0|1|f|g|h|1|i| Fm | CPRT
|
|
|c o n d|1 1 1 0|a|b|c|1|e| Fn |1|1|1|1|0|0|0|1|f|g|h|1|i| Fm | comparisons
|
|
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
|
|
|
|
CPDT data transfer instructions
|
|
LDF, STF, LFM (copro 2), SFM (copro 2)
|
|
|
|
CPDO dyadic arithmetic instructions
|
|
ADF, MUF, SUF, RSF, DVF, RDF,
|
|
POW, RPW, RMF, FML, FDV, FRD, POL
|
|
|
|
CPDO monadic arithmetic instructions
|
|
MVF, MNF, ABS, RND, SQT, LOG, LGN, EXP,
|
|
SIN, COS, TAN, ASN, ACS, ATN, URD, NRM
|
|
|
|
CPRT joint arithmetic/data transfer instructions
|
|
FIX (arithmetic followed by load/store)
|
|
FLT (load/store followed by arithmetic)
|
|
CMF, CNF CMFE, CNFE (comparisons)
|
|
WFS, RFS (write/read floating point status register)
|
|
WFC, RFC (write/read floating point control register)
|
|
|
|
cond condition codes
|
|
P pre/post index bit: 0 = postindex, 1 = preindex
|
|
U up/down bit: 0 = stack grows down, 1 = stack grows up
|
|
W write back bit: 1 = update base register (Rn)
|
|
L load/store bit: 0 = store, 1 = load
|
|
Rn base register
|
|
Rd destination/source register
|
|
Fd floating point destination register
|
|
Fn floating point source register
|
|
Fm floating point source register or floating point constant
|
|
|
|
uv transfer length (TABLE 1)
|
|
wx register count (TABLE 2)
|
|
abcd arithmetic opcode (TABLES 3 & 4)
|
|
ef destination size (rounding precision) (TABLE 5)
|
|
gh rounding mode (TABLE 6)
|
|
j dyadic/monadic bit: 0 = dyadic, 1 = monadic
|
|
i constant bit: 1 = constant (TABLE 6)
|
|
*/
|
|
|
|
/*
|
|
TABLE 1
|
|
+-------------------------+---+---+---------+---------+
|
|
| Precision | u | v | FPSR.EP | length |
|
|
+-------------------------+---+---+---------+---------+
|
|
| Single | 0 | 0 | x | 1 words |
|
|
| Double | 1 | 1 | x | 2 words |
|
|
| Extended | 1 | 1 | x | 3 words |
|
|
| Packed decimal | 1 | 1 | 0 | 3 words |
|
|
| Expanded packed decimal | 1 | 1 | 1 | 4 words |
|
|
+-------------------------+---+---+---------+---------+
|
|
Note: x = don't care
|
|
*/
|
|
|
|
/*
|
|
TABLE 2
|
|
+---+---+---------------------------------+
|
|
| w | x | Number of registers to transfer |
|
|
+---+---+---------------------------------+
|
|
| 0 | 1 | 1 |
|
|
| 1 | 0 | 2 |
|
|
| 1 | 1 | 3 |
|
|
| 0 | 0 | 4 |
|
|
+---+---+---------------------------------+
|
|
*/
|
|
|
|
/*
|
|
TABLE 3: Dyadic Floating Point Opcodes
|
|
+---+---+---+---+----------+-----------------------+-----------------------+
|
|
| a | b | c | d | Mnemonic | Description | Operation |
|
|
+---+---+---+---+----------+-----------------------+-----------------------+
|
|
| 0 | 0 | 0 | 0 | ADF | Add | Fd := Fn + Fm |
|
|
| 0 | 0 | 0 | 1 | MUF | Multiply | Fd := Fn * Fm |
|
|
| 0 | 0 | 1 | 0 | SUF | Subtract | Fd := Fn - Fm |
|
|
| 0 | 0 | 1 | 1 | RSF | Reverse subtract | Fd := Fm - Fn |
|
|
| 0 | 1 | 0 | 0 | DVF | Divide | Fd := Fn / Fm |
|
|
| 0 | 1 | 0 | 1 | RDF | Reverse divide | Fd := Fm / Fn |
|
|
| 0 | 1 | 1 | 0 | POW | Power | Fd := Fn ^ Fm |
|
|
| 0 | 1 | 1 | 1 | RPW | Reverse power | Fd := Fm ^ Fn |
|
|
| 1 | 0 | 0 | 0 | RMF | Remainder | Fd := IEEE rem(Fn/Fm) |
|
|
| 1 | 0 | 0 | 1 | FML | Fast Multiply | Fd := Fn * Fm |
|
|
| 1 | 0 | 1 | 0 | FDV | Fast Divide | Fd := Fn / Fm |
|
|
| 1 | 0 | 1 | 1 | FRD | Fast reverse divide | Fd := Fm / Fn |
|
|
| 1 | 1 | 0 | 0 | POL | Polar angle (ArcTan2) | Fd := arctan2(Fn,Fm) |
|
|
| 1 | 1 | 0 | 1 | | undefined instruction | trap |
|
|
| 1 | 1 | 1 | 0 | | undefined instruction | trap |
|
|
| 1 | 1 | 1 | 1 | | undefined instruction | trap |
|
|
+---+---+---+---+----------+-----------------------+-----------------------+
|
|
Note: POW, RPW, POL are deprecated, and are available for backwards
|
|
compatibility only.
|
|
*/
|
|
|
|
/*
|
|
TABLE 4: Monadic Floating Point Opcodes
|
|
+---+---+---+---+----------+-----------------------+-----------------------+
|
|
| a | b | c | d | Mnemonic | Description | Operation |
|
|
+---+---+---+---+----------+-----------------------+-----------------------+
|
|
| 0 | 0 | 0 | 0 | MVF | Move | Fd := Fm |
|
|
| 0 | 0 | 0 | 1 | MNF | Move negated | Fd := - Fm |
|
|
| 0 | 0 | 1 | 0 | ABS | Absolute value | Fd := abs(Fm) |
|
|
| 0 | 0 | 1 | 1 | RND | Round to integer | Fd := int(Fm) |
|
|
| 0 | 1 | 0 | 0 | SQT | Square root | Fd := sqrt(Fm) |
|
|
| 0 | 1 | 0 | 1 | LOG | Log base 10 | Fd := log10(Fm) |
|
|
| 0 | 1 | 1 | 0 | LGN | Log base e | Fd := ln(Fm) |
|
|
| 0 | 1 | 1 | 1 | EXP | Exponent | Fd := e ^ Fm |
|
|
| 1 | 0 | 0 | 0 | SIN | Sine | Fd := sin(Fm) |
|
|
| 1 | 0 | 0 | 1 | COS | Cosine | Fd := cos(Fm) |
|
|
| 1 | 0 | 1 | 0 | TAN | Tangent | Fd := tan(Fm) |
|
|
| 1 | 0 | 1 | 1 | ASN | Arc Sine | Fd := arcsin(Fm) |
|
|
| 1 | 1 | 0 | 0 | ACS | Arc Cosine | Fd := arccos(Fm) |
|
|
| 1 | 1 | 0 | 1 | ATN | Arc Tangent | Fd := arctan(Fm) |
|
|
| 1 | 1 | 1 | 0 | URD | Unnormalized round | Fd := int(Fm) |
|
|
| 1 | 1 | 1 | 1 | NRM | Normalize | Fd := norm(Fm) |
|
|
+---+---+---+---+----------+-----------------------+-----------------------+
|
|
Note: LOG, LGN, EXP, SIN, COS, TAN, ASN, ACS, ATN are deprecated, and are
|
|
available for backwards compatibility only.
|
|
*/
|
|
|
|
/*
|
|
TABLE 5
|
|
+-------------------------+---+---+
|
|
| Rounding Precision | e | f |
|
|
+-------------------------+---+---+
|
|
| IEEE Single precision | 0 | 0 |
|
|
| IEEE Double precision | 0 | 1 |
|
|
| IEEE Extended precision | 1 | 0 |
|
|
| undefined (trap) | 1 | 1 |
|
|
+-------------------------+---+---+
|
|
*/
|
|
|
|
/*
|
|
TABLE 5
|
|
+---------------------------------+---+---+
|
|
| Rounding Mode | g | h |
|
|
+---------------------------------+---+---+
|
|
| Round to nearest (default) | 0 | 0 |
|
|
| Round toward plus infinity | 0 | 1 |
|
|
| Round toward negative infinity | 1 | 0 |
|
|
| Round toward zero | 1 | 1 |
|
|
+---------------------------------+---+---+
|
|
*)
|
|
function taicpu.GetString:string;
|
|
var
|
|
i : longint;
|
|
s : string;
|
|
addsize : boolean;
|
|
begin
|
|
s:='['+gas_op2str[opcode];
|
|
for i:=0 to ops-1 do
|
|
begin
|
|
with oper[i]^ do
|
|
begin
|
|
if i=0 then
|
|
s:=s+' '
|
|
else
|
|
s:=s+',';
|
|
{ type }
|
|
addsize:=false;
|
|
if (ot and OT_VREG)=OT_VREG then
|
|
s:=s+'vreg'
|
|
else
|
|
if (ot and OT_FPUREG)=OT_FPUREG then
|
|
s:=s+'fpureg'
|
|
else
|
|
if (ot and OT_REGISTER)=OT_REGISTER then
|
|
begin
|
|
s:=s+'reg';
|
|
addsize:=true;
|
|
end
|
|
else
|
|
if (ot and OT_REGLIST)=OT_REGLIST then
|
|
begin
|
|
s:=s+'reglist';
|
|
addsize:=false;
|
|
end
|
|
else
|
|
if (ot and OT_IMMEDIATE)=OT_IMMEDIATE then
|
|
begin
|
|
s:=s+'imm';
|
|
addsize:=true;
|
|
end
|
|
else
|
|
if (ot and OT_MEMORY)=OT_MEMORY then
|
|
begin
|
|
s:=s+'mem';
|
|
addsize:=true;
|
|
if (ot and OT_AM2)<>0 then
|
|
s:=s+' am2 ';
|
|
end
|
|
else
|
|
s:=s+'???';
|
|
{ size }
|
|
if addsize then
|
|
begin
|
|
if (ot and OT_BITS8)<>0 then
|
|
s:=s+'8'
|
|
else
|
|
if (ot and OT_BITS16)<>0 then
|
|
s:=s+'24'
|
|
else
|
|
if (ot and OT_BITS32)<>0 then
|
|
s:=s+'32'
|
|
else
|
|
if (ot and OT_BITSSHIFTER)<>0 then
|
|
s:=s+'shifter'
|
|
else
|
|
s:=s+'??';
|
|
{ signed }
|
|
if (ot and OT_SIGNED)<>0 then
|
|
s:=s+'s';
|
|
end;
|
|
end;
|
|
end;
|
|
GetString:=s+']';
|
|
end;
|
|
|
|
|
|
procedure taicpu.ResetPass1;
|
|
begin
|
|
{ we need to reset everything here, because the choosen insentry
|
|
can be invalid for a new situation where the previously optimized
|
|
insentry is not correct }
|
|
InsEntry:=nil;
|
|
InsSize:=0;
|
|
LastInsOffset:=-1;
|
|
end;
|
|
|
|
|
|
procedure taicpu.ResetPass2;
|
|
begin
|
|
{ we are here in a second pass, check if the instruction can be optimized }
|
|
if assigned(InsEntry) and
|
|
((InsEntry^.flags and IF_PASS2)<>0) then
|
|
begin
|
|
InsEntry:=nil;
|
|
InsSize:=0;
|
|
end;
|
|
LastInsOffset:=-1;
|
|
end;
|
|
|
|
|
|
function taicpu.CheckIfValid:boolean;
|
|
begin
|
|
Result:=False; { unimplemented }
|
|
end;
|
|
|
|
|
|
function taicpu.Pass1(objdata:TObjData):longint;
|
|
begin
|
|
Pass1:=0;
|
|
LastInsOffset:=-1;
|
|
end;
|
|
|
|
|
|
procedure taicpu.Pass2(objdata:TObjData);
|
|
begin
|
|
{ error in pass1 ? }
|
|
if insentry=nil then
|
|
exit;
|
|
current_filepos:=fileinfo;
|
|
{ Generate the instruction }
|
|
GenCode(objdata);
|
|
end;
|
|
|
|
|
|
procedure taicpu.ppuloadoper(ppufile:tcompilerppufile;var o:toper);
|
|
begin
|
|
end;
|
|
|
|
|
|
procedure taicpu.ppuwriteoper(ppufile:tcompilerppufile;const o:toper);
|
|
begin
|
|
end;
|
|
|
|
|
|
procedure taicpu.ppubuildderefimploper(var o:toper);
|
|
begin
|
|
end;
|
|
|
|
|
|
procedure taicpu.ppuderefoper(var o:toper);
|
|
begin
|
|
end;
|
|
|
|
|
|
function taicpu.InsEnd:longint;
|
|
begin
|
|
Result:=0; { unimplemented }
|
|
end;
|
|
|
|
|
|
procedure taicpu.create_ot(objdata:TObjData);
|
|
begin
|
|
end;
|
|
|
|
|
|
function taicpu.Matches(p:PInsEntry):longint;
|
|
begin
|
|
end;
|
|
|
|
|
|
function taicpu.calcsize(p:PInsEntry):shortint;
|
|
begin
|
|
result:=4;
|
|
end;
|
|
|
|
|
|
function taicpu.NeedAddrPrefix(opidx:byte):boolean;
|
|
begin
|
|
Result:=False; { unimplemented }
|
|
end;
|
|
|
|
|
|
procedure taicpu.Swapoperands;
|
|
begin
|
|
end;
|
|
|
|
|
|
function taicpu.FindInsentry(objdata:TObjData):boolean;
|
|
begin
|
|
end;
|
|
|
|
|
|
procedure taicpu.gencode(objdata:TObjData);
|
|
var
|
|
bytes : dword;
|
|
i_field : byte;
|
|
|
|
procedure setshifterop(op : byte);
|
|
begin
|
|
case oper[op]^.typ of
|
|
top_const:
|
|
begin
|
|
i_field:=1;
|
|
bytes:=bytes or dword(oper[op]^.val and $fff);
|
|
end;
|
|
top_reg:
|
|
begin
|
|
i_field:=0;
|
|
bytes:=bytes or (getsupreg(oper[op]^.reg) shl 16);
|
|
|
|
{ does a real shifter op follow? }
|
|
if (op+1<=op) and (oper[op+1]^.typ=top_shifterop) then
|
|
begin
|
|
end;
|
|
end;
|
|
else
|
|
internalerror(2005091103);
|
|
end;
|
|
end;
|
|
|
|
begin
|
|
bytes:=$0;
|
|
{ evaluate and set condition code }
|
|
|
|
{ condition code allowed? }
|
|
|
|
{ setup rest of the instruction }
|
|
case insentry^.code[0] of
|
|
#$08:
|
|
begin
|
|
{ set instruction code }
|
|
bytes:=bytes or (ord(insentry^.code[1]) shl 26);
|
|
bytes:=bytes or (ord(insentry^.code[2]) shl 21);
|
|
|
|
{ set destination }
|
|
bytes:=bytes or (getsupreg(oper[0]^.reg) shl 12);
|
|
|
|
{ create shifter op }
|
|
setshifterop(1);
|
|
|
|
{ set i field }
|
|
bytes:=bytes or (i_field shl 25);
|
|
|
|
{ set s if necessary }
|
|
if oppostfix=PF_S then
|
|
bytes:=bytes or (1 shl 20);
|
|
end;
|
|
#$ff:
|
|
internalerror(2005091101);
|
|
else
|
|
internalerror(2005091102);
|
|
end;
|
|
{ we're finished, write code }
|
|
objdata.writebytes(bytes,sizeof(bytes));
|
|
end;
|
|
|
|
|
|
{$ifdef dummy}
|
|
(*
|
|
static void gencode (long segment, long offset, int bits,
|
|
insn *ins, char *codes, long insn_end)
|
|
{
|
|
int has_S_code; /* S - setflag */
|
|
int has_B_code; /* B - setflag */
|
|
int has_T_code; /* T - setflag */
|
|
int has_W_code; /* ! => W flag */
|
|
int has_F_code; /* ^ => S flag */
|
|
int keep;
|
|
unsigned char c;
|
|
unsigned char bytes[4];
|
|
long data, size;
|
|
static int cc_code[] = /* bit pattern of cc */
|
|
{ /* order as enum in */
|
|
0x0E, 0x03, 0x02, 0x00, /* nasm.h */
|
|
0x0A, 0x0C, 0x08, 0x0D,
|
|
0x09, 0x0B, 0x04, 0x01,
|
|
0x05, 0x07, 0x06,
|
|
};
|
|
|
|
|
|
#ifdef DEBUG
|
|
static char *CC[] =
|
|
{ /* condition code names */
|
|
"AL", "CC", "CS", "EQ",
|
|
"GE", "GT", "HI", "LE",
|
|
"LS", "LT", "MI", "NE",
|
|
"PL", "VC", "VS", "",
|
|
"S"
|
|
};
|
|
|
|
|
|
has_S_code = (ins->condition & C_SSETFLAG);
|
|
has_B_code = (ins->condition & C_BSETFLAG);
|
|
has_T_code = (ins->condition & C_TSETFLAG);
|
|
has_W_code = (ins->condition & C_EXSETFLAG);
|
|
has_F_code = (ins->condition & C_FSETFLAG);
|
|
ins->condition = (ins->condition & 0x0F);
|
|
|
|
|
|
if (rt_debug)
|
|
{
|
|
printf ("gencode: instruction: %s%s", insn_names[ins->opcode],
|
|
CC[ins->condition & 0x0F]);
|
|
if (has_S_code)
|
|
printf ("S");
|
|
if (has_B_code)
|
|
printf ("B");
|
|
if (has_T_code)
|
|
printf ("T");
|
|
if (has_W_code)
|
|
printf ("!");
|
|
if (has_F_code)
|
|
printf ("^");
|
|
|
|
printf ("\n");
|
|
|
|
c = *codes;
|
|
|
|
printf (" (%d) decode - '0x%02X'\n", ins->operands, c);
|
|
|
|
|
|
bytes[0] = 0xB;
|
|
bytes[1] = 0xE;
|
|
bytes[2] = 0xE;
|
|
bytes[3] = 0xF;
|
|
}
|
|
|
|
// First condition code in upper nibble
|
|
if (ins->condition < C_NONE)
|
|
{
|
|
c = cc_code[ins->condition] << 4;
|
|
}
|
|
else
|
|
{
|
|
c = cc_code[C_AL] << 4; // is often ALWAYS but not always
|
|
}
|
|
|
|
|
|
switch (keep = *codes)
|
|
{
|
|
case 1:
|
|
// B, BL
|
|
++codes;
|
|
c |= *codes++;
|
|
bytes[0] = c;
|
|
|
|
if (ins->oprs[0].segment != segment)
|
|
{
|
|
// fais une relocation
|
|
c = 1;
|
|
data = 0; // Let the linker locate ??
|
|
}
|
|
else
|
|
{
|
|
c = 0;
|
|
data = ins->oprs[0].offset - (offset + 8);
|
|
|
|
if (data % 4)
|
|
{
|
|
errfunc (ERR_NONFATAL, "offset not aligned on 4 bytes");
|
|
}
|
|
}
|
|
|
|
if (data >= 0x1000)
|
|
{
|
|
errfunc (ERR_NONFATAL, "too long offset");
|
|
}
|
|
|
|
data = data >> 2;
|
|
bytes[1] = (data >> 16) & 0xFF;
|
|
bytes[2] = (data >> 8) & 0xFF;
|
|
bytes[3] = (data ) & 0xFF;
|
|
|
|
if (c == 1)
|
|
{
|
|
// out (offset, segment, &bytes[0], OUT_RAWDATA+1, NO_SEG, NO_SEG);
|
|
out (offset, segment, &bytes[0], OUT_REL3ADR+4, ins->oprs[0].segment, NO_SEG);
|
|
}
|
|
else
|
|
{
|
|
out (offset, segment, &bytes[0], OUT_RAWDATA+4, NO_SEG, NO_SEG);
|
|
}
|
|
return;
|
|
|
|
case 2:
|
|
// SWI
|
|
++codes;
|
|
c |= *codes++;
|
|
bytes[0] = c;
|
|
data = ins->oprs[0].offset;
|
|
bytes[1] = (data >> 16) & 0xFF;
|
|
bytes[2] = (data >> 8) & 0xFF;
|
|
bytes[3] = (data) & 0xFF;
|
|
out (offset, segment, &bytes, OUT_RAWDATA+4, NO_SEG, NO_SEG);
|
|
return;
|
|
case 3:
|
|
// BX
|
|
++codes;
|
|
c |= *codes++;
|
|
bytes[0] = c;
|
|
bytes[1] = *codes++;
|
|
bytes[2] = *codes++;
|
|
bytes[3] = *codes++;
|
|
c = regval (&ins->oprs[0],1);
|
|
if (c == 15) // PC
|
|
{
|
|
errfunc (ERR_WARNING, "'BX' with R15 has undefined behaviour");
|
|
}
|
|
else if (c > 15)
|
|
{
|
|
errfunc (ERR_NONFATAL, "Illegal register specified for 'BX'");
|
|
}
|
|
|
|
bytes[3] |= (c & 0x0F);
|
|
out (offset, segment, bytes, OUT_RAWDATA+4, NO_SEG, NO_SEG);
|
|
return;
|
|
|
|
case 4: // AND Rd,Rn,Rm
|
|
case 5: // AND Rd,Rn,Rm,<shift>Rs
|
|
case 6: // AND Rd,Rn,Rm,<shift>imm
|
|
case 7: // AND Rd,Rn,<shift>imm
|
|
++codes;
|
|
#ifdef DEBUG
|
|
if (rt_debug)
|
|
{
|
|
printf (" decode - '0x%02X'\n", keep);
|
|
printf (" code - '0x%02X'\n", (unsigned char) ( *codes));
|
|
}
|
|
#endif
|
|
bytes[0] = c | *codes;
|
|
++codes;
|
|
|
|
bytes[1] = *codes;
|
|
if (has_S_code)
|
|
bytes[1] |= 0x10;
|
|
c = regval (&ins->oprs[1],1);
|
|
// Rn in low nibble
|
|
bytes[1] |= c;
|
|
|
|
// Rd in high nibble
|
|
bytes[2] = regval (&ins->oprs[0],1) << 4;
|
|
|
|
if (keep != 7)
|
|
{
|
|
// Rm in low nibble
|
|
bytes[3] = regval (&ins->oprs[2],1);
|
|
}
|
|
|
|
// Shifts if any
|
|
if (keep == 5 || keep == 6)
|
|
{
|
|
// Shift in bytes 2 and 3
|
|
if (keep == 5)
|
|
{
|
|
// Rs
|
|
c = regval (&ins->oprs[3],1);
|
|
bytes[2] |= c;
|
|
|
|
c = 0x10; // Set bit 4 in byte[3]
|
|
}
|
|
if (keep == 6)
|
|
{
|
|
c = (ins->oprs[3].offset) & 0x1F;
|
|
|
|
// #imm
|
|
bytes[2] |= c >> 1;
|
|
if (c & 0x01)
|
|
{
|
|
bytes[3] |= 0x80;
|
|
}
|
|
c = 0; // Clr bit 4 in byte[3]
|
|
}
|
|
// <shift>
|
|
c |= shiftval (&ins->oprs[3]) << 5;
|
|
|
|
bytes[3] |= c;
|
|
}
|
|
|
|
// reg,reg,imm
|
|
if (keep == 7)
|
|
{
|
|
int shimm;
|
|
|
|
shimm = imm_shift (ins->oprs[2].offset);
|
|
|
|
if (shimm == -1)
|
|
{
|
|
errfunc (ERR_NONFATAL, "cannot create that constant");
|
|
}
|
|
bytes[3] = shimm & 0xFF;
|
|
bytes[2] |= (shimm & 0xF00) >> 8;
|
|
}
|
|
|
|
out (offset, segment, bytes, OUT_RAWDATA+4, NO_SEG, NO_SEG);
|
|
return;
|
|
|
|
case 8: // MOV Rd,Rm
|
|
case 9: // MOV Rd,Rm,<shift>Rs
|
|
case 0xA: // MOV Rd,Rm,<shift>imm
|
|
case 0xB: // MOV Rd,<shift>imm
|
|
++codes;
|
|
#ifdef DEBUG
|
|
if (rt_debug)
|
|
{
|
|
printf (" decode - '0x%02X'\n", keep);
|
|
printf (" code - '0x%02X'\n", (unsigned char) ( *codes));
|
|
}
|
|
#endif
|
|
bytes[0] = c | *codes;
|
|
++codes;
|
|
|
|
bytes[1] = *codes;
|
|
if (has_S_code)
|
|
bytes[1] |= 0x10;
|
|
|
|
// Rd in high nibble
|
|
bytes[2] = regval (&ins->oprs[0],1) << 4;
|
|
|
|
if (keep != 0x0B)
|
|
{
|
|
// Rm in low nibble
|
|
bytes[3] = regval (&ins->oprs[1],1);
|
|
}
|
|
|
|
// Shifts if any
|
|
if (keep == 0x09 || keep == 0x0A)
|
|
{
|
|
// Shift in bytes 2 and 3
|
|
if (keep == 0x09)
|
|
{
|
|
// Rs
|
|
c = regval (&ins->oprs[2],1);
|
|
bytes[2] |= c;
|
|
|
|
c = 0x10; // Set bit 4 in byte[3]
|
|
}
|
|
if (keep == 0x0A)
|
|
{
|
|
c = (ins->oprs[2].offset) & 0x1F;
|
|
|
|
// #imm
|
|
bytes[2] |= c >> 1;
|
|
if (c & 0x01)
|
|
{
|
|
bytes[3] |= 0x80;
|
|
}
|
|
c = 0; // Clr bit 4 in byte[3]
|
|
}
|
|
// <shift>
|
|
c |= shiftval (&ins->oprs[2]) << 5;
|
|
|
|
bytes[3] |= c;
|
|
}
|
|
|
|
// reg,imm
|
|
if (keep == 0x0B)
|
|
{
|
|
int shimm;
|
|
|
|
shimm = imm_shift (ins->oprs[1].offset);
|
|
|
|
if (shimm == -1)
|
|
{
|
|
errfunc (ERR_NONFATAL, "cannot create that constant");
|
|
}
|
|
bytes[3] = shimm & 0xFF;
|
|
bytes[2] |= (shimm & 0xF00) >> 8;
|
|
}
|
|
|
|
out (offset, segment, bytes, OUT_RAWDATA+4, NO_SEG, NO_SEG);
|
|
return;
|
|
|
|
|
|
case 0xC: // CMP Rn,Rm
|
|
case 0xD: // CMP Rn,Rm,<shift>Rs
|
|
case 0xE: // CMP Rn,Rm,<shift>imm
|
|
case 0xF: // CMP Rn,<shift>imm
|
|
++codes;
|
|
|
|
bytes[0] = c | *codes++;
|
|
|
|
bytes[1] = *codes;
|
|
|
|
// Implicit S code
|
|
bytes[1] |= 0x10;
|
|
|
|
c = regval (&ins->oprs[0],1);
|
|
// Rn in low nibble
|
|
bytes[1] |= c;
|
|
|
|
// No destination
|
|
bytes[2] = 0;
|
|
|
|
if (keep != 0x0B)
|
|
{
|
|
// Rm in low nibble
|
|
bytes[3] = regval (&ins->oprs[1],1);
|
|
}
|
|
|
|
// Shifts if any
|
|
if (keep == 0x0D || keep == 0x0E)
|
|
{
|
|
// Shift in bytes 2 and 3
|
|
if (keep == 0x0D)
|
|
{
|
|
// Rs
|
|
c = regval (&ins->oprs[2],1);
|
|
bytes[2] |= c;
|
|
|
|
c = 0x10; // Set bit 4 in byte[3]
|
|
}
|
|
if (keep == 0x0E)
|
|
{
|
|
c = (ins->oprs[2].offset) & 0x1F;
|
|
|
|
// #imm
|
|
bytes[2] |= c >> 1;
|
|
if (c & 0x01)
|
|
{
|
|
bytes[3] |= 0x80;
|
|
}
|
|
c = 0; // Clr bit 4 in byte[3]
|
|
}
|
|
// <shift>
|
|
c |= shiftval (&ins->oprs[2]) << 5;
|
|
|
|
bytes[3] |= c;
|
|
}
|
|
|
|
// reg,imm
|
|
if (keep == 0x0F)
|
|
{
|
|
int shimm;
|
|
|
|
shimm = imm_shift (ins->oprs[1].offset);
|
|
|
|
if (shimm == -1)
|
|
{
|
|
errfunc (ERR_NONFATAL, "cannot create that constant");
|
|
}
|
|
bytes[3] = shimm & 0xFF;
|
|
bytes[2] |= (shimm & 0xF00) >> 8;
|
|
}
|
|
|
|
out (offset, segment, bytes, OUT_RAWDATA+4, NO_SEG, NO_SEG);
|
|
return;
|
|
|
|
case 0x10: // MRS Rd,<psr>
|
|
++codes;
|
|
|
|
bytes[0] = c | *codes++;
|
|
|
|
bytes[1] = *codes++;
|
|
|
|
// Rd
|
|
c = regval (&ins->oprs[0],1);
|
|
|
|
bytes[2] = c << 4;
|
|
|
|
bytes[3] = 0;
|
|
|
|
c = ins->oprs[1].basereg;
|
|
|
|
if (c == R_CPSR || c == R_SPSR)
|
|
{
|
|
if (c == R_SPSR)
|
|
{
|
|
bytes[1] |= 0x40;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
errfunc (ERR_NONFATAL, "CPSR or SPSR expected");
|
|
}
|
|
|
|
out (offset, segment, bytes, OUT_RAWDATA+4, NO_SEG, NO_SEG);
|
|
|
|
return;
|
|
|
|
case 0x11: // MSR <psr>,Rm
|
|
case 0x12: // MSR <psrf>,Rm
|
|
case 0x13: // MSR <psrf>,#expression
|
|
++codes;
|
|
|
|
bytes[0] = c | *codes++;
|
|
|
|
bytes[1] = *codes++;
|
|
|
|
bytes[2] = *codes;
|
|
|
|
|
|
if (keep == 0x11 || keep == 0x12)
|
|
{
|
|
// Rm
|
|
c = regval (&ins->oprs[1],1);
|
|
|
|
bytes[3] = c;
|
|
}
|
|
else
|
|
{
|
|
int shimm;
|
|
|
|
shimm = imm_shift (ins->oprs[1].offset);
|
|
|
|
if (shimm == -1)
|
|
{
|
|
errfunc (ERR_NONFATAL, "cannot create that constant");
|
|
}
|
|
bytes[3] = shimm & 0xFF;
|
|
bytes[2] |= (shimm & 0xF00) >> 8;
|
|
}
|
|
|
|
c = ins->oprs[0].basereg;
|
|
|
|
if ( keep == 0x11)
|
|
{
|
|
if ( c == R_CPSR || c == R_SPSR)
|
|
{
|
|
if ( c== R_SPSR)
|
|
{
|
|
bytes[1] |= 0x40;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
errfunc (ERR_NONFATAL, "CPSR or SPSR expected");
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if ( c == R_CPSR_FLG || c == R_SPSR_FLG)
|
|
{
|
|
if ( c== R_SPSR_FLG)
|
|
{
|
|
bytes[1] |= 0x40;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
errfunc (ERR_NONFATAL, "CPSR_flg or SPSR_flg expected");
|
|
}
|
|
}
|
|
break;
|
|
|
|
case 0x14: // MUL Rd,Rm,Rs
|
|
case 0x15: // MULA Rd,Rm,Rs,Rn
|
|
++codes;
|
|
|
|
bytes[0] = c | *codes++;
|
|
|
|
bytes[1] = *codes++;
|
|
|
|
bytes[3] = *codes;
|
|
|
|
// Rd
|
|
bytes[1] |= regval (&ins->oprs[0],1);
|
|
if (has_S_code)
|
|
bytes[1] |= 0x10;
|
|
|
|
// Rm
|
|
bytes[3] |= regval (&ins->oprs[1],1);
|
|
|
|
// Rs
|
|
bytes[2] = regval (&ins->oprs[2],1);
|
|
|
|
if (keep == 0x15)
|
|
{
|
|
bytes[2] |= regval (&ins->oprs[3],1) << 4;
|
|
}
|
|
break;
|
|
|
|
case 0x16: // SMLAL RdHi,RdLo,Rm,Rs
|
|
++codes;
|
|
|
|
bytes[0] = c | *codes++;
|
|
|
|
bytes[1] = *codes++;
|
|
|
|
bytes[3] = *codes;
|
|
|
|
// RdHi
|
|
bytes[1] |= regval (&ins->oprs[1],1);
|
|
if (has_S_code)
|
|
bytes[1] |= 0x10;
|
|
|
|
// RdLo
|
|
bytes[2] = regval (&ins->oprs[0],1) << 4;
|
|
// Rm
|
|
bytes[3] |= regval (&ins->oprs[2],1);
|
|
|
|
// Rs
|
|
bytes[2] |= regval (&ins->oprs[3],1);
|
|
|
|
break;
|
|
|
|
case 0x17: // LDR Rd, expression
|
|
++codes;
|
|
|
|
bytes[0] = c | *codes++;
|
|
|
|
bytes[1] = *codes++;
|
|
|
|
// Rd
|
|
bytes[2] = regval (&ins->oprs[0],1) << 4;
|
|
if (has_B_code)
|
|
bytes[1] |= 0x40;
|
|
if (has_T_code)
|
|
{
|
|
errfunc (ERR_NONFATAL, "'T' not allowed in pre-index mode");
|
|
}
|
|
if (has_W_code)
|
|
{
|
|
errfunc (ERR_NONFATAL, "'!' not allowed");
|
|
}
|
|
|
|
// Rn - implicit R15
|
|
bytes[1] |= 0xF;
|
|
|
|
if (ins->oprs[1].segment != segment)
|
|
{
|
|
errfunc (ERR_NONFATAL, "label not in same segment");
|
|
}
|
|
|
|
data = ins->oprs[1].offset - (offset + 8);
|
|
|
|
if (data < 0)
|
|
{
|
|
data = -data;
|
|
}
|
|
else
|
|
{
|
|
bytes[1] |= 0x80;
|
|
}
|
|
|
|
if (data >= 0x1000)
|
|
{
|
|
errfunc (ERR_NONFATAL, "too long offset");
|
|
}
|
|
|
|
bytes[2] |= ((data & 0xF00) >> 8);
|
|
bytes[3] = data & 0xFF;
|
|
break;
|
|
|
|
case 0x18: // LDR Rd, [Rn]
|
|
++codes;
|
|
|
|
bytes[0] = c | *codes++;
|
|
|
|
bytes[1] = *codes++;
|
|
|
|
// Rd
|
|
bytes[2] = regval (&ins->oprs[0],1) << 4;
|
|
if (has_B_code)
|
|
bytes[1] |= 0x40;
|
|
if (has_T_code)
|
|
{
|
|
bytes[1] |= 0x20; // write-back
|
|
}
|
|
else
|
|
{
|
|
bytes[0] |= 0x01; // implicit pre-index mode
|
|
}
|
|
|
|
if (has_W_code)
|
|
{
|
|
bytes[1] |= 0x20; // write-back
|
|
}
|
|
|
|
// Rn
|
|
c = regval (&ins->oprs[1],1);
|
|
bytes[1] |= c;
|
|
|
|
if (c == 0x15) // R15
|
|
data = -8;
|
|
else
|
|
data = 0;
|
|
|
|
if (data < 0)
|
|
{
|
|
data = -data;
|
|
}
|
|
else
|
|
{
|
|
bytes[1] |= 0x80;
|
|
}
|
|
|
|
bytes[2] |= ((data & 0xF00) >> 8);
|
|
bytes[3] = data & 0xFF;
|
|
break;
|
|
|
|
case 0x19: // LDR Rd, [Rn,#expression]
|
|
case 0x20: // LDR Rd, [Rn,Rm]
|
|
case 0x21: // LDR Rd, [Rn,Rm,shift]
|
|
++codes;
|
|
|
|
bytes[0] = c | *codes++;
|
|
|
|
bytes[1] = *codes++;
|
|
|
|
// Rd
|
|
bytes[2] = regval (&ins->oprs[0],1) << 4;
|
|
if (has_B_code)
|
|
bytes[1] |= 0x40;
|
|
|
|
// Rn
|
|
c = regval (&ins->oprs[1],1);
|
|
bytes[1] |= c;
|
|
|
|
if (ins->oprs[ins->operands-1].bracket) // FIXME: Bracket on last operand -> pre-index <--
|
|
{
|
|
bytes[0] |= 0x01; // pre-index mode
|
|
if (has_W_code)
|
|
{
|
|
bytes[1] |= 0x20;
|
|
}
|
|
if (has_T_code)
|
|
{
|
|
errfunc (ERR_NONFATAL, "'T' not allowed in pre-index mode");
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if (has_T_code) // Forced write-back in post-index mode
|
|
{
|
|
bytes[1] |= 0x20;
|
|
}
|
|
if (has_W_code)
|
|
{
|
|
errfunc (ERR_NONFATAL, "'!' not allowed in post-index mode");
|
|
}
|
|
}
|
|
|
|
if (keep == 0x19)
|
|
{
|
|
data = ins->oprs[2].offset;
|
|
|
|
if (data < 0)
|
|
{
|
|
data = -data;
|
|
}
|
|
else
|
|
{
|
|
bytes[1] |= 0x80;
|
|
}
|
|
|
|
if (data >= 0x1000)
|
|
{
|
|
errfunc (ERR_NONFATAL, "too long offset");
|
|
}
|
|
|
|
bytes[2] |= ((data & 0xF00) >> 8);
|
|
bytes[3] = data & 0xFF;
|
|
}
|
|
else
|
|
{
|
|
if (ins->oprs[2].minus == 0)
|
|
{
|
|
bytes[1] |= 0x80;
|
|
}
|
|
c = regval (&ins->oprs[2],1);
|
|
bytes[3] = c;
|
|
|
|
if (keep == 0x21)
|
|
{
|
|
c = ins->oprs[3].offset;
|
|
if (c > 0x1F)
|
|
{
|
|
errfunc (ERR_NONFATAL, "too large shiftvalue");
|
|
c = c & 0x1F;
|
|
}
|
|
|
|
bytes[2] |= c >> 1;
|
|
if (c & 0x01)
|
|
{
|
|
bytes[3] |= 0x80;
|
|
}
|
|
bytes[3] |= shiftval (&ins->oprs[3]) << 5;
|
|
}
|
|
}
|
|
|
|
break;
|
|
|
|
case 0x22: // LDRH Rd, expression
|
|
++codes;
|
|
|
|
bytes[0] = c | 0x01; // Implicit pre-index
|
|
|
|
bytes[1] = *codes++;
|
|
|
|
// Rd
|
|
bytes[2] = regval (&ins->oprs[0],1) << 4;
|
|
|
|
// Rn - implicit R15
|
|
bytes[1] |= 0xF;
|
|
|
|
if (ins->oprs[1].segment != segment)
|
|
{
|
|
errfunc (ERR_NONFATAL, "label not in same segment");
|
|
}
|
|
|
|
data = ins->oprs[1].offset - (offset + 8);
|
|
|
|
if (data < 0)
|
|
{
|
|
data = -data;
|
|
}
|
|
else
|
|
{
|
|
bytes[1] |= 0x80;
|
|
}
|
|
|
|
if (data >= 0x100)
|
|
{
|
|
errfunc (ERR_NONFATAL, "too long offset");
|
|
}
|
|
bytes[3] = *codes++;
|
|
|
|
bytes[2] |= ((data & 0xF0) >> 4);
|
|
bytes[3] |= data & 0xF;
|
|
break;
|
|
|
|
case 0x23: // LDRH Rd, Rn
|
|
++codes;
|
|
|
|
bytes[0] = c | 0x01; // Implicit pre-index
|
|
|
|
bytes[1] = *codes++;
|
|
|
|
// Rd
|
|
bytes[2] = regval (&ins->oprs[0],1) << 4;
|
|
|
|
// Rn
|
|
c = regval (&ins->oprs[1],1);
|
|
bytes[1] |= c;
|
|
|
|
if (c == 0x15) // R15
|
|
data = -8;
|
|
else
|
|
data = 0;
|
|
|
|
if (data < 0)
|
|
{
|
|
data = -data;
|
|
}
|
|
else
|
|
{
|
|
bytes[1] |= 0x80;
|
|
}
|
|
|
|
if (data >= 0x100)
|
|
{
|
|
errfunc (ERR_NONFATAL, "too long offset");
|
|
}
|
|
bytes[3] = *codes++;
|
|
|
|
bytes[2] |= ((data & 0xF0) >> 4);
|
|
bytes[3] |= data & 0xF;
|
|
break;
|
|
|
|
case 0x24: // LDRH Rd, Rn, expression
|
|
case 0x25: // LDRH Rd, Rn, Rm
|
|
++codes;
|
|
|
|
bytes[0] = c;
|
|
|
|
bytes[1] = *codes++;
|
|
|
|
// Rd
|
|
bytes[2] = regval (&ins->oprs[0],1) << 4;
|
|
|
|
// Rn
|
|
c = regval (&ins->oprs[1],1);
|
|
bytes[1] |= c;
|
|
|
|
if (ins->oprs[ins->operands-1].bracket) // FIXME: Bracket on last operand -> pre-index <--
|
|
{
|
|
bytes[0] |= 0x01; // pre-index mode
|
|
if (has_W_code)
|
|
{
|
|
bytes[1] |= 0x20;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if (has_W_code)
|
|
{
|
|
errfunc (ERR_NONFATAL, "'!' not allowed in post-index mode");
|
|
}
|
|
}
|
|
|
|
bytes[3] = *codes++;
|
|
|
|
if (keep == 0x24)
|
|
{
|
|
data = ins->oprs[2].offset;
|
|
|
|
if (data < 0)
|
|
{
|
|
data = -data;
|
|
}
|
|
else
|
|
{
|
|
bytes[1] |= 0x80;
|
|
}
|
|
|
|
if (data >= 0x100)
|
|
{
|
|
errfunc (ERR_NONFATAL, "too long offset");
|
|
}
|
|
|
|
bytes[2] |= ((data & 0xF0) >> 4);
|
|
bytes[3] |= data & 0xF;
|
|
}
|
|
else
|
|
{
|
|
if (ins->oprs[2].minus == 0)
|
|
{
|
|
bytes[1] |= 0x80;
|
|
}
|
|
c = regval (&ins->oprs[2],1);
|
|
bytes[3] |= c;
|
|
|
|
}
|
|
break;
|
|
|
|
case 0x26: // LDM/STM Rn, {reg-list}
|
|
++codes;
|
|
|
|
bytes[0] = c;
|
|
|
|
bytes[0] |= ( *codes >> 4) & 0xF;
|
|
bytes[1] = ( *codes << 4) & 0xF0;
|
|
++codes;
|
|
|
|
if (has_W_code)
|
|
{
|
|
bytes[1] |= 0x20;
|
|
}
|
|
if (has_F_code)
|
|
{
|
|
bytes[1] |= 0x40;
|
|
}
|
|
|
|
// Rn
|
|
bytes[1] |= regval (&ins->oprs[0],1);
|
|
|
|
data = ins->oprs[1].basereg;
|
|
|
|
bytes[2] = ((data >> 8) & 0xFF);
|
|
bytes[3] = (data & 0xFF);
|
|
|
|
break;
|
|
|
|
case 0x27: // SWP Rd, Rm, [Rn]
|
|
++codes;
|
|
|
|
bytes[0] = c;
|
|
|
|
bytes[0] |= *codes++;
|
|
|
|
bytes[1] = regval (&ins->oprs[2],1);
|
|
if (has_B_code)
|
|
{
|
|
bytes[1] |= 0x40;
|
|
}
|
|
bytes[2] = regval (&ins->oprs[0],1) << 4;
|
|
bytes[3] = *codes++;
|
|
bytes[3] |= regval (&ins->oprs[1],1);
|
|
break;
|
|
|
|
default:
|
|
errfunc (ERR_FATAL, "unknown decoding of instruction");
|
|
|
|
bytes[0] = c;
|
|
// And a fix nibble
|
|
++codes;
|
|
bytes[0] |= *codes++;
|
|
|
|
if ( *codes == 0x01) // An I bit
|
|
{
|
|
|
|
}
|
|
if ( *codes == 0x02) // An I bit
|
|
{
|
|
|
|
}
|
|
++codes;
|
|
}
|
|
out (offset, segment, bytes, OUT_RAWDATA+4, NO_SEG, NO_SEG);
|
|
}
|
|
|
|
*)
|
|
{$endif dummy}
|
|
|
|
begin
|
|
cai_align:=tai_align;
|
|
end.
|
|
|