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e2a744e19b
ARM can not reference an arbitrary offset so it needs some special handling if the offset goes beyond abs(4095). The code for do_spill_read and do_spill written used to be very similar. I've partially factored out the code into spilling_create_load_store. The former code loaded the offset from a constant pool, which is a waste of memory-bandwidth and cache lines. The new code tries to find a way to adjust the baseregister so the memory location can be reached more easily, this allows us to handle at least +-1MB with just a single additional ADD or SUB instruction. If that fails we'll resort to the normal constant loading code, which on it's own will fallback to loading the constant from a constant-pool. So instead of: ldr r1, =16388 ldr r0, [r13, r1] which will at least uses 4 cycles (2 Instruction cycles + 2 stall cycles) on most cores. We try to generate: add r1, r13, #16384 ldr r0, [r1, #4] which most armv5+ cores will execute in 2 cycles. We'll also save on DCache usage. git-svn-id: trunk@21889 -
398 lines
14 KiB
ObjectPascal
398 lines
14 KiB
ObjectPascal
{
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Copyright (c) 1998-2003 by Florian Klaempfl
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This unit implements the arm specific class for the register
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allocator
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit rgcpu;
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{$i fpcdefs.inc}
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interface
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uses
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aasmbase,aasmtai,aasmdata,aasmcpu,
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cgbase,cgutils,
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cpubase,
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rgobj;
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type
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trgcpu = class(trgobj)
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private
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procedure spilling_create_load_store(list: TAsmList; pos: tai; const spilltemp:treference;tempreg:tregister; is_store: boolean);
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public
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procedure do_spill_read(list:TAsmList;pos:tai;const spilltemp:treference;tempreg:tregister);override;
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procedure do_spill_written(list:TAsmList;pos:tai;const spilltemp:treference;tempreg:tregister);override;
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procedure add_constraints(reg:tregister);override;
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function get_spill_subreg(r:tregister) : tsubregister;override;
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end;
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trgcputhumb2 = class(trgobj)
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procedure do_spill_read(list:TAsmList;pos:tai;const spilltemp:treference;tempreg:tregister);override;
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procedure do_spill_written(list:TAsmList;pos:tai;const spilltemp:treference;tempreg:tregister);override;
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end;
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trgintcputhumb2 = class(trgcputhumb2)
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procedure add_cpu_interferences(p : tai);override;
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end;
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trgintcpu = class(trgcpu)
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procedure add_cpu_interferences(p : tai);override;
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end;
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implementation
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uses
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verbose, cutils,globtype,globals,cpuinfo,
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cgobj,
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procinfo;
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procedure trgintcputhumb2.add_cpu_interferences(p: tai);
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var
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r : tregister;
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begin
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if p.typ=ait_instruction then
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begin
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case taicpu(p).opcode of
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A_ADD:
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begin
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if taicpu(p).ops = 3 then
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begin
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if (taicpu(p).oper[0]^.typ = top_reg) and
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(taicpu(p).oper[1]^.typ = top_reg) and
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(taicpu(p).oper[2]^.typ in [top_reg, top_shifterop]) then
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begin
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{ if d == 13 || (d == 15 && S == ‘0’) || n == 15 || m IN [13,15] then UNPREDICTABLE; }
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add_edge(getsupreg(taicpu(p).oper[0]^.reg), RS_R13);
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if taicpu(p).oppostfix <> PF_S then
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add_edge(getsupreg(taicpu(p).oper[0]^.reg), RS_R15);
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add_edge(getsupreg(taicpu(p).oper[1]^.reg), RS_R15);
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if (taicpu(p).oper[2]^.typ = top_shifterop) and
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(taicpu(p).oper[2]^.shifterop^.rs <> NR_NO) then
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begin
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add_edge(getsupreg(taicpu(p).oper[2]^.shifterop^.rs), RS_R13);
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add_edge(getsupreg(taicpu(p).oper[2]^.shifterop^.rs), RS_R15);
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end
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else if (taicpu(p).oper[2]^.typ = top_reg) then
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begin
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add_edge(getsupreg(taicpu(p).oper[2]^.reg), RS_R13);
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add_edge(getsupreg(taicpu(p).oper[2]^.reg), RS_R15);
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end;
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end;
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end;
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end;
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A_LDRB,
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A_STRB,
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A_STR,
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A_LDR,
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A_LDRH,
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A_STRH,
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A_LDRSB,
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A_LDRSH,
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A_LDRD,
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A_STRD:
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{ don't mix up the framepointer and stackpointer with pre/post indexed operations }
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if (taicpu(p).oper[1]^.typ=top_ref) and
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(taicpu(p).oper[1]^.ref^.addressmode in [AM_PREINDEXED,AM_POSTINDEXED]) then
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begin
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add_edge(getsupreg(taicpu(p).oper[1]^.ref^.base),getsupreg(current_procinfo.framepointer));
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{ FIXME: temp variable r is needed here to avoid Internal error 20060521 }
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{ while compiling the compiler. }
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r:=NR_STACK_POINTER_REG;
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if current_procinfo.framepointer<>r then
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add_edge(getsupreg(taicpu(p).oper[1]^.ref^.base),getsupreg(r));
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end;
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end;
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end;
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end;
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procedure trgcpu.spilling_create_load_store(list: TAsmList; pos: tai; const spilltemp:treference;tempreg:tregister; is_store: boolean);
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var
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tmpref : treference;
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helplist : TAsmList;
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l : tasmlabel;
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hreg : tregister;
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immshift: byte;
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a: aint;
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begin
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helplist:=TAsmList.create;
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{ load consts entry }
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if getregtype(tempreg)=R_INTREGISTER then
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hreg:=getregisterinline(helplist,[R_SUBWHOLE])
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else
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hreg:=cg.getintregister(helplist,OS_ADDR);
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{ Lets remove the bits we can fold in later and check if the result can be easily with an add or sub }
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a:=abs(spilltemp.offset);
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if is_shifter_const(a and not($FFF), immshift) then
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if spilltemp.offset > 0 then
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begin
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{$ifdef DEBUG_SPILLING}
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helplist.concat(tai_comment.create(strpnew('Spilling: Use ADD to fix spill offset')));
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{$endif}
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helplist.concat(taicpu.op_reg_reg_const(A_ADD, hreg, current_procinfo.framepointer,
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a and not($FFF)));
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reference_reset_base(tmpref, hreg, a and $FFF, sizeof(aint));
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end
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else
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begin
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{$ifdef DEBUG_SPILLING}
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helplist.concat(tai_comment.create(strpnew('Spilling: Use SUB to fix spill offset')));
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{$endif}
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helplist.concat(taicpu.op_reg_reg_const(A_SUB, hreg, current_procinfo.framepointer,
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a and not($FFF)));
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reference_reset_base(tmpref, hreg, -(a and $FFF), sizeof(aint));
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end
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else
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begin
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{$ifdef DEBUG_SPILLING}
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helplist.concat(tai_comment.create(strpnew('Spilling: Use a_load_const_reg to fix spill offset')));
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{$endif}
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cg.a_load_const_reg(helplist,OS_ADDR,spilltemp.offset,hreg);
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reference_reset_base(tmpref,current_procinfo.framepointer,0,sizeof(aint));
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tmpref.index:=hreg;
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end;
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if spilltemp.index<>NR_NO then
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internalerror(200401263);
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if is_store then
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helplist.concat(spilling_create_store(tempreg,tmpref))
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else
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helplist.concat(spilling_create_load(tmpref,tempreg));
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if getregtype(tempreg)=R_INTREGISTER then
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ungetregisterinline(helplist,hreg);
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list.insertlistafter(pos,helplist);
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helplist.free;
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end;
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procedure trgcpu.do_spill_read(list:TAsmList;pos:tai;const spilltemp:treference;tempreg:tregister);
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begin
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{ don't load spilled register between
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mov lr,pc
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mov pc,r4
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but befure the mov lr,pc
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}
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if assigned(pos.previous) and
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(pos.typ=ait_instruction) and
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(taicpu(pos).opcode=A_MOV) and
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(taicpu(pos).oper[0]^.typ=top_reg) and
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(taicpu(pos).oper[0]^.reg=NR_R14) and
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(taicpu(pos).oper[1]^.typ=top_reg) and
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(taicpu(pos).oper[1]^.reg=NR_PC) then
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pos:=tai(pos.previous);
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if abs(spilltemp.offset)>4095 then
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spilling_create_load_store(list, pos, spilltemp, tempreg, false)
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else
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inherited do_spill_read(list,pos,spilltemp,tempreg);
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end;
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procedure trgcpu.do_spill_written(list:TAsmList;pos:tai;const spilltemp:treference;tempreg:tregister);
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begin
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if abs(spilltemp.offset)>4095 then
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spilling_create_load_store(list, pos, spilltemp, tempreg, true)
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else
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inherited do_spill_written(list,pos,spilltemp,tempreg);
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end;
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procedure trgcpu.add_constraints(reg:tregister);
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var
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supreg,i : Tsuperregister;
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begin
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case getsubreg(reg) of
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{ Let 32bit floats conflict with all double precision regs > 15
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(since these don't have 32 bit equivalents) }
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R_SUBFS:
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begin
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supreg:=getsupreg(reg);
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for i:=RS_D16 to RS_D31 do
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add_edge(supreg,i);
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end;
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end;
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end;
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function trgcpu.get_spill_subreg(r:tregister) : tsubregister;
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begin
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if (getregtype(r)<>R_MMREGISTER) then
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result:=defaultsub
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else
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result:=getsubreg(r);
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end;
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procedure trgcputhumb2.do_spill_read(list:TAsmList;pos:tai;const spilltemp:treference;tempreg:tregister);
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var
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tmpref : treference;
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helplist : TAsmList;
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l : tasmlabel;
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hreg : tregister;
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begin
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{ don't load spilled register between
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mov lr,pc
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mov pc,r4
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but befure the mov lr,pc
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}
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if assigned(pos.previous) and
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(pos.typ=ait_instruction) and
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(taicpu(pos).opcode=A_MOV) and
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(taicpu(pos).oper[0]^.typ=top_reg) and
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(taicpu(pos).oper[0]^.reg=NR_R14) and
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(taicpu(pos).oper[1]^.typ=top_reg) and
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(taicpu(pos).oper[1]^.reg=NR_PC) then
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pos:=tai(pos.previous);
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if (spilltemp.offset>4095) or (spilltemp.offset<-255) then
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begin
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helplist:=TAsmList.create;
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reference_reset(tmpref,sizeof(aint));
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{ create consts entry }
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current_asmdata.getjumplabel(l);
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cg.a_label(current_procinfo.aktlocaldata,l);
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tmpref.symboldata:=current_procinfo.aktlocaldata.last;
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current_procinfo.aktlocaldata.concat(tai_const.Create_32bit(spilltemp.offset));
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{ load consts entry }
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if getregtype(tempreg)=R_INTREGISTER then
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hreg:=getregisterinline(helplist,[R_SUBWHOLE])
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else
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hreg:=cg.getintregister(helplist,OS_ADDR);
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tmpref.symbol:=l;
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tmpref.base:=NR_R15;
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helplist.concat(taicpu.op_reg_ref(A_LDR,hreg,tmpref));
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reference_reset_base(tmpref,current_procinfo.framepointer,0,sizeof(aint));
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tmpref.index:=hreg;
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if spilltemp.index<>NR_NO then
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internalerror(200401263);
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helplist.concat(spilling_create_load(tmpref,tempreg));
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if getregtype(tempreg)=R_INTREGISTER then
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ungetregisterinline(helplist,hreg);
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list.insertlistafter(pos,helplist);
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helplist.free;
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end
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else
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inherited do_spill_read(list,pos,spilltemp,tempreg);
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end;
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procedure trgcputhumb2.do_spill_written(list:TAsmList;pos:tai;const spilltemp:treference;tempreg:tregister);
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var
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tmpref : treference;
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helplist : TAsmList;
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l : tasmlabel;
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hreg : tregister;
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begin
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if (spilltemp.offset>4095) or (spilltemp.offset<-255) then
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begin
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helplist:=TAsmList.create;
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reference_reset(tmpref,sizeof(aint));
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{ create consts entry }
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current_asmdata.getjumplabel(l);
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cg.a_label(current_procinfo.aktlocaldata,l);
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tmpref.symboldata:=current_procinfo.aktlocaldata.last;
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current_procinfo.aktlocaldata.concat(tai_const.Create_32bit(spilltemp.offset));
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{ load consts entry }
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if getregtype(tempreg)=R_INTREGISTER then
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hreg:=getregisterinline(helplist,[R_SUBWHOLE])
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else
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hreg:=cg.getintregister(helplist,OS_ADDR);
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tmpref.symbol:=l;
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tmpref.base:=NR_R15;
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helplist.concat(taicpu.op_reg_ref(A_LDR,hreg,tmpref));
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if spilltemp.index<>NR_NO then
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internalerror(200401263);
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reference_reset_base(tmpref,current_procinfo.framepointer,0,sizeof(pint));
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tmpref.index:=hreg;
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helplist.concat(spilling_create_store(tempreg,tmpref));
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if getregtype(tempreg)=R_INTREGISTER then
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ungetregisterinline(helplist,hreg);
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list.insertlistafter(pos,helplist);
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helplist.free;
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end
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else
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inherited do_spill_written(list,pos,spilltemp,tempreg);
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end;
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procedure trgintcpu.add_cpu_interferences(p : tai);
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var
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r : tregister;
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begin
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if p.typ=ait_instruction then
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begin
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case taicpu(p).opcode of
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A_MLA,
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A_MUL:
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if current_settings.cputype<cpu_armv6 then
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add_edge(getsupreg(taicpu(p).oper[0]^.reg),getsupreg(taicpu(p).oper[1]^.reg));
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A_UMULL,
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A_UMLAL,
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A_SMULL,
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A_SMLAL:
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begin
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add_edge(getsupreg(taicpu(p).oper[0]^.reg),getsupreg(taicpu(p).oper[1]^.reg));
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add_edge(getsupreg(taicpu(p).oper[1]^.reg),getsupreg(taicpu(p).oper[2]^.reg));
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add_edge(getsupreg(taicpu(p).oper[0]^.reg),getsupreg(taicpu(p).oper[2]^.reg));
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end;
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A_LDRB,
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A_STRB,
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A_STR,
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A_LDR,
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A_LDRH,
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A_STRH:
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{ don't mix up the framepointer and stackpointer with pre/post indexed operations }
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if (taicpu(p).oper[1]^.typ=top_ref) and
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(taicpu(p).oper[1]^.ref^.addressmode in [AM_PREINDEXED,AM_POSTINDEXED]) then
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begin
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add_edge(getsupreg(taicpu(p).oper[1]^.ref^.base),getsupreg(current_procinfo.framepointer));
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{ FIXME: temp variable r is needed here to avoid Internal error 20060521 }
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{ while compiling the compiler. }
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r:=NR_STACK_POINTER_REG;
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if current_procinfo.framepointer<>r then
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add_edge(getsupreg(taicpu(p).oper[1]^.ref^.base),getsupreg(r));
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end;
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end;
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end;
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end;
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end.
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