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484 lines
17 KiB
ObjectPascal
484 lines
17 KiB
ObjectPascal
{
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Copyright (c) 1998-2020 by Jonas Maebe and Florian Klaempfl, members of the Free Pascal
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Development Team
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This unit implements an ARM optimizer object used commonly for ARM and AAarch64
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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Unit aoptarm;
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{$i fpcdefs.inc}
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{ $define DEBUG_PREREGSCHEDULER}
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{ $define DEBUG_AOPTCPU}
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Interface
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uses
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cgbase, cgutils, cpubase, aasmtai, aasmcpu,aopt, aoptobj;
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Type
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{ while ARM and AAarch64 look not very similar at a first glance,
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several optimizations can be shared between both }
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TARMAsmOptimizer = class(TAsmOptimizer)
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procedure DebugMsg(const s : string; p : tai);
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function RemoveSuperfluousMove(const p: tai; movp: tai; const optimizer: string): boolean;
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function GetNextInstructionUsingReg(Current: tai; out Next: tai; reg: TRegister): Boolean;
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function OptPass1UXTB(var p: tai): Boolean;
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function OptPass1UXTH(var p: tai): Boolean;
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End;
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function MatchInstruction(const instr: tai; const op: TCommonAsmOps; const cond: TAsmConds; const postfix: TOpPostfixes): boolean;
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function MatchInstruction(const instr: tai; const op: TAsmOp; const cond: TAsmConds; const postfix: TOpPostfixes): boolean;
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{$ifdef AARCH64}
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function MatchInstruction(const instr: tai; const op: TAsmOps; const postfix: TOpPostfixes): boolean;
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{$endif AARCH64}
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function MatchInstruction(const instr: tai; const op: TAsmOp; const postfix: TOpPostfixes): boolean;
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function RefsEqual(const r1, r2: treference): boolean;
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function MatchOperand(const oper: TOper; const reg: TRegister): boolean; inline;
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function MatchOperand(const oper1: TOper; const oper2: TOper): boolean; inline;
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Implementation
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uses
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cutils,verbose,globtype,globals,
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systems,
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cpuinfo,
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cgobj,procinfo,
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aasmbase,aasmdata;
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{$ifdef DEBUG_AOPTCPU}
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procedure TARMAsmOptimizer.DebugMsg(const s: string;p : tai);
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begin
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asml.insertbefore(tai_comment.Create(strpnew(s)), p);
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end;
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{$else DEBUG_AOPTCPU}
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procedure TARMAsmOptimizer.DebugMsg(const s: string;p : tai);inline;
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begin
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end;
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{$endif DEBUG_AOPTCPU}
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function MatchInstruction(const instr: tai; const op: TCommonAsmOps; const cond: TAsmConds; const postfix: TOpPostfixes): boolean;
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begin
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result :=
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(instr.typ = ait_instruction) and
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((op = []) or ((ord(taicpu(instr).opcode)<256) and (taicpu(instr).opcode in op))) and
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((cond = []) or (taicpu(instr).condition in cond)) and
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((postfix = []) or (taicpu(instr).oppostfix in postfix));
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end;
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function MatchInstruction(const instr: tai; const op: TAsmOp; const cond: TAsmConds; const postfix: TOpPostfixes): boolean;
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begin
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result :=
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(instr.typ = ait_instruction) and
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(taicpu(instr).opcode = op) and
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((cond = []) or (taicpu(instr).condition in cond)) and
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((postfix = []) or (taicpu(instr).oppostfix in postfix));
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end;
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{$ifdef AARCH64}
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function MatchInstruction(const instr: tai; const op: TAsmOps; const postfix: TOpPostfixes): boolean;
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begin
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result :=
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(instr.typ = ait_instruction) and
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((op = []) or (taicpu(instr).opcode in op)) and
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((postfix = []) or (taicpu(instr).oppostfix in postfix));
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end;
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{$endif AARCH64}
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function MatchInstruction(const instr: tai; const op: TAsmOp; const postfix: TOpPostfixes): boolean;
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begin
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result :=
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(instr.typ = ait_instruction) and
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(taicpu(instr).opcode = op) and
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((postfix = []) or (taicpu(instr).oppostfix in postfix));
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end;
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function MatchOperand(const oper: TOper; const reg: TRegister): boolean; inline;
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begin
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result := (oper.typ = top_reg) and (oper.reg = reg);
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end;
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function RefsEqual(const r1, r2: treference): boolean;
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begin
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refsequal :=
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(r1.offset = r2.offset) and
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(r1.base = r2.base) and
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(r1.index = r2.index) and (r1.scalefactor = r2.scalefactor) and
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(r1.symbol=r2.symbol) and (r1.refaddr = r2.refaddr) and
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(r1.relsymbol = r2.relsymbol) and
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{$ifdef ARM}
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(r1.signindex = r2.signindex) and
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{$endif ARM}
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(r1.shiftimm = r2.shiftimm) and
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(r1.addressmode = r2.addressmode) and
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(r1.shiftmode = r2.shiftmode) and
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(r1.volatility=[]) and
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(r2.volatility=[]);
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end;
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function MatchOperand(const oper1: TOper; const oper2: TOper): boolean; inline;
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begin
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result := oper1.typ = oper2.typ;
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if result then
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case oper1.typ of
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top_const:
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Result:=oper1.val = oper2.val;
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top_reg:
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Result:=oper1.reg = oper2.reg;
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top_conditioncode:
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Result:=oper1.cc = oper2.cc;
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top_realconst:
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Result:=oper1.val_real = oper2.val_real;
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top_ref:
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Result:=RefsEqual(oper1.ref^, oper2.ref^);
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else Result:=false;
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end
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end;
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function TARMAsmOptimizer.GetNextInstructionUsingReg(Current: tai;
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Out Next: tai; reg: TRegister): Boolean;
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begin
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Next:=Current;
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repeat
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Result:=GetNextInstruction(Next,Next);
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until not (Result) or
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not(cs_opt_level3 in current_settings.optimizerswitches) or
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(Next.typ<>ait_instruction) or
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RegInInstruction(reg,Next) or
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is_calljmp(taicpu(Next).opcode)
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{$ifdef ARM}
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or RegModifiedByInstruction(NR_PC,Next);
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{$endif ARM}
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end;
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function TARMAsmOptimizer.RemoveSuperfluousMove(const p: tai; movp: tai; const optimizer: string):boolean;
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var
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alloc,
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dealloc : tai_regalloc;
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hp1 : tai;
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begin
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Result:=false;
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if MatchInstruction(movp, A_MOV, [taicpu(p).condition], [PF_None]) and
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{ We can't optimize if there is a shiftop }
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(taicpu(movp).ops=2) and
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MatchOperand(taicpu(movp).oper[1]^, taicpu(p).oper[0]^.reg) and
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{ don't mess with moves to fp }
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(taicpu(movp).oper[0]^.reg<>current_procinfo.framepointer) and
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{ the destination register of the mov might not be used beween p and movp }
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not(RegUsedBetween(taicpu(movp).oper[0]^.reg,p,movp)) and
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{$ifdef ARM}
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{ cb[n]z are thumb instructions which require specific registers, with no wide forms }
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(taicpu(p).opcode<>A_CBZ) and
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(taicpu(p).opcode<>A_CBNZ) and
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{There is a special requirement for MUL and MLA, oper[0] and oper[1] are not allowed to be the same}
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not (
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(taicpu(p).opcode in [A_MLA, A_MUL]) and
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(taicpu(p).oper[1]^.reg = taicpu(movp).oper[0]^.reg) and
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(current_settings.cputype < cpu_armv6)
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) and
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{$endif ARM}
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{ Take care to only do this for instructions which REALLY load to the first register.
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Otherwise
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str reg0, [reg1]
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mov reg2, reg0
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will be optimized to
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str reg2, [reg1]
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}
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RegLoadedWithNewValue(taicpu(p).oper[0]^.reg, p) then
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begin
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dealloc:=FindRegDeAlloc(taicpu(p).oper[0]^.reg,tai(movp.Next));
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if assigned(dealloc) then
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begin
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DebugMsg('Peephole '+optimizer+' removed superfluous mov', movp);
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result:=true;
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{ taicpu(p).oper[0]^.reg is not used anymore, try to find its allocation
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and remove it if possible }
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asml.Remove(dealloc);
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alloc:=FindRegAllocBackward(taicpu(p).oper[0]^.reg,tai(p.previous));
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if assigned(alloc) then
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begin
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asml.Remove(alloc);
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alloc.free;
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dealloc.free;
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end
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else
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asml.InsertAfter(dealloc,p);
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{ try to move the allocation of the target register }
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GetLastInstruction(movp,hp1);
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alloc:=FindRegAlloc(taicpu(movp).oper[0]^.reg,tai(hp1.Next));
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if assigned(alloc) then
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begin
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asml.Remove(alloc);
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asml.InsertBefore(alloc,p);
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{ adjust used regs }
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IncludeRegInUsedRegs(taicpu(movp).oper[0]^.reg,UsedRegs);
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end;
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{ finally get rid of the mov }
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taicpu(p).loadreg(0,taicpu(movp).oper[0]^.reg);
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{ Remove preindexing and postindexing for LDR in some cases.
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For example:
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ldr reg2,[reg1, xxx]!
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mov reg1,reg2
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must be translated to:
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ldr reg1,[reg1, xxx]
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Preindexing must be removed there, since the same register is used as the base and as the target.
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Such case is not allowed for ARM CPU and produces crash. }
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if (taicpu(p).opcode = A_LDR) and (taicpu(p).oper[1]^.typ = top_ref)
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and (taicpu(movp).oper[0]^.reg = taicpu(p).oper[1]^.ref^.base)
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then
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taicpu(p).oper[1]^.ref^.addressmode:=AM_OFFSET;
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asml.remove(movp);
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movp.free;
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end;
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end;
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end;
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function TARMAsmOptimizer.OptPass1UXTB(var p : tai) : Boolean;
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var
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hp1, hp2: tai;
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begin
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Result:=false;
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{
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change
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uxtb reg2,reg1
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strb reg2,[...]
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dealloc reg2
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to
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strb reg1,[...]
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}
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if MatchInstruction(p, taicpu(p).opcode, [C_None], [PF_None]) and
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(taicpu(p).ops=2) and
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GetNextInstructionUsingReg(p,hp1,taicpu(p).oper[0]^.reg) and
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MatchInstruction(hp1, A_STR, [C_None], [PF_B]) and
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assigned(FindRegDealloc(taicpu(p).oper[0]^.reg,tai(hp1.Next))) and
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{ the reference in strb might not use reg2 }
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not(RegInRef(taicpu(p).oper[0]^.reg,taicpu(hp1).oper[1]^.ref^)) and
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{ reg1 might not be modified inbetween }
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not(RegModifiedBetween(taicpu(p).oper[1]^.reg,p,hp1)) then
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begin
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DebugMsg('Peephole UxtbStrb2Strb done', p);
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taicpu(hp1).loadReg(0,taicpu(p).oper[1]^.reg);
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GetNextInstruction(p,hp2);
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asml.remove(p);
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p.free;
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p:=hp2;
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result:=true;
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end
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{
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change
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uxtb reg2,reg1
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uxth reg3,reg2
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dealloc reg2
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to
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uxtb reg3,reg1
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}
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else if MatchInstruction(p, A_UXTB, [C_None], [PF_None]) and
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(taicpu(p).ops=2) and
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GetNextInstructionUsingReg(p,hp1,taicpu(p).oper[0]^.reg) and
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MatchInstruction(hp1, A_UXTH, [C_None], [PF_None]) and
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(taicpu(hp1).ops = 2) and
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MatchOperand(taicpu(hp1).oper[1]^, taicpu(p).oper[0]^.reg) and
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RegEndofLife(taicpu(p).oper[0]^.reg,taicpu(hp1)) and
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{ reg1 might not be modified inbetween }
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not(RegModifiedBetween(taicpu(p).oper[1]^.reg,p,hp1)) then
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begin
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DebugMsg('Peephole UxtbUxth2Uxtb done', p);
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AllocRegBetween(taicpu(hp1).oper[0]^.reg,p,hp1,UsedRegs);
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taicpu(p).loadReg(0,taicpu(hp1).oper[0]^.reg);
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asml.remove(hp1);
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hp1.free;
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result:=true;
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end
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{
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change
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uxtb reg2,reg1
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uxtb reg3,reg2
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dealloc reg2
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to
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uxtb reg3,reg1
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}
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else if MatchInstruction(p, A_UXTB, [C_None], [PF_None]) and
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(taicpu(p).ops=2) and
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GetNextInstructionUsingReg(p,hp1,taicpu(p).oper[0]^.reg) and
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MatchInstruction(hp1, A_UXTB, [C_None], [PF_None]) and
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(taicpu(hp1).ops = 2) and
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MatchOperand(taicpu(hp1).oper[1]^, taicpu(p).oper[0]^.reg) and
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RegEndofLife(taicpu(p).oper[0]^.reg,taicpu(hp1)) and
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{ reg1 might not be modified inbetween }
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not(RegModifiedBetween(taicpu(p).oper[1]^.reg,p,hp1)) then
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begin
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DebugMsg('Peephole UxtbUxtb2Uxtb done', p);
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AllocRegBetween(taicpu(hp1).oper[0]^.reg,p,hp1,UsedRegs);
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taicpu(p).loadReg(0,taicpu(hp1).oper[0]^.reg);
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asml.remove(hp1);
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hp1.free;
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result:=true;
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end
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{
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change
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uxtb reg2,reg1
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and reg3,reg2,#0x*FF
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dealloc reg2
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to
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uxtb reg3,reg1
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}
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else if MatchInstruction(p, A_UXTB, [C_None], [PF_None]) and
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(taicpu(p).ops=2) and
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GetNextInstructionUsingReg(p,hp1,taicpu(p).oper[0]^.reg) and
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MatchInstruction(hp1, A_AND, [C_None], [PF_None]) and
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(taicpu(hp1).ops=3) and
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(taicpu(hp1).oper[2]^.typ=top_const) and
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((taicpu(hp1).oper[2]^.val and $FF)=$FF) and
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MatchOperand(taicpu(hp1).oper[1]^, taicpu(p).oper[0]^.reg) and
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RegEndofLife(taicpu(p).oper[0]^.reg,taicpu(hp1)) and
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{ reg1 might not be modified inbetween }
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not(RegModifiedBetween(taicpu(p).oper[1]^.reg,p,hp1)) then
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begin
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DebugMsg('Peephole UxtbAndImm2Uxtb done', p);
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taicpu(hp1).opcode:=A_UXTB;
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taicpu(hp1).ops:=2;
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taicpu(hp1).loadReg(1,taicpu(p).oper[1]^.reg);
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GetNextInstruction(p,hp2);
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asml.remove(p);
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p.free;
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p:=hp2;
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result:=true;
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end
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else if GetNextInstructionUsingReg(p, hp1, taicpu(p).oper[0]^.reg) and
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RemoveSuperfluousMove(p, hp1, 'UxtbMov2Data') then
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Result:=true;
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end;
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function TARMAsmOptimizer.OptPass1UXTH(var p : tai) : Boolean;
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var
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hp1: tai;
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begin
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Result:=false;
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{
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change
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uxth reg2,reg1
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strh reg2,[...]
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dealloc reg2
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to
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strh reg1,[...]
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}
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if MatchInstruction(p, taicpu(p).opcode, [C_None], [PF_None]) and
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(taicpu(p).ops=2) and
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GetNextInstructionUsingReg(p,hp1,taicpu(p).oper[0]^.reg) and
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MatchInstruction(hp1, A_STR, [C_None], [PF_H]) and
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RegEndofLife(taicpu(p).oper[0]^.reg,taicpu(hp1)) and
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{ the reference in strb might not use reg2 }
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not(RegInRef(taicpu(p).oper[0]^.reg,taicpu(hp1).oper[1]^.ref^)) and
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{ reg1 might not be modified inbetween }
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not(RegModifiedBetween(taicpu(p).oper[1]^.reg,p,hp1)) then
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begin
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DebugMsg('Peephole UXTHStrh2Strh done', p);
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taicpu(hp1).loadReg(0,taicpu(p).oper[1]^.reg);
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GetNextInstruction(p, hp1);
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asml.remove(p);
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p.free;
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p:=hp1;
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result:=true;
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end
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{
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change
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uxth reg2,reg1
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uxth reg3,reg2
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dealloc reg2
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to
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uxth reg3,reg1
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}
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else if MatchInstruction(p, A_UXTH, [C_None], [PF_None]) and
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(taicpu(p).ops=2) and
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GetNextInstructionUsingReg(p,hp1,taicpu(p).oper[0]^.reg) and
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MatchInstruction(hp1, A_UXTH, [C_None], [PF_None]) and
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(taicpu(hp1).ops=2) and
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MatchOperand(taicpu(hp1).oper[1]^, taicpu(p).oper[0]^.reg) and
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RegEndofLife(taicpu(p).oper[0]^.reg,taicpu(hp1)) and
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{ reg1 might not be modified inbetween }
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not(RegModifiedBetween(taicpu(p).oper[1]^.reg,p,hp1)) then
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begin
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DebugMsg('Peephole UxthUxth2Uxth done', p);
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AllocRegBetween(taicpu(p).oper[1]^.reg,p,hp1,UsedRegs);
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taicpu(hp1).opcode:=A_UXTH;
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taicpu(hp1).loadReg(1,taicpu(p).oper[1]^.reg);
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GetNextInstruction(p, hp1);
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asml.remove(p);
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p.free;
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p:=hp1;
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result:=true;
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end
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{
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change
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uxth reg2,reg1
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and reg3,reg2,#65535
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dealloc reg2
|
|
to
|
|
uxth reg3,reg1
|
|
}
|
|
else if MatchInstruction(p, A_UXTH, [C_None], [PF_None]) and
|
|
(taicpu(p).ops=2) and
|
|
GetNextInstructionUsingReg(p,hp1,taicpu(p).oper[0]^.reg) and
|
|
MatchInstruction(hp1, A_AND, [C_None], [PF_None]) and
|
|
(taicpu(hp1).ops=3) and
|
|
(taicpu(hp1).oper[2]^.typ=top_const) and
|
|
((taicpu(hp1).oper[2]^.val and $FFFF)=$FFFF) and
|
|
MatchOperand(taicpu(hp1).oper[1]^, taicpu(p).oper[0]^.reg) and
|
|
RegEndofLife(taicpu(p).oper[0]^.reg,taicpu(hp1)) and
|
|
{ reg1 might not be modified inbetween }
|
|
not(RegModifiedBetween(taicpu(p).oper[1]^.reg,p,hp1)) then
|
|
begin
|
|
DebugMsg('Peephole UxthAndImm2Uxth done', p);
|
|
taicpu(hp1).opcode:=A_UXTH;
|
|
taicpu(hp1).ops:=2;
|
|
taicpu(hp1).loadReg(1,taicpu(p).oper[1]^.reg);
|
|
GetNextInstruction(p, hp1);
|
|
asml.remove(p);
|
|
p.free;
|
|
p:=hp1;
|
|
result:=true;
|
|
end
|
|
else if GetNextInstructionUsingReg(p, hp1, taicpu(p).oper[0]^.reg) and
|
|
RemoveSuperfluousMove(p, hp1, 'UxthMov2Data') then
|
|
Result:=true;
|
|
end;
|
|
|
|
end.
|
|
|