fpc/compiler/riscv
Jeppe Johansen 74a7963d58 Redo overflow checking code.
Fix shift operators in case of unsigned subreg operations. There should be no sign extension here.
Add some unittest implementations that test stack execution and writing to readonly constants.

git-svn-id: branches/laksen/riscv_new@39762 -
2018-09-16 18:37:59 +00:00
..
aasmcpu.pas Add rounding mode operands. 2018-09-01 19:48:44 +00:00
agrvgas.pas Add rounding mode operands. 2018-09-01 19:48:44 +00:00
cgrv.pas Redo overflow checking code. 2018-09-16 18:37:59 +00:00
hlcgrv.pas
nrvadd.pas Fix bugs caused by swapping of operands in float comparisons. 2018-09-01 19:47:28 +00:00
nrvcnv.pas
nrvcon.pas
nrvinl.pas Add rounding mode operands. 2018-09-01 19:48:44 +00:00
nrvset.pas Add RV64GC cpu type. 2018-07-21 22:34:42 +00:00
rgcpu.pas