mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-10-31 22:29:45 +01:00
55669f62b1
Made absolutevarsym use PUint instead of AWord for its offset to fix range errors. git-svn-id: trunk@31242 -
484 lines
21 KiB
ObjectPascal
484 lines
21 KiB
ObjectPascal
unit ATmega16HVB;
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{$goto on}
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interface
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var
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// AD_CONVERTER
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VADMUX : byte absolute $00+$7C; // The VADC multiplexer Selection Register
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VADC : word absolute $00+$78; // VADC Data Register Bytes
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VADCL : byte absolute $00+$78; // VADC Data Register Bytes
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VADCH : byte absolute $00+$78+1; // VADC Data Register Bytes
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VADCSR : byte absolute $00+$7A; // The VADC Control and Status register
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// WATCHDOG
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WDTCSR : byte absolute $00+$60; // Watchdog Timer Control Register
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// FET
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FCSR : byte absolute $00+$F0; // FET Control and Status Register
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// SPI
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SPCR : byte absolute $00+$4c; // SPI Control Register
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SPSR : byte absolute $00+$4d; // SPI Status Register
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SPDR : byte absolute $00+$4e; // SPI Data Register
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// EEPROM
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EEAR : word absolute $00+$41; // EEPROM Read/Write Access
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EEARL : byte absolute $00+$41; // EEPROM Read/Write Access
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EEARH : byte absolute $00+$41+1; // EEPROM Read/Write Access
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EEDR : byte absolute $00+$40; // EEPROM Data Register
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EECR : byte absolute $00+$3F; // EEPROM Control Register
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// COULOMB_COUNTER
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CADCSRA : byte absolute $00+$E6; // CC-ADC Control and Status Register A
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CADCSRB : byte absolute $00+$E7; // CC-ADC Control and Status Register B
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CADCSRC : byte absolute $00+$E8; // CC-ADC Control and Status Register C
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CADIC : word absolute $00+$E4; // CC-ADC Instantaneous Current
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CADICL : byte absolute $00+$E4; // CC-ADC Instantaneous Current
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CADICH : byte absolute $00+$E4+1; // CC-ADC Instantaneous Current
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CADAC3 : byte absolute $00+$E3; // ADC Accumulate Current
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CADAC2 : byte absolute $00+$E2; // ADC Accumulate Current
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CADAC1 : byte absolute $00+$E1; // ADC Accumulate Current
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CADAC0 : byte absolute $00+$E0; // ADC Accumulate Current
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CADRCC : byte absolute $00+$E9; // CC-ADC Regular Charge Current
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CADRDC : byte absolute $00+$EA; // CC-ADC Regular Discharge Current
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// TWI
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TWBCSR : byte absolute $00+$BE; // TWI Bus Control and Status Register
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TWAMR : byte absolute $00+$BD; // TWI (Slave) Address Mask Register
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TWBR : byte absolute $00+$B8; // TWI Bit Rate register
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TWCR : byte absolute $00+$BC; // TWI Control Register
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TWSR : byte absolute $00+$B9; // TWI Status Register
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TWDR : byte absolute $00+$BB; // TWI Data register
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TWAR : byte absolute $00+$BA; // TWI (Slave) Address register
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// EXTERNAL_INTERRUPT
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EICRA : byte absolute $00+$69; // External Interrupt Control Register
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EIMSK : byte absolute $00+$3D; // External Interrupt Mask Register
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EIFR : byte absolute $00+$3C; // External Interrupt Flag Register
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PCICR : byte absolute $00+$68; // Pin Change Interrupt Control Register
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PCIFR : byte absolute $00+$3B; // Pin Change Interrupt Flag Register
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PCMSK1 : byte absolute $00+$6C; // Pin Change Enable Mask Register 1
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PCMSK0 : byte absolute $00+$6B; // Pin Change Enable Mask Register 0
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// TIMER_COUNTER_1
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TCCR1B : byte absolute $00+$81; // Timer/Counter1 Control Register B
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TCCR1A : byte absolute $00+$80; // Timer/Counter 1 Control Register A
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TCNT1 : word absolute $00+$84; // Timer Counter 1 Bytes
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TCNT1L : byte absolute $00+$84; // Timer Counter 1 Bytes
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TCNT1H : byte absolute $00+$84+1; // Timer Counter 1 Bytes
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OCR1A : byte absolute $00+$88; // Output Compare Register 1A
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OCR1B : byte absolute $00+$89; // Output Compare Register B
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TIMSK1 : byte absolute $00+$6F; // Timer/Counter Interrupt Mask Register
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TIFR1 : byte absolute $00+$36; // Timer/Counter Interrupt Flag register
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GTCCR : byte absolute $00+$43; // General Timer/Counter Control Register
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// CELL_BALANCING
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CBCR : byte absolute $00+$F1; // Cell Balancing Control Register
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// BATTERY_PROTECTION
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BPPLR : byte absolute $00+$FE; // Battery Protection Parameter Lock Register
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BPCR : byte absolute $00+$FD; // Battery Protection Control Register
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BPHCTR : byte absolute $00+$FC; // Battery Protection Short-current Timing Register
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BPOCTR : byte absolute $00+$FB; // Battery Protection Over-current Timing Register
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BPSCTR : byte absolute $00+$FA; // Battery Protection Short-current Timing Register
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BPCHCD : byte absolute $00+$F9; // Battery Protection Charge-High-current Detection Level Register
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BPDHCD : byte absolute $00+$F8; // Battery Protection Discharge-High-current Detection Level Register
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BPCOCD : byte absolute $00+$F7; // Battery Protection Charge-Over-current Detection Level Register
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BPDOCD : byte absolute $00+$F6; // Battery Protection Discharge-Over-current Detection Level Register
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BPSCD : byte absolute $00+$F5; // Battery Protection Short-Circuit Detection Level Register
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BPIFR : byte absolute $00+$F3; // Battery Protection Interrupt Flag Register
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BPIMSK : byte absolute $00+$F2; // Battery Protection Interrupt Mask Register
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// CHARGER_DETECT
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CHGDCSR : byte absolute $00+$D4; // Charger Detect Control and Status Register
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// VOLTAGE_REGULATOR
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ROCR : byte absolute $00+$C8; // Regulator Operating Condition Register
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// BANDGAP
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BGCSR : byte absolute $00+$D2; // Bandgap Control and Status Register
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BGCRR : byte absolute $00+$D1; // Bandgap Calibration of Resistor Ladder
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BGCCR : byte absolute $00+$D0; // Bandgap Calibration Register
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// CPU
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SREG : byte absolute $00+$5F; // Status Register
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SP : word absolute $00+$5D; // Stack Pointer
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SPL : byte absolute $00+$5D; // Stack Pointer
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SPH : byte absolute $00+$5D+1; // Stack Pointer
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MCUCR : byte absolute $00+$55; // MCU Control Register
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MCUSR : byte absolute $00+$54; // MCU Status Register
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FOSCCAL : byte absolute $00+$66; // Fast Oscillator Calibration Value
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OSICSR : byte absolute $00+$37; // Oscillator Sampling Interface Control and Status Register
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SMCR : byte absolute $00+$53; // Sleep Mode Control Register
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GPIOR2 : byte absolute $00+$4B; // General Purpose IO Register 2
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GPIOR1 : byte absolute $00+$4A; // General Purpose IO Register 1
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GPIOR0 : byte absolute $00+$3E; // General Purpose IO Register 0
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DIDR0 : byte absolute $00+$7E; // Digital Input Disable Register
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PRR0 : byte absolute $00+$64; // Power Reduction Register 0
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CLKPR : byte absolute $00+$61; // Clock Prescale Register
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// PORTA
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PORTA : byte absolute $00+$22; // Port A Data Register
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DDRA : byte absolute $00+$21; // Port A Data Direction Register
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PINA : byte absolute $00+$20; // Port A Input Pins
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// PORTB
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PORTB : byte absolute $00+$25; // Port B Data Register
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DDRB : byte absolute $00+$24; // Port B Data Direction Register
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PINB : byte absolute $00+$23; // Port B Input Pins
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// PORTC
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PORTC : byte absolute $00+$28; // Port C Data Register
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PINC : byte absolute $00+$26; // Port C Input Pins
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// TIMER_COUNTER_0
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TCCR0B : byte absolute $00+$45; // Timer/Counter0 Control Register B
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TCCR0A : byte absolute $00+$44; // Timer/Counter 0 Control Register A
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TCNT0 : word absolute $00+$46; // Timer Counter 0 Bytes
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TCNT0L : byte absolute $00+$46; // Timer Counter 0 Bytes
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TCNT0H : byte absolute $00+$46+1; // Timer Counter 0 Bytes
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OCR0A : byte absolute $00+$48; // Output Compare Register 0A
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OCR0B : byte absolute $00+$49; // Output Compare Register B
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TIMSK0 : byte absolute $00+$6E; // Timer/Counter Interrupt Mask Register
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TIFR0 : byte absolute $00+$35; // Timer/Counter Interrupt Flag register
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// BOOT_LOAD
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SPMCSR : byte absolute $00+$57; // Store Program Memory Control and Status Register
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const
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// VADMUX
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// VADCSR
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VADEN = 3; // VADC Enable
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VADSC = 2; // VADC Satrt Conversion
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VADCCIF = 1; // VADC Conversion Complete Interrupt Flag
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VADCCIE = 0; // VADC Conversion Complete Interrupt Enable
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// WDTCSR
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WDIF = 7; // Watchdog Timeout Interrupt Flag
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WDIE = 6; // Watchdog Timeout Interrupt Enable
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WDP = 0; // Watchdog Timer Prescaler Bits
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WDCE = 4; // Watchdog Change Enable
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WDE = 3; // Watch Dog Enable
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// FCSR
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DUVRD = 3; // Deep Under-Voltage Recovery Disable
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CPS = 2; // Current Protection Status
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DFE = 1; // Discharge FET Enable
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CFE = 0; // Charge FET Enable
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// SPCR
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SPIE = 7; // SPI Interrupt Enable
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SPE = 6; // SPI Enable
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DORD = 5; // Data Order
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MSTR = 4; // Master/Slave Select
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CPOL = 3; // Clock polarity
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CPHA = 2; // Clock Phase
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SPR = 0; // SPI Clock Rate Selects
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// SPSR
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SPIF = 7; // SPI Interrupt Flag
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WCOL = 6; // Write Collision Flag
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SPI2X = 0; // Double SPI Speed Bit
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// EECR
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EEPM = 4; //
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EERIE = 3; // EEProm Ready Interrupt Enable
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EEMPE = 2; // EEPROM Master Write Enable
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EEPE = 1; // EEPROM Write Enable
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EERE = 0; // EEPROM Read Enable
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// CADCSRA
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CADEN = 7; // When the CADEN bit is cleared (zero), the CC-ADC is disabled. When the CADEN bit is set (one), the CC-ADC will continuously measure the voltage drop over the external sense resistor RSENSE. In Power-down, only the Regular Current detection is active. In Power-off, the CC-ADC is always disabled.
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CADPOL = 6; //
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CADUB = 5; // CC_ADC Update Busy
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CADAS = 3; // CC_ADC Accumulate Current Select Bits
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CADSI = 1; // The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined.
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CADSE = 0; // When the CADSE bit is written to one, the ongoing CC-ADC conversion is aborted, and the CC-ADC enters Regular Current detection mode.
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// CADCSRB
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CADACIE = 6; //
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CADRCIE = 5; // Regular Current Interrupt Enable
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CADICIE = 4; // CAD Instantenous Current Interrupt Enable
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CADACIF = 2; // CC-ADC Accumulate Current Interrupt Flag
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CADRCIF = 1; // CC-ADC Accumulate Current Interrupt Flag
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CADICIF = 0; // CC-ADC Instantaneous Current Interrupt Flag
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// CADCSRC
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CADVSE = 0; // CC-ADC Voltage Scaling Enable
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// TWBCSR
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TWBCIF = 7; // TWI Bus Connect/Disconnect Interrupt Flag
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TWBCIE = 6; // TWI Bus Connect/Disconnect Interrupt Enable
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TWBDT = 1; // TWI Bus Disconnect Time-out Period
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TWBCIP = 0; // TWI Bus Connect/Disconnect Interrupt Polarity
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// TWAMR
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TWAM = 1; //
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// TWCR
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TWINT = 7; // TWI Interrupt Flag
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TWEA = 6; // TWI Enable Acknowledge Bit
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TWSTA = 5; // TWI Start Condition Bit
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TWSTO = 4; // TWI Stop Condition Bit
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TWWC = 3; // TWI Write Collition Flag
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TWEN = 2; // TWI Enable Bit
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TWIE = 0; // TWI Interrupt Enable
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// TWSR
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TWS = 3; // TWI Status
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TWPS = 0; // TWI Prescaler
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// TWAR
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TWA = 1; // TWI (Slave) Address register Bits
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TWGCE = 0; // TWI General Call Recognition Enable Bit
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// EICRA
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ISC3 = 6; // External Interrupt Sense Control 3 Bits
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ISC2 = 4; // External Interrupt Sense Control 2 Bits
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ISC1 = 2; // External Interrupt Sense Control 1 Bits
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ISC0 = 0; // External Interrupt Sense Control 0 Bits
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// EIMSK
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INT = 0; // External Interrupt Request 3 Enable
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// EIFR
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INTF = 0; // External Interrupt Flags
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// PCICR
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PCIE = 0; // Pin Change Interrupt Enables
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// PCIFR
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PCIF = 0; // Pin Change Interrupt Flags
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// TCCR1B
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CS = 0; // Clock Select1 bis
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// TCCR1A
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TCW1 = 7; // Timer/Counter Width
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ICEN1 = 6; // Input Capture Mode Enable
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ICNC1 = 5; // Input Capture Noise Canceler
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ICES1 = 4; // Input Capture Edge Select
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ICS1 = 3; // Input Capture Select
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WGM10 = 0; // Waveform Generation Mode
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// TIMSK1
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ICIE1 = 3; // Timer/Counter n Input Capture Interrupt Enable
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OCIE1B = 2; // Timer/Counter1 Output Compare B Interrupt Enable
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OCIE1A = 1; // Timer/Counter1 Output Compare A Interrupt Enable
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TOIE1 = 0; // Timer/Counter1 Overflow Interrupt Enable
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// TIFR1
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ICF1 = 3; // Timer/Counter 1 Input Capture Flag
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OCF1B = 2; // Timer/Counter1 Output Compare Flag B
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OCF1A = 1; // Timer/Counter1 Output Compare Flag A
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TOV1 = 0; // Timer/Counter1 Overflow Flag
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// GTCCR
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TSM = 7; // Timer/Counter Synchronization Mode
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PSRSYNC = 0; // Prescaler Reset
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// CBCR
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CBE = 0; // Cell Balancing Enables
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// BPPLR
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BPPLE = 1; // Battery Protection Parameter Lock Enable
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BPPL = 0; // Battery Protection Parameter Lock
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// BPCR
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EPID = 5; // External Protection Input Disable
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SCD = 4; // Short Circuit Protection Disabled
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DOCD = 3; // Discharge Over-current Protection Disabled
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COCD = 2; // Charge Over-current Protection Disabled
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DHCD = 1; // Discharge High-current Protection Disable
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CHCD = 0; // Charge High-current Protection Disable
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// BPIFR
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SCIF = 4; // Short-circuit Protection Activated Interrupt Flag
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DOCIF = 3; // Discharge Over-current Protection Activated Interrupt Flag
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COCIF = 2; // Charge Over-current Protection Activated Interrupt Flag
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DHCIF = 1; // Disharge High-current Protection Activated Interrupt
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CHCIF = 0; // Charge High-current Protection Activated Interrupt
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// BPIMSK
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SCIE = 4; // Short-circuit Protection Activated Interrupt Enable
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DOCIE = 3; // Discharge Over-current Protection Activated Interrupt Enable
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COCIE = 2; // Charge Over-current Protection Activated Interrupt Enable
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DHCIE = 1; // Discharger High-current Protection Activated Interrupt
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CHCIE = 0; // Charger High-current Protection Activated Interrupt
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// CHGDCSR
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BATTPVL = 4; // BATT Pin Voltage Level
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CHGDISC = 2; // Charger Detect Interrupt Sense Control
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CHGDIF = 1; // Charger Detect Interrupt Flag
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CHGDIE = 0; // Charger Detect Interrupt Enable
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// ROCR
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ROCS = 7; // ROC Status
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ROCD = 4; // ROC Disable
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ROCWIF = 1; // ROC Warning Interrupt Flag
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ROCWIE = 0; // ROC Warning Interrupt Enable
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// BGCSR
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BGD = 5; // Bandgap Disable
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BGSCDE = 4; // Bandgap Short Circuit Detection Enabled
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BGSCDIF = 1; // Bandgap Short Circuit Detection Interrupt Flag
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BGSCDIE = 0; // Bandgap Short Circuit Detection Interrupt Enable
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// BGCCR
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BGCC = 0; // BG Calibration of PTAT Current Bits
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// SREG
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I = 7; // Global Interrupt Enable
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T = 6; // Bit Copy Storage
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H = 5; // Half Carry Flag
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S = 4; // Sign Bit
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V = 3; // Two's Complement Overflow Flag
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N = 2; // Negative Flag
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Z = 1; // Zero Flag
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C = 0; // Carry Flag
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// MCUCR
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CKOE = 5; // Clock Output Enable
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PUD = 4; // Pull-up disable
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IVSEL = 1; // Interrupt Vector Select
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IVCE = 0; // Interrupt Vector Change Enable
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// MCUSR
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OCDRF = 4; // OCD Reset Flag
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WDRF = 3; // Watchdog Reset Flag
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BODRF = 2; // Brown-out Reset Flag
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EXTRF = 1; // External Reset Flag
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PORF = 0; // Power-on reset flag
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// OSICSR
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OSISEL0 = 4; // Oscillator Sampling Interface Select 0
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OSIST = 1; // Oscillator Sampling Interface Status
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OSIEN = 0; // Oscillator Sampling Interface Enable
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// SMCR
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SM = 1; // Sleep Mode Select bits
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SE = 0; // Sleep Enable
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// DIDR0
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PA1DID = 1; // When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled.
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PA0DID = 0; // When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled.
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// PRR0
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PRTWI = 6; // Power Reduction TWI
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PRVRM = 5; // Power Reduction Voltage Regulator Monitor
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PRSPI = 3; // Power reduction SPI
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PRTIM1 = 2; // Power Reduction Timer/Counter1
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PRTIM0 = 1; // Power Reduction Timer/Counter0
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PRVADC = 0; // Power Reduction V-ADC
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// CLKPR
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CLKPCE = 7; // Clock Prescaler Change Enable
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CLKPS = 0; // Clock Prescaler Select Bits
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// TCCR0B
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CS02 = 2; // Clock Select0 bit 2
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CS01 = 1; // Clock Select0 bit 1
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CS00 = 0; // Clock Select0 bit 0
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// TCCR0A
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TCW0 = 7; // Timer/Counter Width
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ICEN0 = 6; // Input Capture Mode Enable
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ICNC0 = 5; // Input Capture Noise Canceler
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ICES0 = 4; // Input Capture Edge Select
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ICS0 = 3; // Input Capture Select
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WGM00 = 0; // Waveform Generation Mode
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// TIMSK0
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ICIE0 = 3; // Timer/Counter n Input Capture Interrupt Enable
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OCIE0B = 2; // Timer/Counter0 Output Compare B Interrupt Enable
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OCIE0A = 1; // Timer/Counter0 Output Compare A Interrupt Enable
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TOIE0 = 0; // Timer/Counter0 Overflow Interrupt Enable
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// TIFR0
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ICF0 = 3; // Timer/Counter 0 Input Capture Flag
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OCF0B = 2; // Timer/Counter0 Output Compare Flag B
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OCF0A = 1; // Timer/Counter0 Output Compare Flag A
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TOV0 = 0; // Timer/Counter0 Overflow Flag
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// GTCCR
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// SPMCSR
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SPMIE = 7; // SPM Interrupt Enable
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RWWSB = 6; // Read-While-Write Section Busy
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SIGRD = 5; // Signature Row Read
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RWWSRE = 4; // Read-While-Write Section Read Enable
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LBSET = 3; // Lock Bit Set
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PGWRT = 2; // Page Write
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PGERS = 1; // Page Erase
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SPMEN = 0; // Store Program Memory Enable
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implementation
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{$i avrcommon.inc}
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procedure BPINT_ISR; external name 'BPINT_ISR'; // Interrupt 1 Battery Protection Interrupt
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procedure VREGMON_ISR; external name 'VREGMON_ISR'; // Interrupt 2 Voltage regulator monitor interrupt
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procedure INT0_ISR; external name 'INT0_ISR'; // Interrupt 3 External Interrupt Request 0
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procedure INT1_ISR; external name 'INT1_ISR'; // Interrupt 4 External Interrupt Request 1
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procedure INT2_ISR; external name 'INT2_ISR'; // Interrupt 5 External Interrupt Request 2
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procedure INT3_ISR; external name 'INT3_ISR'; // Interrupt 6 External Interrupt Request 3
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procedure PCINT0_ISR; external name 'PCINT0_ISR'; // Interrupt 7 Pin Change Interrupt 0
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procedure PCINT1_ISR; external name 'PCINT1_ISR'; // Interrupt 8 Pin Change Interrupt 1
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procedure WDT_ISR; external name 'WDT_ISR'; // Interrupt 9 Watchdog Timeout Interrupt
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procedure BGSCD_ISR; external name 'BGSCD_ISR'; // Interrupt 10 Bandgap Buffer Short Circuit Detected
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procedure CHDET_ISR; external name 'CHDET_ISR'; // Interrupt 11 Charger Detect
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procedure TIMER1_IC_ISR; external name 'TIMER1_IC_ISR'; // Interrupt 12 Timer 1 Input capture
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procedure TIMER1_COMPA_ISR; external name 'TIMER1_COMPA_ISR'; // Interrupt 13 Timer 1 Compare Match A
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procedure TIMER1_COMPB_ISR; external name 'TIMER1_COMPB_ISR'; // Interrupt 14 Timer 1 Compare Match B
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procedure TIMER1_OVF_ISR; external name 'TIMER1_OVF_ISR'; // Interrupt 15 Timer 1 overflow
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procedure TIMER0_IC_ISR; external name 'TIMER0_IC_ISR'; // Interrupt 16 Timer 0 Input Capture
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procedure TIMER0_COMPA_ISR; external name 'TIMER0_COMPA_ISR'; // Interrupt 17 Timer 0 Comapre Match A
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procedure TIMER0_COMPB_ISR; external name 'TIMER0_COMPB_ISR'; // Interrupt 18 Timer 0 Compare Match B
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procedure TIMER0_OVF_ISR; external name 'TIMER0_OVF_ISR'; // Interrupt 19 Timer 0 Overflow
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procedure TWIBUSCD_ISR; external name 'TWIBUSCD_ISR'; // Interrupt 20 Two-Wire Bus Connect/Disconnect
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procedure TWI_ISR; external name 'TWI_ISR'; // Interrupt 21 Two-Wire Serial Interface
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procedure SPI_STC_ISR; external name 'SPI_STC_ISR'; // Interrupt 22 SPI Serial transfer complete
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procedure VADC_ISR; external name 'VADC_ISR'; // Interrupt 23 Voltage ADC Conversion Complete
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procedure CCADC_CONV_ISR; external name 'CCADC_CONV_ISR'; // Interrupt 24 Coulomb Counter ADC Conversion Complete
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procedure CCADC_REG_CUR_ISR; external name 'CCADC_REG_CUR_ISR'; // Interrupt 25 Coloumb Counter ADC Regular Current
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procedure CCADC_ACC_ISR; external name 'CCADC_ACC_ISR'; // Interrupt 26 Coloumb Counter ADC Accumulator
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procedure EE_READY_ISR; external name 'EE_READY_ISR'; // Interrupt 27 EEPROM Ready
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procedure SPM_ISR; external name 'SPM_ISR'; // Interrupt 28 SPM Ready
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procedure _FPC_start; assembler; nostackframe;
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label
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_start;
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asm
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.init
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.globl _start
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jmp _start
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jmp BPINT_ISR
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jmp VREGMON_ISR
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jmp INT0_ISR
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jmp INT1_ISR
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jmp INT2_ISR
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jmp INT3_ISR
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jmp PCINT0_ISR
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jmp PCINT1_ISR
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jmp WDT_ISR
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jmp BGSCD_ISR
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jmp CHDET_ISR
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jmp TIMER1_IC_ISR
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jmp TIMER1_COMPA_ISR
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jmp TIMER1_COMPB_ISR
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jmp TIMER1_OVF_ISR
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jmp TIMER0_IC_ISR
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jmp TIMER0_COMPA_ISR
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jmp TIMER0_COMPB_ISR
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jmp TIMER0_OVF_ISR
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jmp TWIBUSCD_ISR
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jmp TWI_ISR
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jmp SPI_STC_ISR
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jmp VADC_ISR
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jmp CCADC_CONV_ISR
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jmp CCADC_REG_CUR_ISR
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jmp CCADC_ACC_ISR
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jmp EE_READY_ISR
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jmp SPM_ISR
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{$i start.inc}
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.weak BPINT_ISR
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.weak VREGMON_ISR
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.weak INT0_ISR
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.weak INT1_ISR
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.weak INT2_ISR
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.weak INT3_ISR
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.weak PCINT0_ISR
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.weak PCINT1_ISR
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.weak WDT_ISR
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.weak BGSCD_ISR
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.weak CHDET_ISR
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.weak TIMER1_IC_ISR
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.weak TIMER1_COMPA_ISR
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.weak TIMER1_COMPB_ISR
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.weak TIMER1_OVF_ISR
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.weak TIMER0_IC_ISR
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.weak TIMER0_COMPA_ISR
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.weak TIMER0_COMPB_ISR
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.weak TIMER0_OVF_ISR
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.weak TWIBUSCD_ISR
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.weak TWI_ISR
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.weak SPI_STC_ISR
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.weak VADC_ISR
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.weak CCADC_CONV_ISR
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.weak CCADC_REG_CUR_ISR
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.weak CCADC_ACC_ISR
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.weak EE_READY_ISR
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.weak SPM_ISR
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.set BPINT_ISR, Default_IRQ_handler
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.set VREGMON_ISR, Default_IRQ_handler
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.set INT0_ISR, Default_IRQ_handler
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.set INT1_ISR, Default_IRQ_handler
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.set INT2_ISR, Default_IRQ_handler
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.set INT3_ISR, Default_IRQ_handler
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.set PCINT0_ISR, Default_IRQ_handler
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.set PCINT1_ISR, Default_IRQ_handler
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.set WDT_ISR, Default_IRQ_handler
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.set BGSCD_ISR, Default_IRQ_handler
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.set CHDET_ISR, Default_IRQ_handler
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.set TIMER1_IC_ISR, Default_IRQ_handler
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.set TIMER1_COMPA_ISR, Default_IRQ_handler
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.set TIMER1_COMPB_ISR, Default_IRQ_handler
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.set TIMER1_OVF_ISR, Default_IRQ_handler
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.set TIMER0_IC_ISR, Default_IRQ_handler
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.set TIMER0_COMPA_ISR, Default_IRQ_handler
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.set TIMER0_COMPB_ISR, Default_IRQ_handler
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.set TIMER0_OVF_ISR, Default_IRQ_handler
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.set TWIBUSCD_ISR, Default_IRQ_handler
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.set TWI_ISR, Default_IRQ_handler
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.set SPI_STC_ISR, Default_IRQ_handler
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.set VADC_ISR, Default_IRQ_handler
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.set CCADC_CONV_ISR, Default_IRQ_handler
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.set CCADC_REG_CUR_ISR, Default_IRQ_handler
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.set CCADC_ACC_ISR, Default_IRQ_handler
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.set EE_READY_ISR, Default_IRQ_handler
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.set SPM_ISR, Default_IRQ_handler
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end;
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end.
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