mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-10-31 08:31:49 +01:00
55669f62b1
Made absolutevarsym use PUint instead of AWord for its offset to fix range errors. git-svn-id: trunk@31242 -
456 lines
18 KiB
ObjectPascal
456 lines
18 KiB
ObjectPascal
unit ATmega6450A;
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{$goto on}
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interface
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var
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// AD_CONVERTER
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ADMUX : byte absolute $00+$7C; // The ADC multiplexer Selection Register
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ADCSRA : byte absolute $00+$7A; // The ADC Control and Status register
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ADC : word absolute $00+$78; // ADC Data Register Bytes
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ADCL : byte absolute $00+$78; // ADC Data Register Bytes
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ADCH : byte absolute $00+$78+1; // ADC Data Register Bytes
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ADCSRB : byte absolute $00+$7B; // ADC Control and Status Register B
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DIDR0 : byte absolute $00+$7E; // Digital Input Disable Register 0
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// ANALOG_COMPARATOR
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ACSR : byte absolute $00+$50; // Analog Comparator Control And Status Register
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DIDR1 : byte absolute $00+$7F; // Digital Input Disable Register 1
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// SPI
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SPCR : byte absolute $00+$4C; // SPI Control Register
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SPSR : byte absolute $00+$4D; // SPI Status Register
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SPDR : byte absolute $00+$4E; // SPI Data Register
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// USI
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USIDR : byte absolute $00+$BA; // USI Data Register
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USISR : byte absolute $00+$B9; // USI Status Register
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USICR : byte absolute $00+$B8; // USI Control Register
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// USART0
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UDR0 : byte absolute $00+$C6; // USART I/O Data Register
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UCSR0A : byte absolute $00+$C0; // USART Control and Status Register A
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UCSR0B : byte absolute $00+$C1; // USART Control and Status Register B
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UCSR0C : byte absolute $00+$C2; // USART Control and Status Register C
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UBRR0 : word absolute $00+$C4; // USART Baud Rate Register Bytes
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UBRR0L : byte absolute $00+$C4; // USART Baud Rate Register Bytes
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UBRR0H : byte absolute $00+$C4+1; // USART Baud Rate Register Bytes
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// CPU
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SREG : byte absolute $00+$5F; // Status Register
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SP : word absolute $00+$5D; // Stack Pointer
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SPL : byte absolute $00+$5D; // Stack Pointer
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SPH : byte absolute $00+$5D+1; // Stack Pointer
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MCUCR : byte absolute $00+$55; // MCU Control Register
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MCUSR : byte absolute $00+$54; // MCU Status Register
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OSCCAL : byte absolute $00+$66; // Oscillator Calibration Value
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CLKPR : byte absolute $00+$61; // Clock Prescale Register
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PRR : byte absolute $00+$64; // Power Reduction Register
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SMCR : byte absolute $00+$53; // Sleep Mode Control Register
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GPIOR2 : byte absolute $00+$4B; // General Purpose IO Register 2
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GPIOR1 : byte absolute $00+$4A; // General Purpose IO Register 1
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GPIOR0 : byte absolute $00+$3E; // General Purpose IO Register 0
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// JTAG
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OCDR : byte absolute $00+$51; // On-Chip Debug Related Register in I/O Memory
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// EEPROM
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EEAR : word absolute $00+$41; // EEPROM Read/Write Access Bytes
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EEARL : byte absolute $00+$41; // EEPROM Read/Write Access Bytes
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EEARH : byte absolute $00+$41+1; // EEPROM Read/Write Access Bytes
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EEDR : byte absolute $00+$40; // EEPROM Data Register
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EECR : byte absolute $00+$3F; // EEPROM Control Register
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// PORTA
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PORTA : byte absolute $00+$22; // Port A Data Register
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DDRA : byte absolute $00+$21; // Port A Data Direction Register
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PINA : byte absolute $00+$20; // Port A Input Pins
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// PORTB
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PORTB : byte absolute $00+$25; // Port B Data Register
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DDRB : byte absolute $00+$24; // Port B Data Direction Register
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PINB : byte absolute $00+$23; // Port B Input Pins
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// PORTC
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PORTC : byte absolute $00+$28; // Port C Data Register
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DDRC : byte absolute $00+$27; // Port C Data Direction Register
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PINC : byte absolute $00+$26; // Port C Input Pins
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// PORTD
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PORTD : byte absolute $00+$2B; // Port D Data Register
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DDRD : byte absolute $00+$2A; // Port D Data Direction Register
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PIND : byte absolute $00+$29; // Port D Input Pins
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// PORTE
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PORTE : byte absolute $00+$2E; // Data Register, Port E
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DDRE : byte absolute $00+$2D; // Data Direction Register, Port E
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PINE : byte absolute $00+$2C; // Input Pins, Port E
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// PORTF
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PORTF : byte absolute $00+$31; // Data Register, Port F
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DDRF : byte absolute $00+$30; // Data Direction Register, Port F
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PINF : byte absolute $00+$2F; // Input Pins, Port F
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// PORTG
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PORTG : byte absolute $00+$34; // Port G Data Register
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DDRG : byte absolute $00+$33; // Port G Data Direction Register
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PING : byte absolute $00+$32; // Port G Input Pins
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// TIMER_COUNTER_0
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TCCR0A : byte absolute $00+$44; // Timer/Counter0 Control Register
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TCNT0 : byte absolute $00+$46; // Timer/Counter0
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OCR0A : byte absolute $00+$47; // Timer/Counter0 Output Compare Register
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TIMSK0 : byte absolute $00+$6E; // Timer/Counter0 Interrupt Mask Register
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TIFR0 : byte absolute $00+$35; // Timer/Counter0 Interrupt Flag register
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GTCCR : byte absolute $00+$43; // General Timer/Control Register
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// TIMER_COUNTER_2
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TCCR2A : byte absolute $00+$B0; // Timer/Counter2 Control Register
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TCNT2 : byte absolute $00+$B2; // Timer/Counter2
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OCR2A : byte absolute $00+$B3; // Timer/Counter2 Output Compare Register
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TIMSK2 : byte absolute $00+$70; // Timer/Counter2 Interrupt Mask register
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TIFR2 : byte absolute $00+$37; // Timer/Counter2 Interrupt Flag Register
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ASSR : byte absolute $00+$B6; // Asynchronous Status Register
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// TIMER_COUNTER_1
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TCCR1A : byte absolute $00+$80; // Timer/Counter1 Control Register A
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TCCR1B : byte absolute $00+$81; // Timer/Counter1 Control Register B
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TCCR1C : byte absolute $00+$82; // Timer/Counter 1 Control Register C
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TCNT1 : word absolute $00+$84; // Timer/Counter1 Bytes
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TCNT1L : byte absolute $00+$84; // Timer/Counter1 Bytes
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TCNT1H : byte absolute $00+$84+1; // Timer/Counter1 Bytes
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OCR1A : word absolute $00+$88; // Timer/Counter1 Output Compare Register A Bytes
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OCR1AL : byte absolute $00+$88; // Timer/Counter1 Output Compare Register A Bytes
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OCR1AH : byte absolute $00+$88+1; // Timer/Counter1 Output Compare Register A Bytes
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OCR1B : word absolute $00+$8A; // Timer/Counter1 Output Compare Register B Bytes
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OCR1BL : byte absolute $00+$8A; // Timer/Counter1 Output Compare Register B Bytes
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OCR1BH : byte absolute $00+$8A+1; // Timer/Counter1 Output Compare Register B Bytes
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ICR1 : word absolute $00+$86; // Timer/Counter1 Input Capture Register Bytes
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ICR1L : byte absolute $00+$86; // Timer/Counter1 Input Capture Register Bytes
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ICR1H : byte absolute $00+$86+1; // Timer/Counter1 Input Capture Register Bytes
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TIMSK1 : byte absolute $00+$6F; // Timer/Counter1 Interrupt Mask Register
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TIFR1 : byte absolute $00+$36; // Timer/Counter1 Interrupt Flag register
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// WATCHDOG
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WDTCR : byte absolute $00+$60; // Watchdog Timer Control Register
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// BOOT_LOAD
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SPMCSR : byte absolute $00+$57; // Store Program Memory Control Register
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// PORTH
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PORTH : byte absolute $00+$DA; // PORT H Data Register
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DDRH : byte absolute $00+$D9; // PORT H Data Direction Register
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PINH : byte absolute $00+$D8; // PORT H Input Pins
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// PORTJ
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PORTJ : byte absolute $00+$DD; // PORT J Data Register
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DDRJ : byte absolute $00+$DC; // PORT J Data Direction Register
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PINJ : byte absolute $00+$DB; // PORT J Input Pins
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// EXTERNAL_INTERRUPT
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EICRA : byte absolute $00+$69; // External Interrupt Control Register A
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EIMSK : byte absolute $00+$3D; // External Interrupt Mask Register
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EIFR : byte absolute $00+$3C; // External Interrupt Flag Register
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PCMSK3 : byte absolute $00+$73; // Pin Change Mask Register 3
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PCMSK2 : byte absolute $00+$6D; // Pin Change Mask Register 2
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PCMSK1 : byte absolute $00+$6C; // Pin Change Mask Register 1
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PCMSK0 : byte absolute $00+$6B; // Pin Change Mask Register 0
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const
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// ADMUX
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REFS = 6; // Reference Selection Bits
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ADLAR = 5; // Left Adjust Result
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MUX = 0; // Analog Channel and Gain Selection Bits
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// ADCSRA
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ADEN = 7; // ADC Enable
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ADSC = 6; // ADC Start Conversion
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ADATE = 5; // ADC Auto Trigger Enable
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ADIF = 4; // ADC Interrupt Flag
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ADIE = 3; // ADC Interrupt Enable
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ADPS = 0; // ADC Prescaler Select Bits
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// ADCSRB
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ADTS = 0; // ADC Auto Trigger Sources
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// DIDR0
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ADC7D = 7; // ADC7 Digital input Disable
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ADC6D = 6; // ADC6 Digital input Disable
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ADC5D = 5; // ADC5 Digital input Disable
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ADC4D = 4; // ADC4 Digital input Disable
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ADC3D = 3; // ADC3 Digital input Disable
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ADC2D = 2; // ADC2 Digital input Disable
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ADC1D = 1; // ADC1 Digital input Disable
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ADC0D = 0; // ADC0 Digital input Disable
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// ADCSRB
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ACME = 6; // Analog Comparator Multiplexer Enable
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// ACSR
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ACD = 7; // Analog Comparator Disable
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ACBG = 6; // Analog Comparator Bandgap Select
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ACO = 5; // Analog Compare Output
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ACI = 4; // Analog Comparator Interrupt Flag
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ACIE = 3; // Analog Comparator Interrupt Enable
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ACIC = 2; // Analog Comparator Input Capture Enable
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ACIS = 0; // Analog Comparator Interrupt Mode Select bits
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// DIDR1
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AIN1D = 1; // AIN1 Digital Input Disable
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AIN0D = 0; // AIN0 Digital Input Disable
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// SPCR
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SPIE = 7; // SPI Interrupt Enable
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SPE = 6; // SPI Enable
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DORD = 5; // Data Order
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MSTR = 4; // Master/Slave Select
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CPOL = 3; // Clock polarity
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CPHA = 2; // Clock Phase
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SPR = 0; // SPI Clock Rate Selects
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// SPSR
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SPIF = 7; // SPI Interrupt Flag
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WCOL = 6; // Write Collision Flag
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SPI2X = 0; // Double SPI Speed Bit
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// USISR
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USISIF = 7; // Start Condition Interrupt Flag
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USIOIF = 6; // Counter Overflow Interrupt Flag
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USIPF = 5; // Stop Condition Flag
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USIDC = 4; // Data Output Collision
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USICNT = 0; // USI Counter Value Bits
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// USICR
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USISIE = 7; // Start Condition Interrupt Enable
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USIOIE = 6; // Counter Overflow Interrupt Enable
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USIWM = 4; // USI Wire Mode Bits
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USICS = 2; // USI Clock Source Select Bits
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USICLK = 1; // Clock Strobe
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USITC = 0; // Toggle Clock Port Pin
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// UCSR0A
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RXC0 = 7; // USART Receive Complete
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TXC0 = 6; // USART Transmit Complete
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UDRE0 = 5; // USART Data Register Empty
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FE0 = 4; // Framing Error
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DOR0 = 3; // Data OverRun
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UPE0 = 2; // USART Parity Error
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U2X0 = 1; // Double the USART Transmission Speed
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MPCM0 = 0; // Multi-processor Communication Mode
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// UCSR0B
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RXCIE0 = 7; // RX Complete Interrupt Enable
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TXCIE0 = 6; // TX Complete Interrupt Enable
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UDRIE0 = 5; // USART Data Register Empty Interrupt Enable
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RXEN0 = 4; // Receiver Enable
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TXEN0 = 3; // Transmitter Enable
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UCSZ02 = 2; // Character Size
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RXB80 = 1; // Receive Data Bit 8
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TXB80 = 0; // Transmit Data Bit 8
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// UCSR0C
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UMSEL0 = 6; // USART Mode Select
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UPM0 = 4; // Parity Mode Bits
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USBS0 = 3; // Stop Bit Select
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UCSZ0 = 1; // Character Size
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UCPOL0 = 0; // Clock Polarity
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// SREG
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I = 7; // Global Interrupt Enable
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T = 6; // Bit Copy Storage
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H = 5; // Half Carry Flag
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S = 4; // Sign Bit
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V = 3; // Two's Complement Overflow Flag
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N = 2; // Negative Flag
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Z = 1; // Zero Flag
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C = 0; // Carry Flag
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// MCUCR
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PUD = 4; // Pull-up disable
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IVSEL = 1; // Interrupt Vector Select
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IVCE = 0; // Interrupt Vector Change Enable
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// MCUSR
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JTRF = 4; // JTAG Reset Flag
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WDRF = 3; // Watchdog Reset Flag
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BORF = 2; // Brown-out Reset Flag
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EXTRF = 1; // External Reset Flag
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PORF = 0; // Power-on reset flag
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// CLKPR
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CLKPCE = 7; // Clock Prescaler Change Enable
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CLKPS = 0; // Clock Prescaler Select Bits
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// PRR
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PRLCD = 4; // Power Reduction LCD
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PRTIM1 = 3; // Power Reduction Timer/Counter1
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PRSPI = 2; // Power Reduction Serial Peripheral Interface
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PRUSART0 = 1; // Power Reduction USART
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PRADC = 0; // Power Reduction ADC
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// SMCR
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SM = 1; // Sleep Mode Select bits
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SE = 0; // Sleep Enable
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// MCUCR
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JTD = 7; // JTAG Interface Disable
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// MCUSR
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// EECR
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EERIE = 3; // EEPROM Ready Interrupt Enable
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EEMWE = 2; // EEPROM Master Write Enable
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EEWE = 1; // EEPROM Write Enable
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EERE = 0; // EEPROM Read Enable
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// TCCR0A
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FOC0A = 7; // Force Output Compare
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WGM00 = 6; // Waveform Generation Mode 0
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COM0A = 4; // Compare Match Output Modes
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WGM01 = 3; // Waveform Generation Mode 1
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CS0 = 0; // Clock Selects
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// TIMSK0
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OCIE0A = 1; // Timer/Counter0 Output Compare Match Interrupt Enable
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TOIE0 = 0; // Timer/Counter0 Overflow Interrupt Enable
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// TIFR0
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OCF0A = 1; // Timer/Counter0 Output Compare Flag 0
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TOV0 = 0; // Timer/Counter0 Overflow Flag
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// GTCCR
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TSM = 7; // Timer/Counter Synchronization Mode
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PSR310 = 0; // Prescaler Reset Timer/Counter1 and Timer/Counter0
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// TCCR2A
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FOC2A = 7; // Force Output Compare A
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WGM20 = 6; // Waveform Generation Mode
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COM2A = 4; // Compare Output Mode bits
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WGM21 = 3; // Waveform Generation Mode
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CS2 = 0; // Clock Select bits
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// TIMSK2
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OCIE2A = 1; // Timer/Counter2 Output Compare Match Interrupt Enable
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TOIE2 = 0; // Timer/Counter2 Overflow Interrupt Enable
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// TIFR2
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OCF2A = 1; // Timer/Counter2 Output Compare Flag 2
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TOV2 = 0; // Timer/Counter2 Overflow Flag
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// GTCCR
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PSR2 = 1; // Prescaler Reset Timer/Counter2
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// ASSR
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EXCLK = 4; // Enable External Clock Interrupt
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AS2 = 3; // AS2: Asynchronous Timer/Counter2
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TCN2UB = 2; // TCN2UB: Timer/Counter2 Update Busy
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OCR2UB = 1; // Output Compare Register2 Update Busy
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TCR2UB = 0; // TCR2UB: Timer/Counter Control Register2 Update Busy
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// TCCR1A
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COM1A = 6; // Compare Output Mode 1A, bits
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COM1B = 4; // Compare Output Mode 1B, bits
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WGM1 = 0; // Waveform Generation Mode
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// TCCR1B
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ICNC1 = 7; // Input Capture 1 Noise Canceler
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ICES1 = 6; // Input Capture 1 Edge Select
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CS1 = 0; // Prescaler source of Timer/Counter 1
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// TCCR1C
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FOC1A = 7; // Force Output Compare 1A
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FOC1B = 6; // Force Output Compare 1B
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// TIMSK1
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ICIE1 = 5; // Timer/Counter1 Input Capture Interrupt Enable
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OCIE1B = 2; // Timer/Counter1 Output Compare B Match Interrupt Enable
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OCIE1A = 1; // Timer/Counter1 Output Compare A Match Interrupt Enable
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TOIE1 = 0; // Timer/Counter1 Overflow Interrupt Enable
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// TIFR1
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ICF1 = 5; // Input Capture Flag 1
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OCF1B = 2; // Output Compare Flag 1B
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OCF1A = 1; // Output Compare Flag 1A
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TOV1 = 0; // Timer/Counter1 Overflow Flag
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// WDTCR
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WDCE = 4; // Watchdog Change Enable
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WDE = 3; // Watch Dog Enable
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WDP = 0; // Watch Dog Timer Prescaler bits
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// SPMCSR
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SPMIE = 7; // SPM Interrupt Enable
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RWWSB = 6; // Read While Write Section Busy
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RWWSRE = 4; // Read While Write section read enable
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BLBSET = 3; // Boot Lock Bit Set
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PGWRT = 2; // Page Write
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PGERS = 1; // Page Erase
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SPMEN = 0; // Store Program Memory Enable
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// EICRA
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ISC01 = 1; // External Interrupt Sense Control 0 Bit 1
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ISC00 = 0; // External Interrupt Sense Control 0 Bit 0
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// EIMSK
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PCIE = 4; // Pin Change Interrupt Enables
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INT0 = 0; // External Interrupt Request 0 Enable
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// EIFR
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PCIF = 4; // Pin Change Interrupt Flags
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INTF0 = 0; // External Interrupt Flag 0
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implementation
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{$i avrcommon.inc}
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procedure INT0_ISR; external name 'INT0_ISR'; // Interrupt 1 External Interrupt Request 0
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procedure PCINT0_ISR; external name 'PCINT0_ISR'; // Interrupt 2 Pin Change Interrupt Request 0
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procedure PCINT1_ISR; external name 'PCINT1_ISR'; // Interrupt 3 Pin Change Interrupt Request 1
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procedure TIMER2_COMP_ISR; external name 'TIMER2_COMP_ISR'; // Interrupt 4 Timer/Counter2 Compare Match
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procedure TIMER2_OVF_ISR; external name 'TIMER2_OVF_ISR'; // Interrupt 5 Timer/Counter2 Overflow
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procedure TIMER1_CAPT_ISR; external name 'TIMER1_CAPT_ISR'; // Interrupt 6 Timer/Counter1 Capture Event
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procedure TIMER1_COMPA_ISR; external name 'TIMER1_COMPA_ISR'; // Interrupt 7 Timer/Counter1 Compare Match A
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procedure TIMER1_COMPB_ISR; external name 'TIMER1_COMPB_ISR'; // Interrupt 8 Timer/Counter Compare Match B
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procedure TIMER1_OVF_ISR; external name 'TIMER1_OVF_ISR'; // Interrupt 9 Timer/Counter1 Overflow
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procedure TIMER0_COMP_ISR; external name 'TIMER0_COMP_ISR'; // Interrupt 10 Timer/Counter0 Compare Match
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procedure TIMER0_OVF_ISR; external name 'TIMER0_OVF_ISR'; // Interrupt 11 Timer/Counter0 Overflow
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procedure SPI__STC_ISR; external name 'SPI__STC_ISR'; // Interrupt 12 SPI Serial Transfer Complete
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procedure USART__RX_ISR; external name 'USART__RX_ISR'; // Interrupt 13 USART, Rx Complete
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procedure USART__UDRE_ISR; external name 'USART__UDRE_ISR'; // Interrupt 14 USART Data register Empty
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procedure USART0__TX_ISR; external name 'USART0__TX_ISR'; // Interrupt 15 USART0, Tx Complete
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procedure USI_START_ISR; external name 'USI_START_ISR'; // Interrupt 16 USI Start Condition
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procedure USI_OVERFLOW_ISR; external name 'USI_OVERFLOW_ISR'; // Interrupt 17 USI Overflow
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procedure ANALOG_COMP_ISR; external name 'ANALOG_COMP_ISR'; // Interrupt 18 Analog Comparator
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procedure ADC_ISR; external name 'ADC_ISR'; // Interrupt 19 ADC Conversion Complete
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procedure EE_READY_ISR; external name 'EE_READY_ISR'; // Interrupt 20 EEPROM Ready
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procedure SPM_READY_ISR; external name 'SPM_READY_ISR'; // Interrupt 21 Store Program Memory Read
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procedure NOT_USED_ISR; external name 'NOT_USED_ISR'; // Interrupt 22 RESERVED
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procedure PCINT2_ISR; external name 'PCINT2_ISR'; // Interrupt 23 Pin Change Interrupt Request 2
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procedure PCINT3_ISR; external name 'PCINT3_ISR'; // Interrupt 24 Pin Change Interrupt Request 3
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procedure _FPC_start; assembler; nostackframe;
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label
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_start;
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asm
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.init
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.globl _start
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jmp _start
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jmp INT0_ISR
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jmp PCINT0_ISR
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jmp PCINT1_ISR
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jmp TIMER2_COMP_ISR
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jmp TIMER2_OVF_ISR
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jmp TIMER1_CAPT_ISR
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jmp TIMER1_COMPA_ISR
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jmp TIMER1_COMPB_ISR
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jmp TIMER1_OVF_ISR
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jmp TIMER0_COMP_ISR
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jmp TIMER0_OVF_ISR
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jmp SPI__STC_ISR
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jmp USART__RX_ISR
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jmp USART__UDRE_ISR
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jmp USART0__TX_ISR
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jmp USI_START_ISR
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jmp USI_OVERFLOW_ISR
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jmp ANALOG_COMP_ISR
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jmp ADC_ISR
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jmp EE_READY_ISR
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jmp SPM_READY_ISR
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jmp NOT_USED_ISR
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jmp PCINT2_ISR
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jmp PCINT3_ISR
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|
|
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{$i start.inc}
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.weak INT0_ISR
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.weak PCINT0_ISR
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.weak PCINT1_ISR
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.weak TIMER2_COMP_ISR
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.weak TIMER2_OVF_ISR
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.weak TIMER1_CAPT_ISR
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.weak TIMER1_COMPA_ISR
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.weak TIMER1_COMPB_ISR
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.weak TIMER1_OVF_ISR
|
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.weak TIMER0_COMP_ISR
|
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.weak TIMER0_OVF_ISR
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.weak SPI__STC_ISR
|
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.weak USART__RX_ISR
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.weak USART__UDRE_ISR
|
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.weak USART0__TX_ISR
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.weak USI_START_ISR
|
|
.weak USI_OVERFLOW_ISR
|
|
.weak ANALOG_COMP_ISR
|
|
.weak ADC_ISR
|
|
.weak EE_READY_ISR
|
|
.weak SPM_READY_ISR
|
|
.weak NOT_USED_ISR
|
|
.weak PCINT2_ISR
|
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.weak PCINT3_ISR
|
|
|
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.set INT0_ISR, Default_IRQ_handler
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.set PCINT0_ISR, Default_IRQ_handler
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.set PCINT1_ISR, Default_IRQ_handler
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.set TIMER2_COMP_ISR, Default_IRQ_handler
|
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.set TIMER2_OVF_ISR, Default_IRQ_handler
|
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.set TIMER1_CAPT_ISR, Default_IRQ_handler
|
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.set TIMER1_COMPA_ISR, Default_IRQ_handler
|
|
.set TIMER1_COMPB_ISR, Default_IRQ_handler
|
|
.set TIMER1_OVF_ISR, Default_IRQ_handler
|
|
.set TIMER0_COMP_ISR, Default_IRQ_handler
|
|
.set TIMER0_OVF_ISR, Default_IRQ_handler
|
|
.set SPI__STC_ISR, Default_IRQ_handler
|
|
.set USART__RX_ISR, Default_IRQ_handler
|
|
.set USART__UDRE_ISR, Default_IRQ_handler
|
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.set USART0__TX_ISR, Default_IRQ_handler
|
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.set USI_START_ISR, Default_IRQ_handler
|
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.set USI_OVERFLOW_ISR, Default_IRQ_handler
|
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.set ANALOG_COMP_ISR, Default_IRQ_handler
|
|
.set ADC_ISR, Default_IRQ_handler
|
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.set EE_READY_ISR, Default_IRQ_handler
|
|
.set SPM_READY_ISR, Default_IRQ_handler
|
|
.set NOT_USED_ISR, Default_IRQ_handler
|
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.set PCINT2_ISR, Default_IRQ_handler
|
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.set PCINT3_ISR, Default_IRQ_handler
|
|
end;
|
|
|
|
end.
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