mirror of
https://gitlab.com/freepascal.org/fpc/source.git
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55669f62b1
Made absolutevarsym use PUint instead of AWord for its offset to fix range errors. git-svn-id: trunk@31242 -
218 lines
7.6 KiB
ObjectPascal
218 lines
7.6 KiB
ObjectPascal
unit ATtiny13A;
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{$goto on}
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interface
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var
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// AD_CONVERTER
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ADMUX : byte absolute $00+$27; // The ADC multiplexer Selection Register
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ADCSRA : byte absolute $00+$26; // The ADC Control and Status register
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ADC : word absolute $00+$24; // ADC Data Register Bytes
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ADCL : byte absolute $00+$24; // ADC Data Register Bytes
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ADCH : byte absolute $00+$24+1; // ADC Data Register Bytes
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ADCSRB : byte absolute $00+$23; // ADC Control and Status Register B
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DIDR0 : byte absolute $00+$34; // Digital Input Disable Register 0
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// ANALOG_COMPARATOR
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ACSR : byte absolute $00+$28; // Analog Comparator Control And Status Register
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// EEPROM
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EEAR : byte absolute $00+$3E; // EEPROM Read/Write Access
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EEDR : byte absolute $00+$3D; // EEPROM Data Register
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EECR : byte absolute $00+$3C; // EEPROM Control Register
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// PORTB
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PORTB : byte absolute $00+$38; // Data Register, Port B
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DDRB : byte absolute $00+$37; // Data Direction Register, Port B
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PINB : byte absolute $00+$36; // Input Pins, Port B
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// EXTERNAL_INTERRUPT
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MCUCR : byte absolute $00+$55; // MCU Control Register
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GIMSK : byte absolute $00+$5B; // General Interrupt Mask Register
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GIFR : byte absolute $00+$5A; // General Interrupt Flag register
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PCMSK : byte absolute $00+$35; // Pin Change Enable Mask
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// TIMER_COUNTER_0
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TIMSK0 : byte absolute $00+$59; // Timer/Counter0 Interrupt Mask Register
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TIFR0 : byte absolute $00+$58; // Timer/Counter0 Interrupt Flag register
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OCR0A : byte absolute $00+$56; // Timer/Counter0 Output Compare Register
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TCCR0A : byte absolute $00+$4F; // Timer/Counter Control Register A
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TCNT0 : byte absolute $00+$52; // Timer/Counter0
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TCCR0B : byte absolute $00+$53; // Timer/Counter Control Register B
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OCR0B : byte absolute $00+$49; // Timer/Counter0 Output Compare Register
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GTCCR : byte absolute $00+$48; // General Timer Conuter Register
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// WATCHDOG
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WDTCR : byte absolute $00+$41; // Watchdog Timer Control Register
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// CPU
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SREG : byte absolute $00+$5F; // Status Register
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SPL : byte absolute $00+$5D; // Stack Pointer Low Byte
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MCUSR : byte absolute $00+$54; // MCU Status register
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OSCCAL : byte absolute $00+$51; // Oscillator Calibration Register
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CLKPR : byte absolute $00+$46; // Clock Prescale Register
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DWDR : byte absolute $00+$4E; // Debug Wire Data Register
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SPMCSR : byte absolute $00+$57; // Store Program Memory Control and Status Register
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PRR : byte absolute $00+$45; // Power Reduction Register
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BODCR : byte absolute $00+$50; // BOD Control Register
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const
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// ADMUX
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REFS0 = 6; // Reference Selection Bit 0
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ADLAR = 5; // Left Adjust Result
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MUX = 0; // Analog Channel and Gain Selection Bits
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// ADCSRA
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ADEN = 7; // ADC Enable
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ADSC = 6; // ADC Start Conversion
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ADATE = 5; // ADC Auto Trigger Enable
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ADIF = 4; // ADC Interrupt Flag
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ADIE = 3; // ADC Interrupt Enable
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ADPS = 0; // ADC Prescaler Select Bits
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// ADCSRB
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ADTS = 0; // ADC Auto Trigger Sources
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// DIDR0
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ADC0D = 5; // ADC0 Digital input Disable
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ADC2D = 4; // ADC2 Digital input Disable
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ADC3D = 3; // ADC3 Digital input Disable
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ADC1D = 2; // ADC2 Digital input Disable
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// ADCSRB
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ACME = 6; // Analog Comparator Multiplexer Enable
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// ACSR
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ACD = 7; // Analog Comparator Disable
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ACBG = 6; // Analog Comparator Bandgap Select
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ACO = 5; // Analog Compare Output
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ACI = 4; // Analog Comparator Interrupt Flag
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ACIE = 3; // Analog Comparator Interrupt Enable
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ACIS = 0; // Analog Comparator Interrupt Mode Select bits
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// DIDR0
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AIN1D = 1; // AIN1 Digital Input Disable
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AIN0D = 0; // AIN0 Digital Input Disable
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// EECR
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EEPM = 4; //
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EERIE = 3; // EEProm Ready Interrupt Enable
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EEMWE = 2; // EEPROM Master Write Enable
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EEWE = 1; // EEPROM Write Enable
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EERE = 0; // EEPROM Read Enable
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// MCUCR
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ISC01 = 1; // Interrupt Sense Control 0 Bit 1
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ISC00 = 0; // Interrupt Sense Control 0 Bit 0
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// GIMSK
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INT0 = 6; // External Interrupt Request 0 Enable
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PCIE = 5; // Pin Change Interrupt Enable
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// GIFR
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INTF0 = 6; // External Interrupt Flag 0
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PCIF = 5; // Pin Change Interrupt Flag
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// TIMSK0
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OCIE0B = 3; // Timer/Counter0 Output Compare Match B Interrupt Enable
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OCIE0A = 2; // Timer/Counter0 Output Compare Match A Interrupt Enable
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TOIE0 = 1; // Timer/Counter0 Overflow Interrupt Enable
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// TIFR0
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OCF0B = 3; // Timer/Counter0 Output Compare Flag 0B
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OCF0A = 2; // Timer/Counter0 Output Compare Flag 0A
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TOV0 = 1; // Timer/Counter0 Overflow Flag
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// TCCR0A
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COM0A = 6; // Compare Match Output A Mode
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COM0B = 4; // Compare Match Output B Mode
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WGM0 = 0; // Waveform Generation Mode
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// TCCR0B
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FOC0A = 7; // Force Output Compare A
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FOC0B = 6; // Force Output Compare B
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WGM02 = 3; // Waveform Generation Mode
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CS0 = 0; // Clock Select
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// GTCCR
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TSM = 7; // Timer/Counter Synchronization Mode
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PSR10 = 0; // Prescaler Reset Timer/Counter0
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// WDTCR
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WDTIF = 7; // Watchdog Timeout Interrupt Flag
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WDTIE = 6; // Watchdog Timeout Interrupt Enable
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WDP = 0; // Watchdog Timer Prescaler Bits
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WDCE = 4; // Watchdog Change Enable
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WDE = 3; // Watch Dog Enable
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// SREG
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I = 7; // Global Interrupt Enable
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T = 6; // Bit Copy Storage
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H = 5; // Half Carry Flag
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S = 4; // Sign Bit
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V = 3; // Two's Complement Overflow Flag
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N = 2; // Negative Flag
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Z = 1; // Zero Flag
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C = 0; // Carry Flag
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// MCUCR
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PUD = 6; // Pull-up Disable
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SE = 5; // Sleep Enable
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SM = 3; // Sleep Mode Select Bits
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ISC0 = 0; // Interrupt Sense Control 0 bits
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// MCUSR
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WDRF = 3; // Watchdog Reset Flag
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BORF = 2; // Brown-out Reset Flag
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EXTRF = 1; // External Reset Flag
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PORF = 0; // Power-On Reset Flag
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// CLKPR
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CLKPCE = 7; // Clock Prescaler Change Enable
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CLKPS = 0; // Clock Prescaler Select Bits
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// SPMCSR
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CTPB = 4; // Clear Temporary Page Buffer
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RFLB = 3; // Read Fuse and Lock Bits
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PGWRT = 2; // Page Write
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PGERS = 1; // Page Erase
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SPMEN = 0; // Store program Memory Enable
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// PRR
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PRTIM0 = 1; // Power Reduction Timer/Counter0
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PRADC = 0; // Power Reduction ADC
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// BODCR
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BPDS = 1; // BOD Power-Down in Power-Down Sleep
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BPDSE = 0; // BOD Power-Down Sleep Enable
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implementation
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{$define RELBRANCHES}
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{$i avrcommon.inc}
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procedure INT0_ISR; external name 'INT0_ISR'; // Interrupt 1 External Interrupt 0
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procedure PCINT0_ISR; external name 'PCINT0_ISR'; // Interrupt 2 External Interrupt Request 0
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procedure TIM0_OVF_ISR; external name 'TIM0_OVF_ISR'; // Interrupt 3 Timer/Counter0 Overflow
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procedure EE_RDY_ISR; external name 'EE_RDY_ISR'; // Interrupt 4 EEPROM Ready
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procedure ANA_COMP_ISR; external name 'ANA_COMP_ISR'; // Interrupt 5 Analog Comparator
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procedure TIM0_COMPA_ISR; external name 'TIM0_COMPA_ISR'; // Interrupt 6 Timer/Counter Compare Match A
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procedure TIM0_COMPB_ISR; external name 'TIM0_COMPB_ISR'; // Interrupt 7 Timer/Counter Compare Match B
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procedure WDT_ISR; external name 'WDT_ISR'; // Interrupt 8 Watchdog Time-out
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procedure ADC_ISR; external name 'ADC_ISR'; // Interrupt 9 ADC Conversion Complete
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procedure _FPC_start; assembler; nostackframe;
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label
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_start;
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asm
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.init
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.globl _start
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rjmp _start
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rjmp INT0_ISR
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rjmp PCINT0_ISR
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rjmp TIM0_OVF_ISR
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rjmp EE_RDY_ISR
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rjmp ANA_COMP_ISR
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rjmp TIM0_COMPA_ISR
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rjmp TIM0_COMPB_ISR
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rjmp WDT_ISR
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rjmp ADC_ISR
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{$i start.inc}
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.weak INT0_ISR
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.weak PCINT0_ISR
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.weak TIM0_OVF_ISR
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.weak EE_RDY_ISR
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.weak ANA_COMP_ISR
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.weak TIM0_COMPA_ISR
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.weak TIM0_COMPB_ISR
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.weak WDT_ISR
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.weak ADC_ISR
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.set INT0_ISR, Default_IRQ_handler
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.set PCINT0_ISR, Default_IRQ_handler
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.set TIM0_OVF_ISR, Default_IRQ_handler
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.set EE_RDY_ISR, Default_IRQ_handler
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.set ANA_COMP_ISR, Default_IRQ_handler
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.set TIM0_COMPA_ISR, Default_IRQ_handler
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.set TIM0_COMPB_ISR, Default_IRQ_handler
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.set WDT_ISR, Default_IRQ_handler
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.set ADC_ISR, Default_IRQ_handler
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end;
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end.
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