mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-10-31 23:49:28 +01:00
55669f62b1
Made absolutevarsym use PUint instead of AWord for its offset to fix range errors. git-svn-id: trunk@31242 -
221 lines
7.8 KiB
ObjectPascal
221 lines
7.8 KiB
ObjectPascal
unit ATtiny26;
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{$goto on}
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interface
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var
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// AD_CONVERTER
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ADMUX : byte absolute $00+$27; // The ADC multiplexer Selection Register
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ADCSR : byte absolute $00+$26; // The ADC Control and Status register
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ADC : word absolute $00+$24; // ADC Data Register Bytes
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ADCL : byte absolute $00+$24; // ADC Data Register Bytes
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ADCH : byte absolute $00+$24+1; // ADC Data Register Bytes
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// ANALOG_COMPARATOR
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ACSR : byte absolute $00+$28; // Analog Comparator Control And Status Register
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// USI
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USIDR : byte absolute $00+$2F; // USI Data Register
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USISR : byte absolute $00+$2E; // USI Status Register
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USICR : byte absolute $00+$2D; // USI Control Register
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// PORTA
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PORTA : byte absolute $00+$3B; // Port A Data Register
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DDRA : byte absolute $00+$3A; // Port A Data Direction Register
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PINA : byte absolute $00+$39; // Port A Input Pins
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// PORTB
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PORTB : byte absolute $00+$38; // Port B Data Register
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DDRB : byte absolute $00+$37; // Port B Data Direction Register
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PINB : byte absolute $00+$36; // Port B Input Pins
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// EEPROM
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EEAR : byte absolute $00+$3E; // EEPROM Read/Write Access
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EEDR : byte absolute $00+$3D; // EEPROM Data Register
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EECR : byte absolute $00+$3C; // EEPROM Control Register
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// WATCHDOG
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WDTCR : byte absolute $00+$41; // Watchdog Timer Control Register
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// CPU
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SREG : byte absolute $00+$5F; // Status Register
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SP : byte absolute $00+$5D; // Stack Pointer
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MCUCR : byte absolute $00+$55; // MCU Control Register
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MCUSR : byte absolute $00+$54; // MCU Status register
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OSCCAL : byte absolute $00+$51; // Status Register
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// TIMER_COUNTER_0
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TIMSK : byte absolute $00+$59; // Timer/Counter Interrupt Mask Register
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TIFR : byte absolute $00+$58; // Timer/Counter Interrupt Flag register
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TCCR0 : byte absolute $00+$53; // Timer/Counter0 Control Register
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TCNT0 : byte absolute $00+$52; // Timer Counter 0
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// TIMER_COUNTER_1
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TCCR1A : byte absolute $00+$50; // Timer/Counter Control Register A
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TCCR1B : byte absolute $00+$4F; // Timer/Counter Control Register B
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TCNT1 : byte absolute $00+$4E; // Timer/Counter Register
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OCR1A : byte absolute $00+$4D; // Output Compare Register
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OCR1B : byte absolute $00+$4C; // Output Compare Register
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OCR1C : byte absolute $00+$4B; // Output Compare Register
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PLLCSR : byte absolute $00+$49; // PLL Control and Status Register
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// EXTERNAL_INTERRUPT
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GIMSK : byte absolute $00+$5B; // General Interrupt Mask Register
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GIFR : byte absolute $00+$5A; // General Interrupt Flag register
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const
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// ADMUX
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REFS = 6; // Reference Selection Bits
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ADLAR = 5; // Left Adjust Result
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MUX = 0; // Analog Channel and Gain Selection Bits
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// ADCSR
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ADEN = 7; // ADC Enable
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ADSC = 6; // ADC Start Conversion
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ADFR = 5; // ADC Free Running Select
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ADIF = 4; // ADC Interrupt Flag
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ADIE = 3; // ADC Interrupt Enable
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ADPS = 0; // ADC Prescaler Select Bits
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// ACSR
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ACD = 7; // Analog Comparator Disable
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ACBG = 6; // Analog Comparator Bandgap Select
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ACO = 5; // Analog Compare Output
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ACI = 4; // Analog Comparator Interrupt Flag
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ACIE = 3; // Analog Comparator Interrupt Enable
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ACME = 2; // Analog Comparator Multiplexer Enable
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ACIS = 0; // Analog Comparator Interrupt Mode Select bits
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// USISR
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USISIF = 7; // Start Condition Interrupt Flag
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USIOIF = 6; // Counter Overflow Interrupt Flag
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USIPF = 5; // Stop Condition Flag
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USIDC = 4; // Data Output Collision
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USICNT = 0; // USI Counter Value Bits
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// USICR
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USISIE = 7; // Start Condition Interrupt Enable
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USIOIE = 6; // Counter Overflow Interrupt Enable
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USIWM = 4; // USI Wire Mode Bits
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USICS = 2; // USI Clock Source Select Bits
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USICLK = 1; // Clock Strobe
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USITC = 0; // Toggle Clock Port Pin
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// EECR
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EERIE = 3; // EEProm Ready Interrupt Enable
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EEMWE = 2; // EEPROM Master Write Enable
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EEWE = 1; // EEPROM Write Enable
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EERE = 0; // EEPROM Read Enable
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// WDTCR
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WDCE = 4; // Watchdog Change Enable
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WDE = 3; // Watch Dog Enable
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WDP = 0; // Watch Dog Timer Prescaler bits
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// SREG
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I = 7; // Global Interrupt Enable
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T = 6; // Bit Copy Storage
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H = 5; // Half Carry Flag
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S = 4; // Sign Bit
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V = 3; // Two's Complement Overflow Flag
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N = 2; // Negative Flag
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Z = 1; // Zero Flag
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C = 0; // Carry Flag
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// MCUCR
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PUD = 6; // Pull-up Disable
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SE = 5; // Sleep Enable
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SM = 3; // Sleep Mode Select Bits
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ISC0 = 0; // Interrupt Sense Control 0 bits
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// MCUSR
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WDRF = 3; // Watchdog Reset Flag
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BORF = 2; // Brown-out Reset Flag
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EXTRF = 1; // External Reset Flag
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PORF = 0; // Power-On Reset Flag
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// TIMSK
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TOIE0 = 1; // Timer/Counter0 Overflow Interrupt Enable
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// TIFR
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TOV0 = 1; // Timer/Counter0 Overflow Flag
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// TCCR0
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PSR0 = 3; // Prescaler Reset Timer/Counter0
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CS0 = 0; // Clock Select0 bits
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// TCCR1A
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COM1A = 6; // Comparator A Output Mode Bits
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COM1B = 4; // Comparator B Output Mode Bits
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FOC1A = 3; // Force Output Compare Match 1A
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FOC1B = 2; // Force Output Compare Match 1B
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PWM1A = 1; // Pulse Width Modulator A Enable
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PWM1B = 0; // Pulse Width Modulator B Enable
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// TCCR1B
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CTC1 = 7; // Clear Timer/Counter on Compare Match
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PSR1 = 6; // Prescaler Reset Timer/Counter1
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CS1 = 0; // Clock Select Bits
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// TIMSK
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OCIE1A = 6; // Timer/Counter1 Output Compare Interrupt Enable
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OCIE1B = 5; // Timer/Counter1 Output Compare Interrupt Enable
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TOIE1 = 2; // Timer/Counter1 Overflow Interrupt Enable
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// TIFR
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OCF1A = 6; // Timer/Counter1 Output Compare Flag 1A
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OCF1B = 5; // Timer/Counter1 Output Compare Flag 1B
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TOV1 = 2; // Timer/Counter1 Overflow Flag
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// PLLCSR
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PCKE = 2; // PCK Enable
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PLLE = 1; // PLL Enable
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PLOCK = 0; // PLL Lock Detector
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// GIMSK
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INT0 = 6; // External Interrupt Request 0 Enable
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PCIE = 4; // Pin Change Interrupt Enables
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// GIFR
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INTF0 = 6; // External Interrupt Flag 0
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PCIF = 5; // Pin Change Interrupt Flag
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implementation
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{$define RELBRANCHES}
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{$i avrcommon.inc}
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procedure INT0_ISR; external name 'INT0_ISR'; // Interrupt 1 External Interrupt 0
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procedure IO_PINS_ISR; external name 'IO_PINS_ISR'; // Interrupt 2 External Interrupt Request 0
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procedure TIMER1_CMPA_ISR; external name 'TIMER1_CMPA_ISR'; // Interrupt 3 Timer/Counter1 Compare Match 1A
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procedure TIMER1_CMPB_ISR; external name 'TIMER1_CMPB_ISR'; // Interrupt 4 Timer/Counter1 Compare Match 1B
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procedure TIMER1_OVF1_ISR; external name 'TIMER1_OVF1_ISR'; // Interrupt 5 Timer/Counter1 Overflow
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procedure TIMER0_OVF0_ISR; external name 'TIMER0_OVF0_ISR'; // Interrupt 6 Timer/Counter0 Overflow
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procedure USI_STRT_ISR; external name 'USI_STRT_ISR'; // Interrupt 7 USI Start
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procedure USI_OVF_ISR; external name 'USI_OVF_ISR'; // Interrupt 8 USI Overflow
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procedure EE_RDY_ISR; external name 'EE_RDY_ISR'; // Interrupt 9 EEPROM Ready
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procedure ANA_COMP_ISR; external name 'ANA_COMP_ISR'; // Interrupt 10 Analog Comparator
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procedure ADC_ISR; external name 'ADC_ISR'; // Interrupt 11 ADC Conversion Complete
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procedure _FPC_start; assembler; nostackframe;
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label
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_start;
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asm
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.init
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.globl _start
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rjmp _start
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rjmp INT0_ISR
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rjmp IO_PINS_ISR
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rjmp TIMER1_CMPA_ISR
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rjmp TIMER1_CMPB_ISR
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rjmp TIMER1_OVF1_ISR
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rjmp TIMER0_OVF0_ISR
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rjmp USI_STRT_ISR
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rjmp USI_OVF_ISR
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rjmp EE_RDY_ISR
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rjmp ANA_COMP_ISR
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rjmp ADC_ISR
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{$i start.inc}
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.weak INT0_ISR
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.weak IO_PINS_ISR
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.weak TIMER1_CMPA_ISR
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.weak TIMER1_CMPB_ISR
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.weak TIMER1_OVF1_ISR
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.weak TIMER0_OVF0_ISR
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.weak USI_STRT_ISR
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.weak USI_OVF_ISR
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.weak EE_RDY_ISR
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.weak ANA_COMP_ISR
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.weak ADC_ISR
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.set INT0_ISR, Default_IRQ_handler
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.set IO_PINS_ISR, Default_IRQ_handler
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.set TIMER1_CMPA_ISR, Default_IRQ_handler
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.set TIMER1_CMPB_ISR, Default_IRQ_handler
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.set TIMER1_OVF1_ISR, Default_IRQ_handler
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.set TIMER0_OVF0_ISR, Default_IRQ_handler
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.set USI_STRT_ISR, Default_IRQ_handler
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.set USI_OVF_ISR, Default_IRQ_handler
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.set EE_RDY_ISR, Default_IRQ_handler
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.set ANA_COMP_ISR, Default_IRQ_handler
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.set ADC_ISR, Default_IRQ_handler
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end;
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end.
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