mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-06-03 05:58:24 +02:00
d1538ab023
+ RTL support:
o VFP exceptions are disabled by default on Darwin,
because they cause kernel panics on iPhoneOS 2.2.1 at least
o all denormals are truncated to 0 on Darwin, because disabling
that also causes kernel panics on iPhoneOS 2.2.1 (probably
because otherwise denormals can also cause exceptions)
* set softfloat rounding mode correctly for non-wince/darwin/vfp
targets
+ compiler support: only half the number of single precision
registers is available due to limitations of the register
allocator
+ added a number of comments about why the stackframe on ARM is
set up the way it is by the compiler
+ added regtype and subregtype info to regsets, because they're
also used for VFP registers (+ support in assembler reader)
+ various generic support routines for dealing with floating point
values located in integer registers that have to be transferred to
mm registers (needed for VFP)
* renamed use_sse() to use_vectorfpu() and also use it for
ARM/vfp support
o only superficially tested for Linux (compiler compiled with -Cpvfpv6
-Cfvfpv2 works on a Cortex-A8, no testsuite run performed -- at least
the fpu exception handler still needs to be implemented), Darwin has
been tested more thoroughly
+ added ARMv6 cpu type and made it default for Darwin/ARM
+ ARMv6+ implementations of atomic operations using ldrex/strex
* don't use r9 on Darwin/ARM, as it's reserved under certain
circumstances (don't know yet which ones)
* changed C-test object files for ARM/Darwin to ARMv6 versions
* check in assembler reader that regsets are not empty, because
instructions with a regset operand have undefined behaviour in that
case
* fixed resultdef of tarmtypeconvnode.first_int_to_real in case of
int64->single type conversion
* fixed constant pool locations in case 64 bit constants are generated,
and/or when vfp instructions with limited reach are present
WARNING: when using VFP on an ARMv6 or later cpu, you *must* compile all
code with -Cparmv6 (or higher), or you will get crashes. The reason is
that storing/restoring multiple VFP registers must happen using
different instructions on pre/post-ARMv6.
git-svn-id: trunk@14317 -
109 lines
2.5 KiB
Plaintext
109 lines
2.5 KiB
Plaintext
;
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; ARM registers
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;
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; layout
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; <name>,<type>,<subtype>,<value>,<stdname>,<stab idx>,<dwarf idx>
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;
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NO,$00,$00,$00,INVALID,-1,-1
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; Integer registers
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R0,$01,$00,$00,r0,0,0
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R1,$01,$00,$01,r1,1,1
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R2,$01,$00,$02,r2,2,2
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R3,$01,$00,$03,r3,3,3
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R4,$01,$00,$04,r4,4,4
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R5,$01,$00,$05,r5,5,5
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R6,$01,$00,$06,r6,6,6
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R7,$01,$00,$07,r7,7,7
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R8,$01,$00,$08,r8,8,8
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R9,$01,$00,$09,r9,9,9
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R10,$01,$00,$0a,r10,10,10
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R11,$01,$00,$0b,r11,11,11
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R12,$01,$00,$0c,r12,12,12
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R13,$01,$00,$0d,r13,13,13
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R14,$01,$00,$0e,r14,14,14
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R15,$01,$00,$0f,r15,15,15
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; Float registers
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F0,$02,$00,$00,f0,32,16
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F1,$02,$00,$01,f1,32,17
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F2,$02,$00,$02,f2,32,18
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F3,$02,$00,$03,f3,32,19
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F4,$02,$00,$04,f4,32,20
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F5,$02,$00,$05,f5,32,21
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F6,$02,$00,$06,f6,32,22
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F7,$02,$00,$07,f7,32,23
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; MM registers
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; S0/S1/D0 etc have the same register number because the register allocated
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; cannot deal with D0 conflicting with both S0 and S1. This unfortunately
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; means that we can only use 16 single precision registers instead of 32,
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; even if no double precision ones are used...
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S0,$04,$06,$00,s0,0,0
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S1,$04,$06,$00,s1,0,0
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D0,$04,$07,$00,d0,0,0
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S2,$04,$06,$01,s2,0,0
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S3,$04,$06,$01,s3,0,0
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D1,$04,$07,$01,d1,0,0
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S4,$04,$06,$02,s4,0,0
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S5,$04,$06,$02,s5,0,0
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D2,$04,$07,$02,d2,0,0
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S6,$04,$06,$03,s6,0,0
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S7,$04,$06,$03,s7,0,0
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D3,$04,$07,$03,d3,0,0
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S8,$04,$06,$04,s8,0,0
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S9,$04,$06,$04,s9,0,0
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D4,$04,$07,$04,d4,0,0
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S10,$04,$06,$05,s10,0,0
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S11,$04,$06,$05,s11,0,0
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D5,$04,$07,$05,d5,0,0
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S12,$04,$06,$06,s12,0,0
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S13,$04,$06,$06,s13,0,0
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D6,$04,$07,$06,d6,0,0
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S14,$04,$06,$07,s14,0,0
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S15,$04,$06,$07,s15,0,0
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D7,$04,$07,$07,d7,0,0
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S16,$04,$06,$08,s16,0,0
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S17,$04,$06,$08,s17,0,0
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D8,$04,$07,$08,d8,0,0
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S18,$04,$06,$09,s18,0,0
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S19,$04,$06,$09,s19,0,0
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D9,$04,$07,$09,d9,0,0
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S20,$04,$06,$0A,s20,0,0
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S21,$04,$06,$0A,s21,0,0
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D10,$04,$07,$0A,d10,0,0
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S22,$04,$06,$0B,s22,0,0
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S23,$04,$06,$0B,s23,0,0
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D11,$04,$07,$0B,d11,0,0
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S24,$04,$06,$0C,s24,0,0
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S25,$04,$06,$0C,s25,0,0
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D12,$04,$07,$0C,d12,0,0
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S26,$04,$06,$0D,s26,0,0
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S27,$04,$06,$0D,s27,0,0
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D13,$04,$07,$0D,d13,0,0
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S28,$04,$06,$0E,s28,0,0
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S29,$04,$06,$0E,s29,0,0
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D14,$04,$07,$0E,d14,0,0
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S30,$04,$06,$0F,s20,0,0
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S31,$04,$06,$0F,s21,0,0
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D15,$04,$07,$0F,d15,0,0
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D16,$04,$07,$10,d16,0,0
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D17,$04,$07,$11,d17,0,0
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D18,$04,$07,$12,d18,0,0
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D19,$04,$07,$13,d19,0,0
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D20,$04,$07,$14,d20,0,0
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D21,$04,$07,$15,d21,0,0
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D22,$04,$07,$16,d22,0,0
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D23,$04,$07,$17,d23,0,0
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D24,$04,$07,$18,d24,0,0
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D25,$04,$07,$19,d25,0,0
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D26,$04,$07,$1A,d26,0,0
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D27,$04,$07,$1B,d27,0,0
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D28,$04,$07,$1C,d28,0,0
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D29,$04,$07,$1D,d29,0,0
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D30,$04,$07,$1E,d30,0,0
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D31,$04,$07,$1F,d31,0,0
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; special registers
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CPSR_C,$05,$00,$00,cpsr_c,0,0
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FPSCR,$05,$00,$01,fpscr,0,0
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