Jonas Maebe 79a06b1514 + iphonesim/x86_64 target (64 bit iOS simulator) ... git-svn-id: trunk@29970 -		2015-02-23 22:56:09 +00:00
..
aasmcpu.pas	* fixed i8086 compilation	2015-02-23 08:51:59 +00:00
agx86att.pas	+ iphonesim/x86_64 target (64 bit iOS simulator)	2015-02-23 22:56:09 +00:00
agx86int.pas	* fix assembling with masm according to #25858	2015-02-05 21:22:39 +00:00
agx86nsm.pas	+ support section smartlinking with nasm	2015-02-08 12:33:50 +00:00
cga.pas
cgx86.pas	+ iphonesim/x86_64 target (64 bit iOS simulator)	2015-02-23 22:56:09 +00:00
cpubase.pas
hlcgx86.pas
itcpugas.pas
itx86int.pas
ni86mem.pas
nx86add.pas
nx86cal.pas
nx86cnv.pas
nx86con.pas
nx86inl.pas	+ cpu capability CPUX86_HAS_CMOV	2015-02-21 20:47:40 +00:00
nx86mat.pas	* make integer division instruction (div/idiv) on x86 dependent on the	2015-01-04 13:08:57 +00:00
nx86mem.pas	* generic part of r26050 from the hlcgllvm branch: made tcgvecnode hlcg-safe	2015-02-23 22:56:00 +00:00
nx86set.pas
rax86.pas	- x86 assembler readers: cleaned out operand swapping code. Operands of TInstruction are kept in AT&T order, Intel reader attaches operands right-to-left. It was effectively the same way before the change (except Intel reader attaching operands left-to-right, followed by a single swap), operand order checks all over the place were just reducing readability.	2014-11-16 16:37:26 +00:00
rax86att.pas	- x86 assembler readers: cleaned out operand swapping code. Operands of TInstruction are kept in AT&T order, Intel reader attaches operands right-to-left. It was effectively the same way before the change (except Intel reader attaching operands left-to-right, followed by a single swap), operand order checks all over the place were just reducing readability.	2014-11-16 16:37:26 +00:00
rax86int.pas	+ applied remaining patches of Torsten Grundke: adds gather instructions of avx2	2015-02-17 21:43:46 +00:00
rgx86.pas
symi86.pas
symx86.pas
x86ins.dat	+ applied remaining patches of Torsten Grundke: adds gather instructions of avx2	2015-02-17 21:43:46 +00:00
x86reg.dat