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https://gitlab.com/freepascal.org/fpc/source.git
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714 lines
31 KiB
ObjectPascal
714 lines
31 KiB
ObjectPascal
{
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Copyright (c) 1998-2002 by Florian Klaempfl
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Generate x86 code for math nodes
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit nx86mat;
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{$i fpcdefs.inc}
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interface
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uses
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node,ncgmat;
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type
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tx86unaryminusnode = class(tcgunaryminusnode)
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{$ifdef SUPPORT_MMX}
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procedure second_mmx;override;
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{$endif SUPPORT_MMX}
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procedure second_float;override;
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function pass_1:tnode;override;
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end;
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tx86notnode = class(tcgnotnode)
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procedure second_boolean;override;
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{$ifdef SUPPORT_MMX}
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procedure second_mmx;override;
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{$endif SUPPORT_MMX}
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end;
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tx86moddivnode = class(tcgmoddivnode)
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procedure pass_generate_code;override;
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end;
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implementation
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uses
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globtype,
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constexp,
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cutils,verbose,globals,
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symconst,symdef,
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aasmbase,aasmtai,aasmcpu,aasmdata,defutil,
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cgbase,pass_1,pass_2,
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ncon,
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cpubase,cpuinfo,
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cga,cgobj,hlcgobj,cgx86,cgutils;
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{*****************************************************************************
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TI386UNARYMINUSNODE
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*****************************************************************************}
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function tx86unaryminusnode.pass_1 : tnode;
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begin
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result:=nil;
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firstpass(left);
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if codegenerror then
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exit;
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if (left.resultdef.typ=floatdef) then
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begin
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if use_vectorfpu(left.resultdef) then
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expectloc:=LOC_MMREGISTER
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else
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expectloc:=LOC_FPUREGISTER;
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end
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{$ifdef SUPPORT_MMX}
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else
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if (cs_mmx in current_settings.localswitches) and
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is_mmx_able_array(left.resultdef) then
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begin
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expectloc:=LOC_MMXREGISTER;
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end
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{$endif SUPPORT_MMX}
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else
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inherited pass_1;
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end;
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{$ifdef SUPPORT_MMX}
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procedure tx86unaryminusnode.second_mmx;
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var
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op : tasmop;
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hreg : tregister;
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begin
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op:=A_NONE;
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secondpass(left);
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location_reset(location,LOC_MMXREGISTER,OS_NO);
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hreg:=tcgx86(cg).getmmxregister(current_asmdata.CurrAsmList);
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emit_reg_reg(A_PXOR,S_NO,hreg,hreg);
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case left.location.loc of
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LOC_MMXREGISTER:
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begin
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location.register:=left.location.register;
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end;
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LOC_CMMXREGISTER:
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begin
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location.register:=tcgx86(cg).getmmxregister(current_asmdata.CurrAsmList);
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emit_reg_reg(A_MOVQ,S_NO,left.location.register,location.register);
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end;
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LOC_REFERENCE,
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LOC_CREFERENCE:
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begin
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location.register:=tcgx86(cg).getmmxregister(current_asmdata.CurrAsmList);
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emit_ref_reg(A_MOVQ,S_NO,left.location.reference,location.register);
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end;
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else
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internalerror(200203225);
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end;
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if cs_mmx_saturation in current_settings.localswitches then
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case mmx_type(resultdef) of
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mmxs8bit:
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op:=A_PSUBSB;
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mmxu8bit:
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op:=A_PSUBUSB;
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mmxs16bit,mmxfixed16:
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op:=A_PSUBSW;
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mmxu16bit:
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op:=A_PSUBUSW;
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end
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else
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case mmx_type(resultdef) of
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mmxs8bit,mmxu8bit:
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op:=A_PSUBB;
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mmxs16bit,mmxu16bit,mmxfixed16:
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op:=A_PSUBW;
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mmxs32bit,mmxu32bit:
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op:=A_PSUBD;
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end;
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if op = A_NONE then
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internalerror(201408202);
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emit_reg_reg(op,S_NO,location.register,hreg);
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emit_reg_reg(A_MOVQ,S_NO,hreg,location.register);
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end;
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{$endif SUPPORT_MMX}
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procedure tx86unaryminusnode.second_float;
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var
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reg : tregister;
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href : treference;
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l1 : tasmlabel;
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begin
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secondpass(left);
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if expectloc=LOC_MMREGISTER then
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begin
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hlcg.location_force_mmregscalar(current_asmdata.CurrAsmList,left.location,left.resultdef,true);
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location_reset(location,LOC_MMREGISTER,def_cgsize(resultdef));
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{ make life of register allocator easier }
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location.register:=cg.getmmregister(current_asmdata.CurrAsmList,def_cgsize(resultdef));
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current_asmdata.getglobaldatalabel(l1);
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new_section(current_asmdata.asmlists[al_typedconsts],sec_rodata_norel,l1.name,const_align(sizeof(pint)));
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current_asmdata.asmlists[al_typedconsts].concat(Tai_label.Create(l1));
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case def_cgsize(resultdef) of
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OS_F32:
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current_asmdata.asmlists[al_typedconsts].concat(tai_const.create_32bit(longint(1 shl 31)));
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OS_F64:
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begin
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current_asmdata.asmlists[al_typedconsts].concat(tai_const.create_32bit(0));
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current_asmdata.asmlists[al_typedconsts].concat(tai_const.create_32bit(-(1 shl 31)));
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end
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else
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internalerror(2004110215);
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end;
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reference_reset_symbol(href,l1,0,resultdef.alignment,[]);
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if UseAVX then
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cg.a_opmm_ref_reg_reg(current_asmdata.CurrAsmList,OP_XOR,left.location.size,href,left.location.register,location.register,nil)
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else
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begin
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reg:=cg.getmmregister(current_asmdata.CurrAsmList,def_cgsize(resultdef));
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cg.a_loadmm_ref_reg(current_asmdata.CurrAsmList,def_cgsize(resultdef),def_cgsize(resultdef),href,reg,mms_movescalar);
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cg.a_loadmm_reg_reg(current_asmdata.CurrAsmList,def_cgsize(resultdef),def_cgsize(resultdef),left.location.register,location.register,mms_movescalar);
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cg.a_opmm_reg_reg(current_asmdata.CurrAsmList,OP_XOR,left.location.size,reg,location.register,nil);
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end;
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end
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else
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begin
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location_reset(location,LOC_FPUREGISTER,def_cgsize(resultdef));
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case left.location.loc of
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LOC_REFERENCE,
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LOC_CREFERENCE:
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begin
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location.register:=NR_ST;
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cg.a_loadfpu_ref_reg(current_asmdata.CurrAsmList,
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left.location.size,location.size,
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left.location.reference,location.register);
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emit_none(A_FCHS,S_NO);
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end;
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LOC_FPUREGISTER,
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LOC_CFPUREGISTER:
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begin
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{ "load st,st" is ignored by the code generator }
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cg.a_loadfpu_reg_reg(current_asmdata.CurrAsmList,left.location.size,location.size,left.location.register,NR_ST);
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location.register:=NR_ST;
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emit_none(A_FCHS,S_NO);
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end;
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else
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internalerror(200312241);
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end;
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end;
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end;
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{*****************************************************************************
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TX86NOTNODE
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*****************************************************************************}
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procedure tx86notnode.second_boolean;
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var
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opsize : tcgsize;
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{$if defined(cpu32bitalu) or defined(cpu16bitalu)}
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hreg: tregister;
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{$endif}
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begin
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opsize:=def_cgsize(resultdef);
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if not handle_locjump then
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begin
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{ the second pass could change the location of left }
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{ if it is a register variable, so we've to do }
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{ this before the case statement }
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secondpass(left);
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case left.location.loc of
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LOC_FLAGS :
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begin
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location_reset(location,LOC_FLAGS,OS_NO);
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location.resflags:=left.location.resflags;
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inverse_flags(location.resflags);
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end;
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LOC_CREFERENCE,
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LOC_REFERENCE:
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begin
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{$if defined(cpu32bitalu)}
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if is_64bit(resultdef) then
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begin
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hreg:=cg.GetIntRegister(current_asmdata.CurrAsmList,OS_32);
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tcgx86(cg).make_simple_ref(current_asmdata.CurrAsmList,left.location.reference);
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cg.a_load_ref_reg(current_asmdata.CurrAsmList,OS_32,OS_32,left.location.reference,hreg);
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inc(left.location.reference.offset,4);
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cg.a_op_ref_reg(current_asmdata.CurrAsmList,OP_OR,OS_32,left.location.reference,hreg);
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end
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else
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{$elseif defined(cpu16bitalu)}
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if is_64bit(resultdef) then
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begin
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hreg:=cg.GetIntRegister(current_asmdata.CurrAsmList,OS_16);
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tcgx86(cg).make_simple_ref(current_asmdata.CurrAsmList,left.location.reference);
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cg.a_load_ref_reg(current_asmdata.CurrAsmList,OS_16,OS_16,left.location.reference,hreg);
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inc(left.location.reference.offset,2);
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cg.a_op_ref_reg(current_asmdata.CurrAsmList,OP_OR,OS_16,left.location.reference,hreg);
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inc(left.location.reference.offset,2);
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cg.a_op_ref_reg(current_asmdata.CurrAsmList,OP_OR,OS_16,left.location.reference,hreg);
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inc(left.location.reference.offset,2);
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cg.a_op_ref_reg(current_asmdata.CurrAsmList,OP_OR,OS_16,left.location.reference,hreg);
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end
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else if is_32bit(resultdef) then
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begin
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hreg:=cg.GetIntRegister(current_asmdata.CurrAsmList,OS_16);
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tcgx86(cg).make_simple_ref(current_asmdata.CurrAsmList,left.location.reference);
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cg.a_load_ref_reg(current_asmdata.CurrAsmList,OS_16,OS_16,left.location.reference,hreg);
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inc(left.location.reference.offset,2);
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cg.a_op_ref_reg(current_asmdata.CurrAsmList,OP_OR,OS_16,left.location.reference,hreg);
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end
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else
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{$endif}
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emit_const_ref(A_CMP, TCGSize2Opsize[opsize], 0, left.location.reference);
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location_reset(location,LOC_FLAGS,OS_NO);
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location.resflags:=F_E;
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end;
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LOC_CONSTANT,
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LOC_REGISTER,
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LOC_CREGISTER,
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LOC_SUBSETREG,
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LOC_CSUBSETREG,
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LOC_SUBSETREF,
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LOC_CSUBSETREF :
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begin
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{$if defined(cpu32bitalu)}
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if is_64bit(resultdef) then
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begin
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,resultdef,false);
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emit_reg_reg(A_OR,S_L,left.location.register64.reghi,left.location.register64.reglo);
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end
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else
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{$elseif defined(cpu16bitalu)}
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if is_64bit(resultdef) then
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begin
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,resultdef,false);
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emit_reg_reg(A_OR,S_W,cg.GetNextReg(left.location.register64.reghi),left.location.register64.reghi);
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emit_reg_reg(A_OR,S_W,cg.GetNextReg(left.location.register64.reglo),left.location.register64.reglo);
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emit_reg_reg(A_OR,S_W,left.location.register64.reghi,left.location.register64.reglo);
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end
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else if is_32bit(resultdef) then
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begin
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,resultdef,false);
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emit_reg_reg(A_OR,S_L,cg.GetNextReg(left.location.register),left.location.register);
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end
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else
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{$endif}
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begin
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,resultdef,true);
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emit_reg_reg(A_TEST,TCGSize2Opsize[opsize],left.location.register,left.location.register);
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end;
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location_reset(location,LOC_FLAGS,OS_NO);
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location.resflags:=F_E;
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end;
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else
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internalerror(200203224);
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end;
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end;
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end;
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{$ifdef SUPPORT_MMX}
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procedure tx86notnode.second_mmx;
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var hreg,r:Tregister;
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begin
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secondpass(left);
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location_reset(location,LOC_MMXREGISTER,OS_NO);
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r:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
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emit_const_reg(A_MOV,S_L,longint($ffffffff),r);
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{ load operand }
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case left.location.loc of
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LOC_MMXREGISTER:
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location_copy(location,left.location);
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LOC_CMMXREGISTER:
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begin
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location.register:=tcgx86(cg).getmmxregister(current_asmdata.CurrAsmList);
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emit_reg_reg(A_MOVQ,S_NO,left.location.register,location.register);
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end;
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LOC_REFERENCE,
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LOC_CREFERENCE:
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begin
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location.register:=tcgx86(cg).getmmxregister(current_asmdata.CurrAsmList);
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emit_ref_reg(A_MOVQ,S_NO,left.location.reference,location.register);
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end;
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end;
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{ load mask }
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hreg:=tcgx86(cg).getmmxregister(current_asmdata.CurrAsmList);
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emit_reg_reg(A_MOVD,S_NO,r,hreg);
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{ lower 32 bit }
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emit_reg_reg(A_PXOR,S_NO,hreg,location.register);
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{ shift mask }
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emit_const_reg(A_PSLLQ,S_B,32,hreg);
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{ higher 32 bit }
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emit_reg_reg(A_PXOR,S_NO,hreg,location.register);
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end;
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{$endif SUPPORT_MMX}
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{*****************************************************************************
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TX86MODDIVNODE
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*****************************************************************************}
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procedure tx86moddivnode.pass_generate_code;
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var
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hreg1,hreg2,hreg3,rega,regd,tempreg:Tregister;
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power:longint;
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instr:TAiCpu;
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op:Tasmop;
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cgsize:TCgSize;
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opsize:topsize;
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e, sm: aint;
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d,m: aword;
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m_add, invertsign: boolean;
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s: byte;
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label
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DefaultDiv;
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begin
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secondpass(left);
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if codegenerror then
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exit;
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secondpass(right);
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if codegenerror then
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exit;
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{ put numerator in register }
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cgsize:=def_cgsize(resultdef);
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opsize:=TCGSize2OpSize[cgsize];
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if not (cgsize in [OS_32,OS_S32,OS_64,OS_S64]) then
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InternalError(2013102702);
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rega:=newreg(R_INTREGISTER,RS_EAX,cgsize2subreg(R_INTREGISTER,cgsize));
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regd:=newreg(R_INTREGISTER,RS_EDX,cgsize2subreg(R_INTREGISTER,cgsize));
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location_reset(location,LOC_REGISTER,cgsize);
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,resultdef,false);
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hreg1:=left.location.register;
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if (nodetype=divn) and (right.nodetype=ordconstn) then
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begin
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if isabspowerof2(tordconstnode(right).value,power) then
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begin
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{ for signed numbers, the numerator must be adjusted before the
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shift instruction, but not with unsigned numbers! Otherwise,
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"Cardinal($ffffffff) div 16" overflows! (JM) }
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if is_signed(left.resultdef) Then
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begin
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invertsign:=tordconstnode(right).value<0;
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{ use a sequence without jumps, saw this in
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comp.compilers (JM) }
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{ no jumps, but more operations }
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hreg2:=cg.getintregister(current_asmdata.CurrAsmList,cgsize);
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emit_reg_reg(A_MOV,opsize,hreg1,hreg2);
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if power=1 then
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begin
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{If the left value is negative, hreg2=(1 shl power)-1=1, otherwise 0.}
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cg.a_op_const_reg(current_asmdata.CurrAsmList,OP_SHR,cgsize,resultdef.size*8-1,hreg2);
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end
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else
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begin
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{If the left value is negative, hreg2=$ffffffff, otherwise 0.}
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cg.a_op_const_reg(current_asmdata.CurrAsmList,OP_SAR,cgsize,resultdef.size*8-1,hreg2);
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{If negative, hreg2=(1 shl power)-1, otherwise 0.}
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{ (don't use emit_const_reg, because if value>high(longint)
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then it must first be loaded into a register) }
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cg.a_op_const_reg(current_asmdata.CurrAsmList,OP_AND,cgsize,(aint(1) shl power)-1,hreg2);
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end;
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{ add to the left value }
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emit_reg_reg(A_ADD,opsize,hreg2,hreg1);
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{ do the shift }
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cg.a_op_const_reg(current_asmdata.CurrAsmList,OP_SAR,cgsize,power,hreg1);
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if invertsign then
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emit_reg(A_NEG,opsize,hreg1);
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end
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else
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cg.a_op_const_reg(current_asmdata.CurrAsmList,OP_SHR,cgsize,power,hreg1);
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location.register:=hreg1;
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end
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else
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begin
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if is_signed(left.resultdef) then
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begin
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e:=tordconstnode(right).value.svalue;
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calc_divconst_magic_signed(resultdef.size*8,e,sm,s);
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cg.getcpuregister(current_asmdata.CurrAsmList,rega);
|
|
emit_const_reg(A_MOV,opsize,sm,rega);
|
|
cg.getcpuregister(current_asmdata.CurrAsmList,regd);
|
|
emit_reg(A_IMUL,opsize,hreg1);
|
|
{ only the high half of result is used }
|
|
cg.ungetcpuregister(current_asmdata.CurrAsmList,rega);
|
|
{ add or subtract dividend }
|
|
if (e>0) and (sm<0) then
|
|
emit_reg_reg(A_ADD,opsize,hreg1,regd)
|
|
else if (e<0) and (sm>0) then
|
|
emit_reg_reg(A_SUB,opsize,hreg1,regd);
|
|
{ shift if necessary }
|
|
if (s<>0) then
|
|
emit_const_reg(A_SAR,opsize,s,regd);
|
|
{ extract and add the sign bit }
|
|
if (e<0) then
|
|
emit_reg_reg(A_MOV,opsize,regd,hreg1);
|
|
{ if e>=0, hreg1 still contains dividend }
|
|
emit_const_reg(A_SHR,opsize,left.resultdef.size*8-1,hreg1);
|
|
emit_reg_reg(A_ADD,opsize,hreg1,regd);
|
|
cg.ungetcpuregister(current_asmdata.CurrAsmList,regd);
|
|
location.register:=cg.getintregister(current_asmdata.CurrAsmList,cgsize);
|
|
cg.a_load_reg_reg(current_asmdata.CurrAsmList,cgsize,cgsize,regd,location.register)
|
|
end
|
|
else
|
|
begin
|
|
d:=tordconstnode(right).value.svalue;
|
|
if d>=aword(1) shl (left.resultdef.size*8-1) then
|
|
begin
|
|
location.register:=cg.getintregister(current_asmdata.CurrAsmList,cgsize);
|
|
{ Ensure that the whole register is 0, since SETcc only sets the lowest byte }
|
|
|
|
if opsize = S_Q then
|
|
begin
|
|
{ Emit an XOR instruction that only operates on the lower 32 bits,
|
|
since we want to initialise this register to zero, the upper 32
|
|
bits will be set to zero regardless, and the resultant machine code
|
|
will usually be smaller due to the lack of a REX prefix. [Kit] }
|
|
tempreg := location.register;
|
|
setsubreg(tempreg, R_SUBD);
|
|
emit_reg_reg(A_XOR, S_L, tempreg, tempreg);
|
|
end
|
|
else
|
|
emit_reg_reg(A_XOR,opsize,location.register,location.register);
|
|
|
|
cg.a_reg_alloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
|
|
if (cgsize in [OS_64,OS_S64]) then { Cannot use 64-bit constants in CMP }
|
|
begin
|
|
hreg2:=cg.getintregister(current_asmdata.CurrAsmList,cgsize);
|
|
emit_const_reg(A_MOV,opsize,aint(d),hreg2);
|
|
emit_reg_reg(A_CMP,opsize,hreg2,hreg1);
|
|
end
|
|
else
|
|
emit_const_reg(A_CMP,opsize,aint(d),hreg1);
|
|
{ NOTE: SBB and SETAE are both 3 bytes long without the REX prefix,
|
|
both use an ALU for their execution and take a single cycle to
|
|
run. The only difference is that SETAE does not modify the flags,
|
|
allowing for some possible reuse. [Kit] }
|
|
{$ifdef x86_64}
|
|
{ Emit a SETcc instruction that depends on the carry bit being zero,
|
|
that is, the numerator is greater than or equal to the denominator. }
|
|
tempreg := location.register;
|
|
setsubreg(tempreg, R_SUBL);
|
|
{ On x86-64, all registers can have their lower 8 bits represented }
|
|
instr:=TAiCpu.op_reg(A_SETcc,S_B,tempreg);
|
|
instr.condition := C_AE;
|
|
current_asmdata.CurrAsmList.concat(instr);
|
|
{$else}
|
|
case getsupreg(location.register) of
|
|
{ On x86, only these four registers can have their lower 8 bits represented }
|
|
RS_EAX, RS_ECX, RS_EDX, RS_EBX:
|
|
begin
|
|
{ Emit a SETcc instruction that depends on the carry bit being zero,
|
|
that is, the numerator is greater than or equal to the denominator. }
|
|
tempreg := location.register;
|
|
setsubreg(tempreg, R_SUBL);
|
|
instr:=TAiCpu.op_reg(A_SETcc,S_B,tempreg);
|
|
instr.condition := C_AE;
|
|
current_asmdata.CurrAsmList.concat(instr);
|
|
end;
|
|
else
|
|
{ It will likely emit SBB anyway because location.register is
|
|
usually imaginary. [Kit] }
|
|
emit_const_reg(A_SBB,opsize,-1,location.register);
|
|
end;
|
|
{$endif}
|
|
cg.a_reg_dealloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
|
|
end
|
|
else
|
|
begin
|
|
calc_divconst_magic_unsigned(resultdef.size*8,d,m,m_add,s);
|
|
cg.getcpuregister(current_asmdata.CurrAsmList,rega);
|
|
emit_const_reg(A_MOV,opsize,aint(m),rega);
|
|
cg.getcpuregister(current_asmdata.CurrAsmList,regd);
|
|
emit_reg(A_MUL,opsize,hreg1);
|
|
cg.ungetcpuregister(current_asmdata.CurrAsmList,rega);
|
|
if m_add then
|
|
begin
|
|
{ addition can overflow, shift first bit considering carry,
|
|
then shift remaining bits in regular way. }
|
|
emit_reg_reg(A_ADD,opsize,hreg1,regd);
|
|
emit_const_reg(A_RCR,opsize,1,regd);
|
|
dec(s);
|
|
end;
|
|
if s<>0 then
|
|
emit_const_reg(A_SHR,opsize,aint(s),regd);
|
|
cg.ungetcpuregister(current_asmdata.CurrAsmList,regd);
|
|
location.register:=cg.getintregister(current_asmdata.CurrAsmList,cgsize);
|
|
cg.a_load_reg_reg(current_asmdata.CurrAsmList,cgsize,cgsize,regd,location.register)
|
|
end;
|
|
end;
|
|
end;
|
|
end
|
|
else if (nodetype=modn) and (right.nodetype=ordconstn) and not(is_signed(left.resultdef)) then
|
|
begin
|
|
{ unsigned modulus by a (+/-)power-of-2 constant? }
|
|
if isabspowerof2(tordconstnode(right).value,power) then
|
|
begin
|
|
emit_const_reg(A_AND,opsize,(aint(1) shl power)-1,hreg1);
|
|
location.register:=hreg1;
|
|
end
|
|
else
|
|
begin
|
|
d:=tordconstnode(right).value.svalue;
|
|
if d>=aword(1) shl (left.resultdef.size*8-1) then
|
|
begin
|
|
|
|
if not (CPUX86_HAS_CMOV in cpu_capabilities[current_settings.cputype]) then
|
|
goto DefaultDiv;
|
|
|
|
location.register:=cg.getintregister(current_asmdata.CurrAsmList,cgsize);
|
|
hreg3:=cg.getintregister(current_asmdata.CurrAsmList,cgsize);
|
|
|
|
m := aword(-aint(d)); { Two's complement of d }
|
|
|
|
if (cgsize in [OS_64,OS_S64]) then { Cannot use 64-bit constants in CMP }
|
|
begin
|
|
hreg2:=cg.getintregister(current_asmdata.CurrAsmList,cgsize);
|
|
emit_const_reg(A_MOV,opsize,aint(d),hreg2);
|
|
emit_const_reg(A_MOV,opsize,aint(m),hreg3);
|
|
emit_reg_reg(A_XOR,opsize,location.register,location.register);
|
|
cg.a_reg_alloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
|
|
emit_reg_reg(A_CMP,opsize,hreg2,hreg1);
|
|
end
|
|
else
|
|
begin
|
|
emit_const_reg(A_MOV,opsize,aint(m),hreg3);
|
|
emit_reg_reg(A_XOR,opsize,location.register,location.register);
|
|
|
|
cg.a_reg_alloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
|
|
emit_const_reg(A_CMP,opsize,aint(d),hreg1);
|
|
end;
|
|
|
|
{ Emit conditional move that depends on the carry flag being zero,
|
|
that is, the comparison result is above or equal }
|
|
instr:=TAiCpu.op_reg_reg(A_CMOVcc,opsize,hreg3,location.register);
|
|
instr.condition := C_AE;
|
|
current_asmdata.CurrAsmList.concat(instr);
|
|
cg.a_reg_dealloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
|
|
|
|
emit_reg_reg(A_ADD,opsize,hreg1,location.register);
|
|
end
|
|
else
|
|
begin
|
|
{ Convert the division to a multiplication }
|
|
calc_divconst_magic_unsigned(resultdef.size*8,d,m,m_add,s);
|
|
cg.getcpuregister(current_asmdata.CurrAsmList,rega);
|
|
emit_const_reg(A_MOV,opsize,aint(m),rega);
|
|
cg.getcpuregister(current_asmdata.CurrAsmList,regd);
|
|
emit_reg(A_MUL,opsize,hreg1);
|
|
cg.ungetcpuregister(current_asmdata.CurrAsmList,rega);
|
|
hreg2:=cg.getintregister(current_asmdata.CurrAsmList,cgsize);
|
|
emit_reg_reg(A_MOV,opsize,hreg1,hreg2);
|
|
if m_add then
|
|
begin
|
|
{ addition can overflow, shift first bit considering carry,
|
|
then shift remaining bits in regular way. }
|
|
cg.a_reg_alloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
|
|
emit_reg_reg(A_ADD,opsize,hreg1,regd);
|
|
emit_const_reg(A_RCR,opsize,1,regd);
|
|
cg.a_reg_dealloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
|
|
dec(s);
|
|
end;
|
|
if s<>0 then
|
|
emit_const_reg(A_SHR,opsize,aint(s),regd); { R/EDX now contains the quotient }
|
|
|
|
{ Now multiply the quotient by the original denominator and
|
|
subtract the product from the original numerator to get
|
|
the remainder. }
|
|
if (cgsize in [OS_64,OS_S64]) then { Cannot use 64-bit constants in IMUL }
|
|
begin
|
|
hreg3:=cg.getintregister(current_asmdata.CurrAsmList,cgsize);
|
|
emit_const_reg(A_MOV,opsize,aint(d),hreg3);
|
|
emit_reg_reg(A_IMUL,opsize,hreg3,regd);
|
|
end
|
|
else
|
|
emit_const_reg(A_IMUL,opsize,aint(d),regd);
|
|
|
|
emit_reg_reg(A_SUB,opsize,regd,hreg2);
|
|
cg.ungetcpuregister(current_asmdata.CurrAsmList,regd);
|
|
location.register:=hreg2;
|
|
end;
|
|
end;
|
|
end
|
|
else
|
|
begin
|
|
DefaultDiv:
|
|
{Bring denominator to a register.}
|
|
cg.getcpuregister(current_asmdata.CurrAsmList,rega);
|
|
emit_reg_reg(A_MOV,opsize,hreg1,rega);
|
|
cg.getcpuregister(current_asmdata.CurrAsmList,regd);
|
|
{Sign extension depends on the left type.}
|
|
if is_signed(left.resultdef) then
|
|
case left.resultdef.size of
|
|
{$ifdef x86_64}
|
|
8:
|
|
emit_none(A_CQO,S_NO);
|
|
{$endif x86_64}
|
|
4:
|
|
emit_none(A_CDQ,S_NO);
|
|
else
|
|
internalerror(2013102701);
|
|
end
|
|
else
|
|
emit_reg_reg(A_XOR,opsize,regd,regd);
|
|
|
|
{ Division depends on the result type }
|
|
if is_signed(resultdef) then
|
|
op:=A_IDIV
|
|
else
|
|
op:=A_DIV;
|
|
|
|
if right.location.loc in [LOC_REFERENCE,LOC_CREFERENCE] then
|
|
emit_ref(op,opsize,right.location.reference)
|
|
else if right.location.loc in [LOC_REGISTER,LOC_CREGISTER] then
|
|
emit_reg(op,opsize,right.location.register)
|
|
else
|
|
begin
|
|
hreg1:=cg.getintregister(current_asmdata.CurrAsmList,right.location.size);
|
|
hlcg.a_load_loc_reg(current_asmdata.CurrAsmList,right.resultdef,right.resultdef,right.location,hreg1);
|
|
emit_reg(op,opsize,hreg1);
|
|
end;
|
|
|
|
{ Copy the result into a new register. Release R/EAX & R/EDX.}
|
|
cg.ungetcpuregister(current_asmdata.CurrAsmList,regd);
|
|
cg.ungetcpuregister(current_asmdata.CurrAsmList,rega);
|
|
location.register:=cg.getintregister(current_asmdata.CurrAsmList,cgsize);
|
|
if nodetype=divn then
|
|
cg.a_load_reg_reg(current_asmdata.CurrAsmList,cgsize,cgsize,rega,location.register)
|
|
else
|
|
cg.a_load_reg_reg(current_asmdata.CurrAsmList,cgsize,cgsize,regd,location.register);
|
|
end;
|
|
end;
|
|
|
|
end.
|