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a3ab2053c9
getjumplabel and added type para to getlabel for specific types * moved lineinfo generation from assemble and aggas to dbgstabs git-svn-id: trunk@1120 -
792 lines
28 KiB
ObjectPascal
792 lines
28 KiB
ObjectPascal
{
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Copyright (c) 1998-2002 by Florian Klaempfl
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Member of the Free Pascal development team
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This unit implements the code generation for 64 bit int
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arithmethics on 32 bit processors
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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{# This unit implements the code generation for 64 bit int arithmethics on
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32 bit processors.
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}
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unit cg64f32;
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{$i fpcdefs.inc}
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interface
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uses
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aasmbase,aasmtai,aasmcpu,
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cpubase,cpupara,
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cgbase,cgobj,parabase,cgutils,
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symtype
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;
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type
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{# Defines all the methods required on 32-bit processors
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to handle 64-bit integers.
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}
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tcg64f32 = class(tcg64)
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procedure a_load64_const_ref(list : taasmoutput;value : int64;const ref : treference);override;
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procedure a_load64_reg_ref(list : taasmoutput;reg : tregister64;const ref : treference);override;
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procedure a_load64_ref_reg(list : taasmoutput;const ref : treference;reg : tregister64);override;
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procedure a_load64_reg_reg(list : taasmoutput;regsrc,regdst : tregister64);override;
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procedure a_load64_const_reg(list : taasmoutput;value: int64;reg : tregister64);override;
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procedure a_load64_loc_reg(list : taasmoutput;const l : tlocation;reg : tregister64);override;
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procedure a_load64_loc_ref(list : taasmoutput;const l : tlocation;const ref : treference);override;
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procedure a_load64_const_loc(list : taasmoutput;value : int64;const l : tlocation);override;
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procedure a_load64_reg_loc(list : taasmoutput;reg : tregister64;const l : tlocation);override;
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procedure a_load64high_reg_ref(list : taasmoutput;reg : tregister;const ref : treference);override;
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procedure a_load64low_reg_ref(list : taasmoutput;reg : tregister;const ref : treference);override;
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procedure a_load64high_ref_reg(list : taasmoutput;const ref : treference;reg : tregister);override;
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procedure a_load64low_ref_reg(list : taasmoutput;const ref : treference;reg : tregister);override;
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procedure a_load64high_loc_reg(list : taasmoutput;const l : tlocation;reg : tregister);override;
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procedure a_load64low_loc_reg(list : taasmoutput;const l : tlocation;reg : tregister);override;
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procedure a_op64_ref_reg(list : taasmoutput;op:TOpCG;size : tcgsize;const ref : treference;reg : tregister64);override;
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procedure a_op64_reg_ref(list : taasmoutput;op:TOpCG;size : tcgsize;reg : tregister64; const ref: treference);override;
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procedure a_op64_const_loc(list : taasmoutput;op:TOpCG;size : tcgsize;value : int64;const l: tlocation);override;
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procedure a_op64_reg_loc(list : taasmoutput;op:TOpCG;size : tcgsize;reg : tregister64;const l : tlocation);override;
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procedure a_op64_loc_reg(list : taasmoutput;op:TOpCG;size : tcgsize;const l : tlocation;reg : tregister64);override;
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procedure a_op64_const_ref(list : taasmoutput;op:TOpCG;size : tcgsize;value : int64;const ref : treference);override;
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procedure a_param64_reg(list : taasmoutput;reg : tregister64;const paraloc : tcgpara);override;
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procedure a_param64_const(list : taasmoutput;value : int64;const paraloc : tcgpara);override;
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procedure a_param64_ref(list : taasmoutput;const r : treference;const paraloc : tcgpara);override;
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procedure a_param64_loc(list : taasmoutput;const l : tlocation;const paraloc : tcgpara);override;
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{# This routine tries to optimize the a_op64_const_reg operation, by
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removing superfluous opcodes. Returns TRUE if normal processing
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must continue in op64_const_reg, otherwise, everything is processed
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entirely in this routine, by emitting the appropriate 32-bit opcodes.
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}
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function optimize64_op_const_reg(list: taasmoutput; var op: topcg; var a : int64; var reg: tregister64): boolean;override;
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procedure g_rangecheck64(list: taasmoutput; const l:tlocation;fromdef,todef: tdef); override;
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end;
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{# Creates a tregister64 record from 2 32 Bit registers. }
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function joinreg64(reglo,reghi : tregister) : tregister64;
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implementation
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uses
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globtype,systems,
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verbose,
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symbase,symconst,symdef,defutil,paramgr;
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{****************************************************************************
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Helpers
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****************************************************************************}
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function joinreg64(reglo,reghi : tregister) : tregister64;
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begin
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result.reglo:=reglo;
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result.reghi:=reghi;
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end;
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procedure swap64(var q : int64);
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begin
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q:=(int64(lo(q)) shl 32) or hi(q);
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end;
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procedure splitparaloc64(const cgpara:tcgpara;var cgparalo,cgparahi:tcgpara);
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var
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paraloclo,
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paralochi : pcgparalocation;
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begin
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if not(cgpara.size in [OS_64,OS_S64]) then
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internalerror(200408231);
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if not assigned(cgpara.location) then
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internalerror(200408201);
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{ init lo/hi para }
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cgparahi.reset;
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if cgpara.size=OS_S64 then
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cgparahi.size:=OS_S32
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else
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cgparahi.size:=OS_32;
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cgparahi.intsize:=4;
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cgparahi.alignment:=cgpara.alignment;
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paralochi:=cgparahi.add_location;
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cgparalo.reset;
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cgparalo.size:=OS_32;
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cgparalo.intsize:=4;
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cgparalo.alignment:=cgpara.alignment;
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paraloclo:=cgparalo.add_location;
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{ 2 parameter fields? }
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if assigned(cgpara.location^.next) then
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begin
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{ Order for multiple locations is always
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paraloc^ -> high
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paraloc^.next -> low }
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if (target_info.endian=ENDIAN_BIG) then
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begin
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{ paraloc^ -> high
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paraloc^.next -> low }
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move(cgpara.location^,paralochi^,sizeof(paralochi^));
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move(cgpara.location^.next^,paraloclo^,sizeof(paraloclo^));
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end
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else
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begin
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{ paraloc^ -> low
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paraloc^.next -> high }
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move(cgpara.location^,paraloclo^,sizeof(paraloclo^));
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move(cgpara.location^.next^,paralochi^,sizeof(paralochi^));
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end;
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end
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else
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begin
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{ single parameter, this can only be in memory }
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if cgpara.location^.loc<>LOC_REFERENCE then
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internalerror(200408282);
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move(cgpara.location^,paraloclo^,sizeof(paraloclo^));
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move(cgpara.location^,paralochi^,sizeof(paralochi^));
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{ for big endian low is at +4, for little endian high }
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if target_info.endian = endian_big then
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inc(cgparalo.location^.reference.offset,4)
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else
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inc(cgparahi.location^.reference.offset,4);
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end;
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{ fix size }
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paraloclo^.size:=cgparalo.size;
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paraloclo^.next:=nil;
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paralochi^.size:=cgparahi.size;
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paralochi^.next:=nil;
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end;
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{****************************************************************************
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TCG64F32
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****************************************************************************}
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procedure tcg64f32.a_load64_reg_ref(list : taasmoutput;reg : tregister64;const ref : treference);
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var
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tmpreg: tregister;
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tmpref: treference;
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begin
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if target_info.endian = endian_big then
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begin
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tmpreg:=reg.reglo;
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reg.reglo:=reg.reghi;
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reg.reghi:=tmpreg;
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end;
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cg.a_load_reg_ref(list,OS_32,OS_32,reg.reglo,ref);
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tmpref := ref;
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inc(tmpref.offset,4);
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cg.a_load_reg_ref(list,OS_32,OS_32,reg.reghi,tmpref);
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end;
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procedure tcg64f32.a_load64_const_ref(list : taasmoutput;value : int64;const ref : treference);
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var
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tmpref: treference;
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begin
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if target_info.endian = endian_big then
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swap64(value);
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cg.a_load_const_ref(list,OS_32,aint(lo(value)),ref);
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tmpref := ref;
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inc(tmpref.offset,4);
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cg.a_load_const_ref(list,OS_32,aint(hi(value)),tmpref);
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end;
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procedure tcg64f32.a_load64_ref_reg(list : taasmoutput;const ref : treference;reg : tregister64);
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var
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tmpreg: tregister;
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tmpref: treference;
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begin
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if target_info.endian = endian_big then
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begin
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tmpreg := reg.reglo;
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reg.reglo := reg.reghi;
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reg.reghi := tmpreg;
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end;
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tmpref := ref;
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if (tmpref.base=reg.reglo) then
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begin
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tmpreg:=cg.getaddressregister(list);
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cg.a_load_reg_reg(list,OS_ADDR,OS_ADDR,tmpref.base,tmpreg);
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tmpref.base:=tmpreg;
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end
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else
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{ this works only for the i386, thus the i386 needs to override }
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{ this method and this method must be replaced by a more generic }
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{ implementation FK }
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if (tmpref.index=reg.reglo) then
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begin
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tmpreg:=cg.getaddressregister(list);
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cg.a_load_reg_reg(list,OS_ADDR,OS_ADDR,tmpref.index,tmpreg);
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tmpref.index:=tmpreg;
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end;
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cg.a_load_ref_reg(list,OS_32,OS_32,tmpref,reg.reglo);
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inc(tmpref.offset,4);
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cg.a_load_ref_reg(list,OS_32,OS_32,tmpref,reg.reghi);
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end;
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procedure tcg64f32.a_load64_reg_reg(list : taasmoutput;regsrc,regdst : tregister64);
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begin
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cg.a_load_reg_reg(list,OS_32,OS_32,regsrc.reglo,regdst.reglo);
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cg.a_load_reg_reg(list,OS_32,OS_32,regsrc.reghi,regdst.reghi);
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end;
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procedure tcg64f32.a_load64_const_reg(list : taasmoutput;value : int64;reg : tregister64);
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begin
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cg.a_load_const_reg(list,OS_32,aint(lo(value)),reg.reglo);
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cg.a_load_const_reg(list,OS_32,aint(hi(value)),reg.reghi);
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end;
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procedure tcg64f32.a_load64_loc_reg(list : taasmoutput;const l : tlocation;reg : tregister64);
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begin
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case l.loc of
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LOC_REFERENCE, LOC_CREFERENCE:
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a_load64_ref_reg(list,l.reference,reg);
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LOC_REGISTER,LOC_CREGISTER:
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a_load64_reg_reg(list,l.register64,reg);
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LOC_CONSTANT :
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a_load64_const_reg(list,l.value64,reg);
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else
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internalerror(200112292);
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end;
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end;
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procedure tcg64f32.a_load64_loc_ref(list : taasmoutput;const l : tlocation;const ref : treference);
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begin
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case l.loc of
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LOC_REGISTER,LOC_CREGISTER:
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a_load64_reg_ref(list,l.register64,ref);
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LOC_CONSTANT :
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a_load64_const_ref(list,l.value64,ref);
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else
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internalerror(200203288);
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end;
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end;
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procedure tcg64f32.a_load64_const_loc(list : taasmoutput;value : int64;const l : tlocation);
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begin
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case l.loc of
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LOC_REFERENCE, LOC_CREFERENCE:
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a_load64_const_ref(list,value,l.reference);
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LOC_REGISTER,LOC_CREGISTER:
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a_load64_const_reg(list,value,l.register64);
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else
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internalerror(200112293);
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end;
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end;
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procedure tcg64f32.a_load64_reg_loc(list : taasmoutput;reg : tregister64;const l : tlocation);
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begin
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case l.loc of
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LOC_REFERENCE, LOC_CREFERENCE:
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a_load64_reg_ref(list,reg,l.reference);
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LOC_REGISTER,LOC_CREGISTER:
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a_load64_reg_reg(list,reg,l.register64);
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else
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internalerror(200112293);
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end;
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end;
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procedure tcg64f32.a_load64high_reg_ref(list : taasmoutput;reg : tregister;const ref : treference);
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var
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tmpref: treference;
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begin
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if target_info.endian = endian_big then
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cg.a_load_reg_ref(list,OS_32,OS_32,reg,ref)
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else
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begin
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tmpref := ref;
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inc(tmpref.offset,4);
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cg.a_load_reg_ref(list,OS_32,OS_32,reg,tmpref)
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end;
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end;
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procedure tcg64f32.a_load64low_reg_ref(list : taasmoutput;reg : tregister;const ref : treference);
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var
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tmpref: treference;
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begin
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if target_info.endian = endian_little then
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cg.a_load_reg_ref(list,OS_32,OS_32,reg,ref)
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else
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begin
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tmpref := ref;
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inc(tmpref.offset,4);
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cg.a_load_reg_ref(list,OS_32,OS_32,reg,tmpref)
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end;
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end;
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procedure tcg64f32.a_load64high_ref_reg(list : taasmoutput;const ref : treference;reg : tregister);
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var
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tmpref: treference;
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begin
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if target_info.endian = endian_big then
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cg.a_load_ref_reg(list,OS_32,OS_32,ref,reg)
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else
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begin
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tmpref := ref;
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inc(tmpref.offset,4);
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cg.a_load_ref_reg(list,OS_32,OS_32,tmpref,reg)
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end;
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end;
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procedure tcg64f32.a_load64low_ref_reg(list : taasmoutput;const ref : treference;reg : tregister);
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var
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tmpref: treference;
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begin
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if target_info.endian = endian_little then
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cg.a_load_ref_reg(list,OS_32,OS_32,ref,reg)
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else
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begin
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tmpref := ref;
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inc(tmpref.offset,4);
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cg.a_load_ref_reg(list,OS_32,OS_32,tmpref,reg)
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end;
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end;
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procedure tcg64f32.a_load64low_loc_reg(list : taasmoutput;const l : tlocation;reg : tregister);
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begin
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case l.loc of
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LOC_REFERENCE,
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LOC_CREFERENCE :
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a_load64low_ref_reg(list,l.reference,reg);
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LOC_REGISTER,
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LOC_CREGISTER :
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cg.a_load_reg_reg(list,OS_32,OS_32,l.register64.reglo,reg);
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LOC_CONSTANT :
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cg.a_load_const_reg(list,OS_32,aint(lo(l.value64)),reg);
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else
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internalerror(200203244);
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end;
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end;
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procedure tcg64f32.a_load64high_loc_reg(list : taasmoutput;const l : tlocation;reg : tregister);
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begin
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case l.loc of
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LOC_REFERENCE,
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LOC_CREFERENCE :
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a_load64high_ref_reg(list,l.reference,reg);
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LOC_REGISTER,
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LOC_CREGISTER :
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cg.a_load_reg_reg(list,OS_32,OS_32,l.register64.reghi,reg);
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LOC_CONSTANT :
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cg.a_load_const_reg(list,OS_32,hi(l.value64),reg);
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else
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internalerror(200203244);
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end;
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end;
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procedure tcg64f32.a_op64_const_loc(list : taasmoutput;op:TOpCG;size : tcgsize;value : int64;const l: tlocation);
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begin
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case l.loc of
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LOC_REFERENCE, LOC_CREFERENCE:
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a_op64_const_ref(list,op,size,value,l.reference);
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LOC_REGISTER,LOC_CREGISTER:
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a_op64_const_reg(list,op,size,value,l.register64);
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else
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internalerror(200203292);
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end;
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end;
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procedure tcg64f32.a_op64_reg_loc(list : taasmoutput;op:TOpCG;size : tcgsize;reg : tregister64;const l : tlocation);
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begin
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case l.loc of
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LOC_REFERENCE, LOC_CREFERENCE:
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a_op64_reg_ref(list,op,size,reg,l.reference);
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LOC_REGISTER,LOC_CREGISTER:
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a_op64_reg_reg(list,op,size,reg,l.register64);
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else
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internalerror(2002032422);
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end;
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end;
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procedure tcg64f32.a_op64_loc_reg(list : taasmoutput;op:TOpCG;size : tcgsize;const l : tlocation;reg : tregister64);
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begin
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case l.loc of
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LOC_REFERENCE, LOC_CREFERENCE:
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a_op64_ref_reg(list,op,size,l.reference,reg);
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LOC_REGISTER,LOC_CREGISTER:
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a_op64_reg_reg(list,op,size,l.register64,reg);
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LOC_CONSTANT :
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a_op64_const_reg(list,op,size,l.value64,reg);
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else
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internalerror(200203242);
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end;
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end;
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procedure tcg64f32.a_op64_ref_reg(list : taasmoutput;op:TOpCG;size : tcgsize;const ref : treference;reg : tregister64);
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var
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tempreg: tregister64;
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begin
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tempreg.reghi:=cg.getintregister(list,OS_32);
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tempreg.reglo:=cg.getintregister(list,OS_32);
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a_load64_ref_reg(list,ref,tempreg);
|
|
a_op64_reg_reg(list,op,size,tempreg,reg);
|
|
end;
|
|
|
|
|
|
procedure tcg64f32.a_op64_reg_ref(list : taasmoutput;op:TOpCG;size : tcgsize;reg : tregister64; const ref: treference);
|
|
var
|
|
tempreg: tregister64;
|
|
begin
|
|
tempreg.reghi:=cg.getintregister(list,OS_32);
|
|
tempreg.reglo:=cg.getintregister(list,OS_32);
|
|
a_load64_ref_reg(list,ref,tempreg);
|
|
a_op64_reg_reg(list,op,size,reg,tempreg);
|
|
a_load64_reg_ref(list,tempreg,ref);
|
|
end;
|
|
|
|
|
|
procedure tcg64f32.a_op64_const_ref(list : taasmoutput;op:TOpCG;size : tcgsize;value : int64;const ref : treference);
|
|
var
|
|
tempreg: tregister64;
|
|
begin
|
|
tempreg.reghi:=cg.getintregister(list,OS_32);
|
|
tempreg.reglo:=cg.getintregister(list,OS_32);
|
|
a_load64_ref_reg(list,ref,tempreg);
|
|
a_op64_const_reg(list,op,size,value,tempreg);
|
|
a_load64_reg_ref(list,tempreg,ref);
|
|
end;
|
|
|
|
|
|
procedure tcg64f32.a_param64_reg(list : taasmoutput;reg : tregister64;const paraloc : tcgpara);
|
|
var
|
|
tmplochi,tmploclo: tcgpara;
|
|
begin
|
|
tmploclo.init;
|
|
tmplochi.init;
|
|
splitparaloc64(paraloc,tmploclo,tmplochi);
|
|
{ Keep this order of first hi before lo to have
|
|
the correct push order for i386 }
|
|
cg.a_param_reg(list,OS_32,reg.reghi,tmplochi);
|
|
cg.a_param_reg(list,OS_32,reg.reglo,tmploclo);
|
|
tmploclo.done;
|
|
tmplochi.done;
|
|
end;
|
|
|
|
|
|
procedure tcg64f32.a_param64_const(list : taasmoutput;value : int64;const paraloc : tcgpara);
|
|
var
|
|
tmplochi,tmploclo: tcgpara;
|
|
begin
|
|
tmploclo.init;
|
|
tmplochi.init;
|
|
splitparaloc64(paraloc,tmploclo,tmplochi);
|
|
{ Keep this order of first hi before lo to have
|
|
the correct push order for i386 }
|
|
cg.a_param_const(list,OS_32,aint(hi(value)),tmplochi);
|
|
cg.a_param_const(list,OS_32,aint(lo(value)),tmploclo);
|
|
tmploclo.done;
|
|
tmplochi.done;
|
|
end;
|
|
|
|
|
|
procedure tcg64f32.a_param64_ref(list : taasmoutput;const r : treference;const paraloc : tcgpara);
|
|
var
|
|
tmprefhi,tmpreflo : treference;
|
|
tmploclo,tmplochi : tcgpara;
|
|
begin
|
|
tmploclo.init;
|
|
tmplochi.init;
|
|
splitparaloc64(paraloc,tmploclo,tmplochi);
|
|
tmprefhi:=r;
|
|
tmpreflo:=r;
|
|
if target_info.endian=endian_big then
|
|
inc(tmpreflo.offset,4)
|
|
else
|
|
inc(tmprefhi.offset,4);
|
|
{ Keep this order of first hi before lo to have
|
|
the correct push order for i386 }
|
|
cg.a_param_ref(list,OS_32,tmprefhi,tmplochi);
|
|
cg.a_param_ref(list,OS_32,tmpreflo,tmploclo);
|
|
tmploclo.done;
|
|
tmplochi.done;
|
|
end;
|
|
|
|
|
|
procedure tcg64f32.a_param64_loc(list : taasmoutput;const l:tlocation;const paraloc : tcgpara);
|
|
begin
|
|
case l.loc of
|
|
LOC_REGISTER,
|
|
LOC_CREGISTER :
|
|
a_param64_reg(list,l.register64,paraloc);
|
|
LOC_CONSTANT :
|
|
a_param64_const(list,l.value64,paraloc);
|
|
LOC_CREFERENCE,
|
|
LOC_REFERENCE :
|
|
a_param64_ref(list,l.reference,paraloc);
|
|
else
|
|
internalerror(200203287);
|
|
end;
|
|
end;
|
|
|
|
|
|
procedure tcg64f32.g_rangecheck64(list : taasmoutput;const l:tlocation;fromdef,todef:tdef);
|
|
|
|
var
|
|
neglabel,
|
|
poslabel,
|
|
endlabel: tasmlabel;
|
|
hreg : tregister;
|
|
hdef : torddef;
|
|
opsize : tcgsize;
|
|
oldregisterdef: boolean;
|
|
from_signed,to_signed: boolean;
|
|
temploc : tlocation;
|
|
|
|
begin
|
|
from_signed := is_signed(fromdef);
|
|
to_signed := is_signed(todef);
|
|
|
|
if not is_64bit(todef) then
|
|
begin
|
|
oldregisterdef := registerdef;
|
|
registerdef := false;
|
|
|
|
{ get the high dword in a register }
|
|
if l.loc in [LOC_REGISTER,LOC_CREGISTER] then
|
|
begin
|
|
hreg := l.register64.reghi;
|
|
end
|
|
else
|
|
begin
|
|
hreg:=cg.getintregister(list,OS_32);
|
|
a_load64high_ref_reg(list,l.reference,hreg);
|
|
end;
|
|
objectlibrary.getjumplabel(poslabel);
|
|
|
|
{ check high dword, must be 0 (for positive numbers) }
|
|
cg.a_cmp_const_reg_label(list,OS_32,OC_EQ,0,hreg,poslabel);
|
|
|
|
{ It can also be $ffffffff, but only for negative numbers }
|
|
if from_signed and to_signed then
|
|
begin
|
|
objectlibrary.getjumplabel(neglabel);
|
|
cg.a_cmp_const_reg_label(list,OS_32,OC_EQ,-1,hreg,neglabel);
|
|
end;
|
|
{ For all other values we have a range check error }
|
|
cg.a_call_name(list,'FPC_RANGEERROR');
|
|
|
|
{ if the high dword = 0, the low dword can be considered a }
|
|
{ simple cardinal }
|
|
cg.a_label(list,poslabel);
|
|
hdef:=torddef.create(u32bit,0,$ffffffff);
|
|
|
|
location_copy(temploc,l);
|
|
temploc.size:=OS_32;
|
|
|
|
if (temploc.loc in [LOC_REFERENCE,LOC_CREFERENCE]) and
|
|
(target_info.endian = endian_big) then
|
|
inc(temploc.reference.offset,4);
|
|
|
|
cg.g_rangecheck(list,temploc,hdef,todef);
|
|
hdef.free;
|
|
|
|
if from_signed and to_signed then
|
|
begin
|
|
objectlibrary.getjumplabel(endlabel);
|
|
cg.a_jmp_always(list,endlabel);
|
|
{ if the high dword = $ffffffff, then the low dword (when }
|
|
{ considered as a longint) must be < 0 }
|
|
cg.a_label(list,neglabel);
|
|
if l.loc in [LOC_REGISTER,LOC_CREGISTER] then
|
|
begin
|
|
hreg := l.register64.reglo;
|
|
end
|
|
else
|
|
begin
|
|
hreg:=cg.getintregister(list,OS_32);
|
|
a_load64low_ref_reg(list,l.reference,hreg);
|
|
end;
|
|
{ get a new neglabel (JM) }
|
|
objectlibrary.getjumplabel(neglabel);
|
|
cg.a_cmp_const_reg_label(list,OS_32,OC_LT,0,hreg,neglabel);
|
|
|
|
cg.a_call_name(list,'FPC_RANGEERROR');
|
|
|
|
{ if we get here, the 64bit value lies between }
|
|
{ longint($80000000) and -1 (JM) }
|
|
cg.a_label(list,neglabel);
|
|
hdef:=torddef.create(s32bit,longint($80000000),-1);
|
|
location_copy(temploc,l);
|
|
temploc.size:=OS_32;
|
|
cg.g_rangecheck(list,temploc,hdef,todef);
|
|
hdef.free;
|
|
cg.a_label(list,endlabel);
|
|
end;
|
|
registerdef := oldregisterdef;
|
|
end
|
|
else
|
|
{ todef = 64bit int }
|
|
{ no 64bit subranges supported, so only a small check is necessary }
|
|
|
|
{ if both are signed or both are unsigned, no problem! }
|
|
if (from_signed xor to_signed) and
|
|
{ also not if the fromdef is unsigned and < 64bit, since that will }
|
|
{ always fit in a 64bit int (todef is 64bit) }
|
|
(from_signed or
|
|
(torddef(fromdef).typ = u64bit)) then
|
|
begin
|
|
{ in all cases, there is only a problem if the higest bit is set }
|
|
if l.loc in [LOC_REGISTER,LOC_CREGISTER] then
|
|
begin
|
|
if is_64bit(fromdef) then
|
|
begin
|
|
hreg := l.register64.reghi;
|
|
opsize := OS_32;
|
|
end
|
|
else
|
|
begin
|
|
hreg := l.register;
|
|
opsize := def_cgsize(fromdef);
|
|
end;
|
|
end
|
|
else
|
|
begin
|
|
hreg:=cg.getintregister(list,OS_32);
|
|
|
|
opsize := def_cgsize(fromdef);
|
|
if opsize in [OS_64,OS_S64] then
|
|
a_load64high_ref_reg(list,l.reference,hreg)
|
|
else
|
|
cg.a_load_ref_reg(list,opsize,OS_32,l.reference,hreg);
|
|
end;
|
|
objectlibrary.getjumplabel(poslabel);
|
|
cg.a_cmp_const_reg_label(list,opsize,OC_GTE,0,hreg,poslabel);
|
|
|
|
cg.a_call_name(list,'FPC_RANGEERROR');
|
|
cg.a_label(list,poslabel);
|
|
end;
|
|
end;
|
|
|
|
|
|
function tcg64f32.optimize64_op_const_reg(list: taasmoutput; var op: topcg; var a : int64; var reg: tregister64): boolean;
|
|
var
|
|
lowvalue, highvalue : longint;
|
|
hreg: tregister;
|
|
begin
|
|
lowvalue := longint(a);
|
|
highvalue:= longint(a shr 32);
|
|
{ assume it will be optimized out }
|
|
optimize64_op_const_reg := true;
|
|
case op of
|
|
OP_ADD:
|
|
begin
|
|
if a = 0 then
|
|
exit;
|
|
end;
|
|
OP_AND:
|
|
begin
|
|
if lowvalue <> -1 then
|
|
cg.a_op_const_reg(list,op,OS_32,lowvalue,reg.reglo);
|
|
if highvalue <> -1 then
|
|
cg.a_op_const_reg(list,op,OS_32,highvalue,reg.reghi);
|
|
{ already emitted correctly }
|
|
exit;
|
|
end;
|
|
OP_OR:
|
|
begin
|
|
if lowvalue <> 0 then
|
|
cg.a_op_const_reg(list,op,OS_32,lowvalue,reg.reglo);
|
|
if highvalue <> 0 then
|
|
cg.a_op_const_reg(list,op,OS_32,highvalue,reg.reghi);
|
|
{ already emitted correctly }
|
|
exit;
|
|
end;
|
|
OP_SUB:
|
|
begin
|
|
if a = 0 then
|
|
exit;
|
|
end;
|
|
OP_XOR:
|
|
begin
|
|
end;
|
|
OP_SHL:
|
|
begin
|
|
if a = 0 then
|
|
exit;
|
|
{ simply clear low-register
|
|
and shift the rest and swap
|
|
registers.
|
|
}
|
|
if (a > 31) then
|
|
begin
|
|
cg.a_load_const_reg(list,OS_32,0,reg.reglo);
|
|
cg.a_op_const_reg(list,OP_SHL,OS_32,a mod 32,reg.reghi);
|
|
{ swap the registers }
|
|
hreg := reg.reghi;
|
|
reg.reghi := reg.reglo;
|
|
reg.reglo := hreg;
|
|
exit;
|
|
end;
|
|
end;
|
|
OP_SHR:
|
|
begin
|
|
if a = 0 then exit;
|
|
{ simply clear high-register
|
|
and shift the rest and swap
|
|
registers.
|
|
}
|
|
if (a > 31) then
|
|
begin
|
|
cg.a_load_const_reg(list,OS_32,0,reg.reghi);
|
|
cg.a_op_const_reg(list,OP_SHL,OS_32,a mod 32,reg.reglo);
|
|
{ swap the registers }
|
|
hreg := reg.reghi;
|
|
reg.reghi := reg.reglo;
|
|
reg.reglo := hreg;
|
|
exit;
|
|
end;
|
|
end;
|
|
OP_IMUL,OP_MUL:
|
|
begin
|
|
if a = 1 then exit;
|
|
end;
|
|
OP_IDIV,OP_DIV:
|
|
begin
|
|
if a = 1 then exit;
|
|
end;
|
|
else
|
|
internalerror(20020817);
|
|
end;
|
|
optimize64_op_const_reg := false;
|
|
end;
|
|
|
|
end.
|