mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-05-07 13:52:38 +02:00
9e5979e8be
Switched codegeneration of VFPv2 and VFPv3 to use UAL mnemonics and syntax. Updated VFP code in RTL to use UAL syntax too. Added preliminary ELF support for ARM. Added support for linking of WinCE COFF files. Should work for with a standard ARMv4-I target. git-svn-id: branches/laksen/armiw@29247 -
715 lines
27 KiB
ObjectPascal
715 lines
27 KiB
ObjectPascal
{
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Copyright (c) 2000-2002 by Florian Klaempfl
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Code generation for add nodes on the ARM
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit narmadd;
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{$i fpcdefs.inc}
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interface
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uses
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node,ncgadd,cpubase;
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type
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tarmaddnode = class(tcgaddnode)
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private
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function GetResFlags(unsigned:Boolean):TResFlags;
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function GetFpuResFlags:TResFlags;
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public
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function pass_1 : tnode;override;
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function use_generic_mul32to64: boolean; override;
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function use_generic_mul64bit: boolean; override;
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protected
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function first_addfloat: tnode; override;
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procedure second_addordinal;override;
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procedure second_addfloat;override;
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procedure second_cmpfloat;override;
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procedure second_cmpordinal;override;
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procedure second_cmpsmallset;override;
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procedure second_cmp64bit;override;
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procedure second_add64bit;override;
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end;
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implementation
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uses
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globtype,verbose,globals,systems,
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constexp,symdef,symtable,symtype,symconst,
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aasmbase,aasmdata,aasmcpu,
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defutil,htypechk,cgbase,cgutils,
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cpuinfo,pass_1,pass_2,procinfo,
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ncon,nadd,ncnv,ncal,nmat,
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ncgutil,cgobj,cgcpu,
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hlcgobj
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;
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{*****************************************************************************
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TSparcAddNode
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*****************************************************************************}
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function tarmaddnode.GetResFlags(unsigned:Boolean):TResFlags;
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begin
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case NodeType of
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equaln:
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GetResFlags:=F_EQ;
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unequaln:
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GetResFlags:=F_NE;
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else
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if not(unsigned) then
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begin
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if nf_swapped in flags then
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case NodeType of
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ltn:
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GetResFlags:=F_GT;
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lten:
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GetResFlags:=F_GE;
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gtn:
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GetResFlags:=F_LT;
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gten:
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GetResFlags:=F_LE;
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else
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internalerror(201408203);
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end
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else
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case NodeType of
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ltn:
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GetResFlags:=F_LT;
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lten:
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GetResFlags:=F_LE;
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gtn:
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GetResFlags:=F_GT;
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gten:
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GetResFlags:=F_GE;
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else
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internalerror(201408204);
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end;
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end
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else
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begin
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if nf_swapped in Flags then
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case NodeType of
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ltn:
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GetResFlags:=F_HI;
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lten:
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GetResFlags:=F_CS;
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gtn:
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GetResFlags:=F_CC;
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gten:
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GetResFlags:=F_LS;
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else
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internalerror(201408205);
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end
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else
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case NodeType of
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ltn:
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GetResFlags:=F_CC;
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lten:
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GetResFlags:=F_LS;
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gtn:
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GetResFlags:=F_HI;
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gten:
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GetResFlags:=F_CS;
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else
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internalerror(201408206);
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end;
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end;
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end;
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end;
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function tarmaddnode.GetFpuResFlags:TResFlags;
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begin
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if nf_swapped in Flags then
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internalerror(2014042001);
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case NodeType of
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equaln:
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result:=F_EQ;
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unequaln:
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result:=F_NE;
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ltn:
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result:=F_MI;
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lten:
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result:=F_LS;
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gtn:
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result:=F_GT;
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gten:
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result:=F_GE;
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else
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internalerror(201408207);
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end;
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end;
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procedure tarmaddnode.second_addfloat;
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var
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op : TAsmOp;
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singleprec: boolean;
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pf: TOpPostfix;
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begin
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pass_left_right;
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if (nf_swapped in flags) then
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swapleftright;
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case current_settings.fputype of
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fpu_fpa,
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fpu_fpa10,
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fpu_fpa11:
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begin
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{ force fpureg as location, left right doesn't matter
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as both will be in a fpureg }
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hlcg.location_force_fpureg(current_asmdata.CurrAsmList,left.location,left.resultdef,true);
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hlcg.location_force_fpureg(current_asmdata.CurrAsmList,right.location,right.resultdef,true);
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location_reset(location,LOC_FPUREGISTER,def_cgsize(resultdef));
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location.register:=cg.getfpuregister(current_asmdata.CurrAsmList,location.size);
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case nodetype of
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addn :
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op:=A_ADF;
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muln :
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op:=A_MUF;
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subn :
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op:=A_SUF;
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slashn :
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op:=A_DVF;
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else
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internalerror(200308313);
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end;
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current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg_reg(op,
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location.register,left.location.register,right.location.register),
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cgsize2fpuoppostfix[def_cgsize(resultdef)]));
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end;
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fpu_vfpv2,
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fpu_vfpv3,
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fpu_vfpv3_d16:
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begin
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{ force mmreg as location, left right doesn't matter
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as both will be in a fpureg }
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hlcg.location_force_mmregscalar(current_asmdata.CurrAsmList,left.location,left.resultdef,true);
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hlcg.location_force_mmregscalar(current_asmdata.CurrAsmList,right.location,right.resultdef,true);
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location_reset(location,LOC_MMREGISTER,def_cgsize(resultdef));
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location.register:=cg.getmmregister(current_asmdata.CurrAsmList,location.size);
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singleprec:=tfloatdef(left.resultdef).floattype=s32real;
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if singleprec then
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pf:=PF_F32
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else
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pf:=PF_F64;
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case nodetype of
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addn :
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op:=A_VADD;
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muln :
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op:=A_VMUL;
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subn :
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op:=A_VSUB;
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slashn :
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op:=A_VDIV;
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else
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internalerror(2009111401);
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end;
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current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg_reg(op,
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location.register,left.location.register,right.location.register),pf));
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end;
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fpu_fpv4_s16:
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begin
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{ force mmreg as location, left right doesn't matter
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as both will be in a fpureg }
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hlcg.location_force_mmregscalar(current_asmdata.CurrAsmList,left.location,left.resultdef,true);
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hlcg.location_force_mmregscalar(current_asmdata.CurrAsmList,right.location,right.resultdef,true);
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location_reset(location,LOC_MMREGISTER,def_cgsize(resultdef));
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location.register:=cg.getmmregister(current_asmdata.CurrAsmList,location.size);
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case nodetype of
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addn :
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op:=A_VADD;
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muln :
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op:=A_VMUL;
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subn :
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op:=A_VSUB;
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slashn :
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op:=A_VDIV;
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else
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internalerror(2009111401);
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end;
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current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg_reg(op, location.register,left.location.register,right.location.register), PF_F32));
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end;
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fpu_soft:
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{ this case should be handled already by pass1 }
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internalerror(200308252);
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else
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internalerror(200308251);
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end;
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end;
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procedure tarmaddnode.second_cmpfloat;
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var
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op: TAsmOp;
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pf: TOpPostfix;
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begin
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pass_left_right;
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if (nf_swapped in flags) then
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swapleftright;
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location_reset(location,LOC_FLAGS,OS_NO);
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location.resflags:=getresflags(false);
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case current_settings.fputype of
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fpu_fpa,
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fpu_fpa10,
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fpu_fpa11:
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begin
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{ force fpureg as location, left right doesn't matter
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as both will be in a fpureg }
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hlcg.location_force_fpureg(current_asmdata.CurrAsmList,left.location,left.resultdef,true);
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hlcg.location_force_fpureg(current_asmdata.CurrAsmList,right.location,right.resultdef,true);
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cg.a_reg_alloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
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if nodetype in [equaln,unequaln] then
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current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg(A_CMF,
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left.location.register,right.location.register),
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cgsize2fpuoppostfix[def_cgsize(resultdef)]))
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else
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current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg(A_CMFE,
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left.location.register,right.location.register),
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cgsize2fpuoppostfix[def_cgsize(resultdef)]));
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end;
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fpu_vfpv2,
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fpu_vfpv3,
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fpu_vfpv3_d16:
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begin
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hlcg.location_force_mmregscalar(current_asmdata.CurrAsmList,left.location,left.resultdef,true);
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hlcg.location_force_mmregscalar(current_asmdata.CurrAsmList,right.location,right.resultdef,true);
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if nodetype in [equaln,unequaln] then
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op:=A_VCMP
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else
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op:=A_VCMPE;
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if (tfloatdef(left.resultdef).floattype=s32real) then
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pf:=PF_F32
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else
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pf:=PF_F64;
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current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg(op,
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left.location.register,right.location.register), pf));
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cg.a_reg_alloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_VMRS,NR_APSR_nzcv,NR_FPSCR));
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location.resflags:=GetFpuResFlags;
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end;
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fpu_fpv4_s16:
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begin
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hlcg.location_force_mmregscalar(current_asmdata.CurrAsmList,left.location,left.resultdef,true);
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hlcg.location_force_mmregscalar(current_asmdata.CurrAsmList,right.location,right.resultdef,true);
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if nodetype in [equaln,unequaln] then
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op:=A_VCMP
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else
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op:=A_VCMPE;
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(op,
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left.location.register,right.location.register));
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cg.a_reg_alloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
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current_asmdata.CurrAsmList.Concat(taicpu.op_reg_reg(A_VMRS, NR_APSR_nzcv, NR_FPSCR));
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end;
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fpu_soft:
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{ this case should be handled already by pass1 }
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internalerror(2009112404);
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end;
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end;
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procedure tarmaddnode.second_cmpsmallset;
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var
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tmpreg : tregister;
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b: byte;
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begin
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pass_left_right;
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location_reset(location,LOC_FLAGS,OS_NO);
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if (not(nf_swapped in flags) and
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(nodetype = lten)) or
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((nf_swapped in flags) and
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(nodetype = gten)) then
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swapleftright;
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(* Try to keep right as a constant *)
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if (right.location.loc <> LOC_CONSTANT) or
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not(is_shifter_const(right.location.value, b)) or
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((GenerateThumbCode) and not(is_thumb_imm(right.location.value))) then
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hlcg.location_force_reg(current_asmdata.CurrAsmList,right.location,right.resultdef,right.resultdef,true);
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,true);
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case nodetype of
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equaln,
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unequaln:
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begin
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cg.a_reg_alloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
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if right.location.loc = LOC_CONSTANT then
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_const(A_CMP,left.location.register,right.location.value))
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else
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_CMP,left.location.register,right.location.register));
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if nodetype = equaln then
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location.resflags:=F_EQ
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else
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location.resflags:=F_NE;
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end;
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lten,
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gten:
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begin
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tmpreg:=cg.getintregister(current_asmdata.CurrAsmList,location.size);
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if right.location.loc = LOC_CONSTANT then
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begin
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_AND,OS_32,right.location.value,left.location.register,tmpreg);
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cg.a_reg_alloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_const(A_CMP,tmpreg,right.location.value));
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end
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else
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begin
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cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList,OP_AND,OS_32,left.location.register,right.location.register,tmpreg);
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cg.a_reg_alloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_CMP,tmpreg,right.location.register));
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end;
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location.resflags:=F_EQ;
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end;
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else
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internalerror(2004012401);
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end;
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end;
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procedure tarmaddnode.second_cmp64bit;
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var
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unsigned : boolean;
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oldnodetype : tnodetype;
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dummyreg : tregister;
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l: tasmlabel;
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const
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lt_zero_swapped: array[boolean] of tnodetype = (ltn, gtn);
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begin
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unsigned:=not(is_signed(left.resultdef)) or
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not(is_signed(right.resultdef));
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pass_left_right;
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{ pass_left_right moves possible consts to the right, the only
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remaining case with left consts (currency) can take this path too (KB) }
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if (right.nodetype=ordconstn) and
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(tordconstnode(right).value=0) and
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((nodetype in [equaln,unequaln]) or
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(not(GenerateThumbCode) and is_signed(left.resultdef) and (nodetype = lt_zero_swapped[nf_swapped in Flags]))
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) then
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begin
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location_reset(location,LOC_FLAGS,OS_NO);
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if not(left.location.loc in [LOC_CREGISTER,LOC_REGISTER]) then
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,true);
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cg.a_reg_alloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
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{ Optimize for the common case of int64 < 0 }
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if nodetype in [ltn, gtn] then
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begin
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{Just check for the MSB in reghi to be set or not, this is independed from nf_swapped}
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location.resflags:=F_NE;
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_const(A_TST,left.location.register64.reghi, aint($80000000)));
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end
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else
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begin
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location.resflags:=getresflags(unsigned);
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dummyreg:=cg.getintregister(current_asmdata.CurrAsmList,location.size);
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if GenerateThumbCode then
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cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList,OP_OR,OS_32,left.location.register64.reglo,left.location.register64.reghi,dummyreg)
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else
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current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg_reg(A_ORR,dummyreg,left.location.register64.reglo,left.location.register64.reghi),PF_S));
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end;
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end
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else
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begin
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,true);
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hlcg.location_force_reg(current_asmdata.CurrAsmList,right.location,right.resultdef,right.resultdef,true);
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{ operation requiring proper N, Z and C flags ? }
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if unsigned or (nodetype in [equaln,unequaln]) then
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begin
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location_reset(location,LOC_FLAGS,OS_NO);
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location.resflags:=getresflags(unsigned);
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cg.a_reg_alloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_CMP,left.location.register64.reghi,right.location.register64.reghi));
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if GenerateThumbCode or GenerateThumb2Code then
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begin
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current_asmdata.getjumplabel(l);
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cg.a_jmp_flags(current_asmdata.CurrAsmList,F_NE,l);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_CMP,left.location.register64.reglo,right.location.register64.reglo));
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cg.a_label(current_asmdata.CurrAsmList,l);
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end
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else
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current_asmdata.CurrAsmList.concat(setcondition(taicpu.op_reg_reg(A_CMP,left.location.register64.reglo,right.location.register64.reglo),C_EQ));
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end
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else
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{ operation requiring proper N, Z and V flags ? }
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begin
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location_reset(location,LOC_JUMP,OS_NO);
|
|
cg.a_reg_alloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
|
|
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_CMP,left.location.register64.reghi,right.location.register64.reghi));
|
|
{ the jump the sequence is a little bit hairy }
|
|
case nodetype of
|
|
ltn,gtn:
|
|
begin
|
|
cg.a_jmp_flags(current_asmdata.CurrAsmList,getresflags(false),current_procinfo.CurrTrueLabel);
|
|
{ cheat a little bit for the negative test }
|
|
toggleflag(nf_swapped);
|
|
cg.a_jmp_flags(current_asmdata.CurrAsmList,getresflags(false),current_procinfo.CurrFalseLabel);
|
|
cg.a_reg_dealloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
|
|
toggleflag(nf_swapped);
|
|
end;
|
|
lten,gten:
|
|
begin
|
|
oldnodetype:=nodetype;
|
|
if nodetype=lten then
|
|
nodetype:=ltn
|
|
else
|
|
nodetype:=gtn;
|
|
cg.a_jmp_flags(current_asmdata.CurrAsmList,getresflags(unsigned),current_procinfo.CurrTrueLabel);
|
|
{ cheat for the negative test }
|
|
if nodetype=ltn then
|
|
nodetype:=gtn
|
|
else
|
|
nodetype:=ltn;
|
|
cg.a_jmp_flags(current_asmdata.CurrAsmList,getresflags(unsigned),current_procinfo.CurrFalseLabel);
|
|
cg.a_reg_dealloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
|
|
nodetype:=oldnodetype;
|
|
end;
|
|
end;
|
|
cg.a_reg_alloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
|
|
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_CMP,left.location.register64.reglo,right.location.register64.reglo));
|
|
{ the comparisaion of the low dword have to be
|
|
always unsigned! }
|
|
cg.a_jmp_flags(current_asmdata.CurrAsmList,getresflags(true),current_procinfo.CurrTrueLabel);
|
|
cg.a_jmp_always(current_asmdata.CurrAsmList,current_procinfo.CurrFalseLabel);
|
|
cg.a_reg_dealloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
|
|
end;
|
|
end;
|
|
end;
|
|
|
|
procedure tarmaddnode.second_add64bit;
|
|
var
|
|
asmList : TAsmList;
|
|
ll,rl,res : TRegister64;
|
|
tmpreg: TRegister;
|
|
begin
|
|
if (nodetype in [muln]) then
|
|
begin
|
|
asmList := current_asmdata.CurrAsmList;
|
|
pass_left_right;
|
|
force_reg_left_right(true, (left.location.loc<>LOC_CONSTANT) and (right.location.loc<>LOC_CONSTANT));
|
|
set_result_location_reg;
|
|
|
|
{ shortcuts to register64s }
|
|
ll:=left.location.register64;
|
|
rl:=right.location.register64;
|
|
res:=location.register64;
|
|
|
|
tmpreg := cg.getintregister(current_asmdata.CurrAsmList,OS_32);
|
|
asmList.concat(taicpu.op_reg_reg_reg(A_MUL,tmpreg,ll.reglo,rl.reghi));
|
|
asmList.concat(taicpu.op_reg_reg_reg_reg(A_UMULL,res.reglo,res.reghi,rl.reglo,ll.reglo));
|
|
tbasecgarm(cg).safe_mla(asmList,tmpreg,rl.reglo,ll.reghi,tmpreg);
|
|
asmList.concat(taicpu.op_reg_reg_reg(A_ADD,res.reghi,tmpreg,res.reghi));
|
|
end
|
|
else
|
|
inherited second_add64bit;
|
|
end;
|
|
|
|
function tarmaddnode.pass_1 : tnode;
|
|
var
|
|
unsigned : boolean;
|
|
begin
|
|
result:=inherited pass_1;
|
|
|
|
if not(assigned(result)) then
|
|
begin
|
|
unsigned:=not(is_signed(left.resultdef)) or
|
|
not(is_signed(right.resultdef));
|
|
|
|
if is_64bit(left.resultdef) and
|
|
((nodetype in [equaln,unequaln]) or
|
|
(unsigned and (nodetype in [ltn,lten,gtn,gten]))
|
|
) then
|
|
expectloc:=LOC_FLAGS;
|
|
end;
|
|
end;
|
|
|
|
function tarmaddnode.first_addfloat: tnode;
|
|
var
|
|
procname: string[31];
|
|
{ do we need to reverse the result ? }
|
|
notnode : boolean;
|
|
fdef : tdef;
|
|
begin
|
|
result := nil;
|
|
notnode := false;
|
|
|
|
if current_settings.fputype = fpu_fpv4_s16 then
|
|
begin
|
|
case tfloatdef(left.resultdef).floattype of
|
|
s32real:
|
|
begin
|
|
result:=nil;
|
|
notnode:=false;
|
|
end;
|
|
s64real:
|
|
begin
|
|
fdef:=search_system_type('FLOAT64').typedef;
|
|
procname:='float64';
|
|
|
|
case nodetype of
|
|
addn:
|
|
procname:=procname+'_add';
|
|
muln:
|
|
procname:=procname+'_mul';
|
|
subn:
|
|
procname:=procname+'_sub';
|
|
slashn:
|
|
procname:=procname+'_div';
|
|
ltn:
|
|
procname:=procname+'_lt';
|
|
lten:
|
|
procname:=procname+'_le';
|
|
gtn:
|
|
begin
|
|
procname:=procname+'_lt';
|
|
swapleftright;
|
|
end;
|
|
gten:
|
|
begin
|
|
procname:=procname+'_le';
|
|
swapleftright;
|
|
end;
|
|
equaln:
|
|
procname:=procname+'_eq';
|
|
unequaln:
|
|
begin
|
|
procname:=procname+'_eq';
|
|
notnode:=true;
|
|
end;
|
|
else
|
|
CGMessage3(type_e_operator_not_supported_for_types,node2opstr(nodetype),left.resultdef.typename,right.resultdef.typename);
|
|
end;
|
|
|
|
if nodetype in [ltn,lten,gtn,gten,equaln,unequaln] then
|
|
resultdef:=pasbool8type;
|
|
result:=ctypeconvnode.create_internal(ccallnode.createintern(procname,ccallparanode.create(
|
|
ctypeconvnode.create_internal(right,fdef),
|
|
ccallparanode.create(
|
|
ctypeconvnode.create_internal(left,fdef),nil))),resultdef);
|
|
|
|
left:=nil;
|
|
right:=nil;
|
|
|
|
{ do we need to reverse the result }
|
|
if notnode then
|
|
result:=cnotnode.create(result);
|
|
end;
|
|
end;
|
|
end
|
|
else
|
|
result:=inherited first_addfloat;
|
|
end;
|
|
|
|
|
|
procedure tarmaddnode.second_cmpordinal;
|
|
var
|
|
unsigned : boolean;
|
|
tmpreg : tregister;
|
|
b : byte;
|
|
begin
|
|
pass_left_right;
|
|
force_reg_left_right(true,true);
|
|
|
|
unsigned:=not(is_signed(left.resultdef)) or
|
|
not(is_signed(right.resultdef));
|
|
cg.a_reg_alloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
|
|
if right.location.loc = LOC_CONSTANT then
|
|
begin
|
|
if (not(GenerateThumbCode) and is_shifter_const(right.location.value,b)) or
|
|
((GenerateThumbCode) and is_thumb_imm(right.location.value)) then
|
|
current_asmdata.CurrAsmList.concat(taicpu.op_reg_const(A_CMP,left.location.register,right.location.value))
|
|
else
|
|
begin
|
|
tmpreg:=cg.getintregister(current_asmdata.CurrAsmList,location.size);
|
|
cg.a_load_const_reg(current_asmdata.CurrAsmList,OS_INT,
|
|
right.location.value,tmpreg);
|
|
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_CMP,left.location.register,tmpreg));
|
|
end;
|
|
end
|
|
else
|
|
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_CMP,left.location.register,right.location.register));
|
|
|
|
location_reset(location,LOC_FLAGS,OS_NO);
|
|
location.resflags:=getresflags(unsigned);
|
|
end;
|
|
|
|
const
|
|
multops: array[boolean] of TAsmOp = (A_SMULL, A_UMULL);
|
|
|
|
procedure tarmaddnode.second_addordinal;
|
|
var
|
|
unsigned: boolean;
|
|
begin
|
|
if (nodetype=muln) and
|
|
is_64bit(resultdef) and
|
|
not(GenerateThumbCode) and
|
|
(CPUARM_HAS_UMULL in cpu_capabilities[current_settings.cputype]) then
|
|
begin
|
|
pass_left_right;
|
|
force_reg_left_right(true, false);
|
|
set_result_location_reg;
|
|
unsigned:=not(is_signed(left.resultdef)) or
|
|
not(is_signed(right.resultdef));
|
|
current_asmdata.CurrAsmList.Concat(
|
|
taicpu.op_reg_reg_reg_reg(multops[unsigned], location.register64.reglo, location.register64.reghi,
|
|
left.location.register,right.location.register));
|
|
end
|
|
else
|
|
inherited second_addordinal;
|
|
end;
|
|
|
|
function tarmaddnode.use_generic_mul32to64: boolean;
|
|
begin
|
|
result:=GenerateThumbCode or not(CPUARM_HAS_UMULL in cpu_capabilities[current_settings.cputype]);
|
|
end;
|
|
|
|
function tarmaddnode.use_generic_mul64bit: boolean;
|
|
begin
|
|
result:=GenerateThumbCode or
|
|
not(CPUARM_HAS_UMULL in cpu_capabilities[current_settings.cputype]) or
|
|
(cs_check_overflow in current_settings.localswitches);
|
|
end;
|
|
|
|
begin
|
|
caddnode:=tarmaddnode;
|
|
end.
|