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186 lines
7.3 KiB
ObjectPascal
186 lines
7.3 KiB
ObjectPascal
{
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Copyright (c) 1998-2002 by the Free Pascal development team
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Basic Processor information for the m68k
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See the file COPYING.FPC, included in this distribution,
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for details about the copyright.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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**********************************************************************}
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Unit CPUInfo;
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Interface
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uses
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globtype;
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Type
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bestreal = double;
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{$if FPC_FULLVERSION>20700}
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bestrealrec = TDoubleRec;
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{$endif FPC_FULLVERSION>20700}
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ts32real = single;
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ts64real = double;
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ts80real = extended;
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ts128real = type extended;
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ts64comp = extended;
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pbestreal=^bestreal;
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{ possible supported processors for this target }
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tcputype =
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(cpu_none,
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cpu_MC68000,
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cpu_MC68020,
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cpu_MC68040,
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cpu_MC68060,
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cpu_isa_a,
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cpu_isa_a_p,
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cpu_isa_b,
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cpu_isa_c,
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cpu_cfv4e
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);
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tfputype =
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(fpu_none,
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fpu_soft,
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fpu_libgcc,
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fpu_68881,
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fpu_coldfire
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);
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tcontrollertype =
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(ct_none
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);
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tcontrollerdatatype = record
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controllertypestr, controllerunitstr: string[20];
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cputype: tcputype; fputype: tfputype;
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flashbase, flashsize, srambase, sramsize, eeprombase, eepromsize, bootbase, bootsize: dword;
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end;
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Const
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{ Is there support for dealing with multiple microcontrollers available }
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{ for this platform? }
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ControllerSupport = false;
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{ We know that there are fields after sramsize
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but we don't care about this warning }
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{$PUSH}
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{$WARN 3177 OFF}
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embedded_controllers : array [tcontrollertype] of tcontrollerdatatype =
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(
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(controllertypestr:''; controllerunitstr:''; cputype:cpu_none; fputype:fpu_none; flashbase:0; flashsize:0; srambase:0; sramsize:0));
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{$POP}
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{ calling conventions supported by the code generator }
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supported_calling_conventions : tproccalloptions = [
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pocall_internproc,
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pocall_register,
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pocall_stdcall,
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pocall_safecall,
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{ the difference to stdcall is only the name mangling }
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pocall_cdecl,
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{ the difference to stdcall is only the name mangling }
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pocall_cppdecl,
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{ this is used by PalmOS, Atari and Amiga-likes }
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pocall_syscall
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];
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cputypestr : array[tcputype] of string[8] = ('',
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'68000',
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'68020',
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'68040',
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'68060',
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'ISAA',
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'ISAA+',
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'ISAB',
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'ISAC',
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'CFV4E'
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);
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gascputypestr : array[tcputype] of string[8] = ('',
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'68000',
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'68020',
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'68040',
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'68060',
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'isaa',
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'isaaplus',
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'isab',
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'isac',
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'cfv4e'
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);
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fputypestr : array[tfputype] of string[8] = ('',
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'SOFT',
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'LIBGCC',
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'68881',
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'COLDFIRE'
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);
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{ Supported optimizations, only used for information }
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supported_optimizerswitches = genericlevel1optimizerswitches+
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genericlevel2optimizerswitches+
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genericlevel3optimizerswitches-
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{ no need to write info about those }
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[cs_opt_level1,cs_opt_level2,cs_opt_level3]+
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[cs_opt_regvar,cs_opt_stackframe,cs_opt_loopunroll,
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cs_opt_tailrecursion,cs_opt_nodecse,
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cs_opt_reorder_fields,cs_opt_fastmath];
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level1optimizerswitches = genericlevel1optimizerswitches;
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level2optimizerswitches = genericlevel2optimizerswitches + level1optimizerswitches +
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[cs_opt_regvar,cs_opt_stackframe,cs_opt_tailrecursion,cs_opt_nodecse];
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level3optimizerswitches = genericlevel3optimizerswitches + level2optimizerswitches + [{,cs_opt_loopunroll}];
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level4optimizerswitches = genericlevel4optimizerswitches + level3optimizerswitches + [];
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type
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tcpuflags =
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(CPUM68K_HAS_DBRA, { CPU supports the DBRA instruction }
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CPUM68K_HAS_CAS, { CPU supports the CAS instruction }
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CPUM68K_HAS_TAS, { CPU supports the TAS instruction }
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CPUM68K_HAS_BRAL, { CPU supports the BRA.L/Bcc.L instructions }
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CPUM68K_HAS_ROLROR, { CPU supports the ROL/ROR and ROXL/ROXR instructions }
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CPUM68K_HAS_BYTEREV, { CPU supports the BYTEREV instruction }
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CPUM68K_HAS_MVSMVZ, { CPU supports the MVZ and MVS instructions }
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CPUM68K_HAS_MOVE16, { CPU supports the MOVE16 instruction }
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CPUM68K_HAS_32BITMUL, { CPU supports MULS/MULU 32x32 -> 32bit }
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CPUM68K_HAS_64BITMUL, { CPU supports MULS/MULU 32x32 -> 64bit }
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CPUM68K_HAS_16BITDIV, { CPU supports DIVS/DIVU 32/16 -> 16bit }
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CPUM68K_HAS_32BITDIV, { CPU supports DIVS/DIVU 32/32 -> 32bit }
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CPUM68K_HAS_64BITDIV, { CPU supports DIVS/DIVU 64/32 -> 32bit }
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CPUM68K_HAS_REMSREMU, { CPU supports the REMS/REMU instructions }
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CPUM68K_HAS_UNALIGNED, { CPU supports unaligned access }
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CPUM68K_HAS_BASEDISP { CPU supports addressing with 32bit base displacements }
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);
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const
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cpu_capabilities : array[tcputype] of set of tcpuflags =
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( { cpu_none } [],
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{ cpu_68000 } [CPUM68K_HAS_DBRA,CPUM68K_HAS_TAS,CPUM68K_HAS_ROLROR,CPUM68K_HAS_16BITDIV],
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{ cpu_68020 } [CPUM68K_HAS_DBRA,CPUM68K_HAS_CAS,CPUM68K_HAS_TAS,CPUM68K_HAS_BRAL,CPUM68K_HAS_ROLROR,CPUM68K_HAS_UNALIGNED,CPUM68K_HAS_BASEDISP,CPUM68K_HAS_32BITMUL,CPUM68K_HAS_64BITMUL,CPUM68K_HAS_16BITDIV,CPUM68K_HAS_32BITDIV,CPUM68K_HAS_64BITDIV],
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{ cpu_68040 } [CPUM68K_HAS_DBRA,CPUM68K_HAS_CAS,CPUM68K_HAS_TAS,CPUM68K_HAS_BRAL,CPUM68K_HAS_ROLROR,CPUM68K_HAS_UNALIGNED,CPUM68K_HAS_BASEDISP,CPUM68K_HAS_32BITMUL,CPUM68K_HAS_64BITMUL,CPUM68K_HAS_16BITDIV,CPUM68K_HAS_32BITDIV,CPUM68K_HAS_64BITDIV,CPUM68K_HAS_MOVE16],
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{ cpu_68060 } [CPUM68K_HAS_DBRA,CPUM68K_HAS_CAS,CPUM68K_HAS_TAS,CPUM68K_HAS_BRAL,CPUM68K_HAS_ROLROR,CPUM68K_HAS_UNALIGNED,CPUM68K_HAS_BASEDISP,CPUM68K_HAS_32BITMUL,CPUM68K_HAS_16BITDIV,CPUM68K_HAS_32BITDIV,CPUM68K_HAS_MOVE16],
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{ cpu_isaa } [CPUM68K_HAS_UNALIGNED,CPUM68K_HAS_32BITMUL,CPUM68K_HAS_16BITDIV,CPUM68K_HAS_32BITDIV,CPUM68K_HAS_REMSREMU],
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{ cpu_isaap } [CPUM68K_HAS_BRAL,CPUM68K_HAS_BYTEREV,CPUM68K_HAS_UNALIGNED,CPUM68K_HAS_32BITMUL,CPUM68K_HAS_16BITDIV,CPUM68K_HAS_32BITDIV,CPUM68K_HAS_REMSREMU],
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{ cpu_isab } [CPUM68K_HAS_TAS,CPUM68K_HAS_BRAL,CPUM68K_HAS_MVSMVZ,CPUM68K_HAS_UNALIGNED,CPUM68K_HAS_32BITMUL,CPUM68K_HAS_16BITDIV,CPUM68K_HAS_32BITDIV,CPUM68K_HAS_REMSREMU],
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{ cpu_isac } [CPUM68K_HAS_TAS,CPUM68K_HAS_BYTEREV,CPUM68K_HAS_MVSMVZ,CPUM68K_HAS_UNALIGNED,CPUM68K_HAS_32BITMUL,CPUM68K_HAS_16BITDIV,CPUM68K_HAS_32BITDIV,CPUM68K_HAS_REMSREMU],
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{ cpu_cfv4e } [CPUM68K_HAS_TAS,CPUM68K_HAS_BRAL,CPUM68K_HAS_MVSMVZ,CPUM68K_HAS_UNALIGNED,CPUM68K_HAS_32BITMUL,CPUM68K_HAS_16BITDIV,CPUM68K_HAS_32BITDIV,CPUM68K_HAS_REMSREMU]
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);
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{ all CPUs commonly called "coldfire" }
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cpu_coldfire = [cpu_isa_a,cpu_isa_a_p,cpu_isa_b,cpu_isa_c,cpu_cfv4e];
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{ all CPUs commonly called "68020+" }
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cpu_mc68020p = [cpu_mc68020,cpu_mc68040,cpu_mc68060];
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Implementation
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end.
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