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a3ab2053c9
getjumplabel and added type para to getlabel for specific types * moved lineinfo generation from assemble and aggas to dbgstabs git-svn-id: trunk@1120 -
325 lines
11 KiB
ObjectPascal
325 lines
11 KiB
ObjectPascal
{
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Copyright (c) 1998-2002 by Florian Klaempfl
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Generate i386 assembler for math nodes
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit n386mat;
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{$i fpcdefs.inc}
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interface
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uses
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node,nmat,ncgmat,nx86mat;
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type
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ti386moddivnode = class(tmoddivnode)
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procedure pass_2;override;
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end;
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ti386shlshrnode = class(tshlshrnode)
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procedure pass_2;override;
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{ everything will be handled in pass_2 }
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function first_shlshr64bitint: tnode; override;
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end;
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ti386unaryminusnode = class(tx86unaryminusnode)
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end;
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ti386notnode = class(tx86notnode)
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end;
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implementation
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uses
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globtype,systems,
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cutils,verbose,globals,
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symconst,symdef,aasmbase,aasmtai,defutil,
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cgbase,pass_2,
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ncon,
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cpubase,cpuinfo,
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cga,ncgutil,cgobj,cgutils;
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{*****************************************************************************
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TI386MODDIVNODE
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*****************************************************************************}
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procedure ti386moddivnode.pass_2;
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var hreg1,hreg2:Tregister;
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power:longint;
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hl:Tasmlabel;
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op:Tasmop;
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begin
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secondpass(left);
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if codegenerror then
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exit;
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secondpass(right);
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if codegenerror then
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exit;
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if is_64bitint(resulttype.def) then
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{ should be handled in pass_1 (JM) }
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internalerror(200109052);
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{ put numerator in register }
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location_reset(location,LOC_REGISTER,OS_INT);
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location_force_reg(exprasmlist,left.location,OS_INT,false);
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hreg1:=left.location.register;
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if (nodetype=divn) and (right.nodetype=ordconstn) and
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ispowerof2(tordconstnode(right).value,power) then
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begin
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{ for signed numbers, the numerator must be adjusted before the
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shift instruction, but not wih unsigned numbers! Otherwise,
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"Cardinal($ffffffff) div 16" overflows! (JM) }
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if is_signed(left.resulttype.def) Then
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begin
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if (aktOptProcessor <> class386) and
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not(cs_littlesize in aktglobalswitches) then
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{ use a sequence without jumps, saw this in
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comp.compilers (JM) }
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begin
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{ no jumps, but more operations }
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hreg2:=cg.getintregister(exprasmlist,OS_INT);
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emit_reg_reg(A_MOV,S_L,hreg1,hreg2);
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{If the left value is signed, hreg2=$ffffffff, otherwise 0.}
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emit_const_reg(A_SAR,S_L,31,hreg2);
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{If signed, hreg2=right value-1, otherwise 0.}
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emit_const_reg(A_AND,S_L,tordconstnode(right).value-1,hreg2);
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{ add to the left value }
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emit_reg_reg(A_ADD,S_L,hreg2,hreg1);
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{ do the shift }
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emit_const_reg(A_SAR,S_L,power,hreg1);
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end
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else
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begin
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{ a jump, but less operations }
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emit_reg_reg(A_TEST,S_L,hreg1,hreg1);
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objectlibrary.getjumplabel(hl);
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cg.a_jmp_flags(exprasmlist,F_NS,hl);
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if power=1 then
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emit_reg(A_INC,S_L,hreg1)
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else
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emit_const_reg(A_ADD,S_L,tordconstnode(right).value-1,hreg1);
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cg.a_label(exprasmlist,hl);
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emit_const_reg(A_SAR,S_L,power,hreg1);
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end
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end
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else
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emit_const_reg(A_SHR,S_L,power,hreg1);
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location.register:=hreg1;
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end
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else
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begin
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cg.getcpuregister(exprasmlist,NR_EAX);
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emit_reg_reg(A_MOV,S_L,hreg1,NR_EAX);
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cg.getcpuregister(exprasmlist,NR_EDX);
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{Sign extension depends on the left type.}
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if torddef(left.resulttype.def).typ=u32bit then
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emit_reg_reg(A_XOR,S_L,NR_EDX,NR_EDX)
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else
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emit_none(A_CDQ,S_NO);
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{Division depends on the right type.}
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if Torddef(right.resulttype.def).typ=u32bit then
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op:=A_DIV
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else
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op:=A_IDIV;
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if right.location.loc in [LOC_REFERENCE,LOC_CREFERENCE] then
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emit_ref(op,S_L,right.location.reference)
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else if right.location.loc in [LOC_REGISTER,LOC_CREGISTER] then
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emit_reg(op,S_L,right.location.register)
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else
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begin
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hreg1:=cg.getintregister(exprasmlist,right.location.size);
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cg.a_load_loc_reg(exprasmlist,OS_32,right.location,hreg1);
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emit_reg(op,S_L,hreg1);
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end;
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{Copy the result into a new register. Release EAX & EDX.}
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cg.ungetcpuregister(exprasmlist,NR_EDX);
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cg.ungetcpuregister(exprasmlist,NR_EAX);
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location.register:=cg.getintregister(exprasmlist,OS_INT);
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if nodetype=divn then
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cg.a_load_reg_reg(exprasmlist,OS_INT,OS_INT,NR_EAX,location.register)
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else
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cg.a_load_reg_reg(exprasmlist,OS_INT,OS_INT,NR_EDX,location.register);
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end;
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end;
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{*****************************************************************************
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TI386SHLRSHRNODE
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*****************************************************************************}
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function ti386shlshrnode.first_shlshr64bitint: tnode;
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begin
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result := nil;
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end;
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procedure ti386shlshrnode.pass_2;
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var hreg64hi,hreg64lo:Tregister;
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op:Tasmop;
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v : TConstExprInt;
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l1,l2,l3:Tasmlabel;
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begin
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secondpass(left);
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secondpass(right);
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{ determine operator }
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if nodetype=shln then
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op:=A_SHL
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else
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op:=A_SHR;
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if is_64bitint(left.resulttype.def) then
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begin
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location_reset(location,LOC_REGISTER,OS_64);
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{ load left operator in a register }
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location_force_reg(exprasmlist,left.location,OS_64,false);
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hreg64hi:=left.location.register64.reghi;
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hreg64lo:=left.location.register64.reglo;
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{ shifting by a constant directly coded: }
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if (right.nodetype=ordconstn) then
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begin
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v:=Tordconstnode(right).value and 63;
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if v>31 then
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begin
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if nodetype=shln then
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begin
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emit_reg_reg(A_XOR,S_L,hreg64hi,hreg64hi);
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if ((v and 31) <> 0) then
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emit_const_reg(A_SHL,S_L,v and 31,hreg64lo);
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end
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else
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begin
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emit_reg_reg(A_XOR,S_L,hreg64lo,hreg64lo);
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if ((v and 31) <> 0) then
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emit_const_reg(A_SHR,S_L,v and 31,hreg64hi);
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end;
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location.register64.reghi:=hreg64lo;
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location.register64.reglo:=hreg64hi;
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end
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else
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begin
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if nodetype=shln then
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begin
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emit_const_reg_reg(A_SHLD,S_L,v and 31,hreg64lo,hreg64hi);
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emit_const_reg(A_SHL,S_L,v and 31,hreg64lo);
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end
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else
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begin
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emit_const_reg_reg(A_SHRD,S_L,v and 31,hreg64hi,hreg64lo);
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emit_const_reg(A_SHR,S_L,v and 31,hreg64hi);
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end;
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location.register64.reglo:=hreg64lo;
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location.register64.reghi:=hreg64hi;
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end;
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end
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else
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begin
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{ load right operators in a register }
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cg.getcpuregister(exprasmlist,NR_ECX);
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cg.a_load_loc_reg(exprasmlist,OS_32,right.location,NR_ECX);
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{ left operator is already in a register }
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{ hence are both in a register }
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{ is it in the case ECX ? }
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{ the damned shift instructions work only til a count of 32 }
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{ so we've to do some tricks here }
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objectlibrary.getjumplabel(l1);
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objectlibrary.getjumplabel(l2);
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objectlibrary.getjumplabel(l3);
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emit_const_reg(A_CMP,S_L,64,NR_ECX);
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cg.a_jmp_flags(exprasmlist,F_L,l1);
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emit_reg_reg(A_XOR,S_L,hreg64lo,hreg64lo);
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emit_reg_reg(A_XOR,S_L,hreg64hi,hreg64hi);
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cg.a_jmp_always(exprasmlist,l3);
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cg.a_label(exprasmlist,l1);
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emit_const_reg(A_CMP,S_L,32,NR_ECX);
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cg.a_jmp_flags(exprasmlist,F_L,l2);
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emit_const_reg(A_SUB,S_L,32,NR_ECX);
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if nodetype=shln then
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begin
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emit_reg_reg(A_SHL,S_L,NR_CL,hreg64lo);
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emit_reg_reg(A_MOV,S_L,hreg64lo,hreg64hi);
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emit_reg_reg(A_XOR,S_L,hreg64lo,hreg64lo);
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cg.a_jmp_always(exprasmlist,l3);
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cg.a_label(exprasmlist,l2);
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emit_reg_reg_reg(A_SHLD,S_L,NR_CL,hreg64lo,hreg64hi);
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emit_reg_reg(A_SHL,S_L,NR_CL,hreg64lo);
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end
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else
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begin
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emit_reg_reg(A_SHR,S_L,NR_CL,hreg64hi);
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emit_reg_reg(A_MOV,S_L,hreg64hi,hreg64lo);
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emit_reg_reg(A_XOR,S_L,hreg64hi,hreg64hi);
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cg.a_jmp_always(exprasmlist,l3);
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cg.a_label(exprasmlist,l2);
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emit_reg_reg_reg(A_SHRD,S_L,NR_CL,hreg64hi,hreg64lo);
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emit_reg_reg(A_SHR,S_L,NR_CL,hreg64hi);
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end;
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cg.a_label(exprasmlist,l3);
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cg.ungetcpuregister(exprasmlist,NR_ECX);
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location.register64.reglo:=hreg64lo;
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location.register64.reghi:=hreg64hi;
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end;
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end
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else
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begin
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{ load left operators in a register }
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location_copy(location,left.location);
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location_force_reg(exprasmlist,location,OS_INT,false);
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{ shifting by a constant directly coded: }
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if (right.nodetype=ordconstn) then
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{ l shl 32 should 0 imho, but neither TP nor Delphi do it in this way (FK)}
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emit_const_reg(op,S_L,tordconstnode(right).value and 31,location.register)
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else
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begin
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{ load right operators in a ECX }
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cg.getcpuregister(exprasmlist,NR_ECX);
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cg.a_load_loc_reg(exprasmlist,OS_32,right.location,NR_ECX);
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{ right operand is in ECX }
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cg.ungetcpuregister(exprasmlist,NR_ECX);
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emit_reg_reg(op,S_L,NR_CL,location.register);
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end;
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end;
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end;
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begin
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cunaryminusnode:=ti386unaryminusnode;
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cmoddivnode:=ti386moddivnode;
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cshlshrnode:=ti386shlshrnode;
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cnotnode:=ti386notnode;
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end.
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