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https://gitlab.com/freepascal.org/fpc/source.git
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00cb8f5725
as well as insert_regalloc_info_all()
+ "register" allocator for the jvm target, which simply replaces every
virtual register with a temp. This is done for all register types in
one pass, so that the temps can be easily reused without worrying
about conflicts. Small optimisation: alloc/store/dealloc/load
sequences for a single reg are removed (many of these are generated
because most cg nodes return their value in a register which is then
immediately consumed by the parent)
* map addressregisters to integer registers with size R_SUBD, because
they require one stackslot (the subregister type is used by rgcpu
to determine the size of the temp it has to allocate)
git-svn-id: branches/jvmbackend@18316 -
132 lines
4.1 KiB
ObjectPascal
132 lines
4.1 KiB
ObjectPascal
{
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Copyright (c) 2010 by Jonas Maebe
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This unit implements the code generator for the Java VM
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit cgcpu;
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{$i fpcdefs.inc}
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interface
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uses
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globtype,parabase,
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cgbase,cgutils,cgobj,
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aasmbase,aasmtai,aasmdata,aasmcpu,
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cpubase,cpuinfo,
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node,symconst,SymType,symdef,
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rgcpu;
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type
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TCgJvm=class(tcg)
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public
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procedure init_register_allocators;override;
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procedure done_register_allocators;override;
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function getintregister(list:TAsmList;size:Tcgsize):Tregister;override;
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function getfpuregister(list:TAsmList;size:Tcgsize):Tregister;override;
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function getaddressregister(list:TAsmList):Tregister;override;
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procedure do_register_allocation(list:TAsmList;headertai:tai);override;
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end;
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procedure create_codegen;
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implementation
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uses
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globals,verbose,systems,cutils,
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paramgr,fmodule,
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tgobj,
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procinfo,cpupi;
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{****************************************************************************
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Assembler code
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****************************************************************************}
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procedure tcgjvm.init_register_allocators;
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begin
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inherited init_register_allocators;
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{$ifndef cpu64bitaddr}
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rg[R_INTREGISTER]:=Trgcpu.create(R_INTREGISTER,R_SUBD,
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[RS_R0],first_int_imreg,[]);
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{$else not cpu64bitaddr}
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rg[R_INTREGISTER]:=Trgcpu.create(R_INTREGISTER,R_SUBQ,
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[RS_R0],first_int_imreg,[]);
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{$endif not cpu64bitaddr}
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rg[R_FPUREGISTER]:=trgcpu.create(R_FPUREGISTER,R_SUBFS,
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[RS_R0],first_fpu_imreg,[]);
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rg[R_MMREGISTER]:=trgcpu.create(R_MMREGISTER,R_SUBNONE,
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[RS_R0],first_mm_imreg,[]);
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end;
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procedure tcgjvm.done_register_allocators;
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begin
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rg[R_INTREGISTER].free;
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rg[R_FPUREGISTER].free;
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rg[R_MMREGISTER].free;
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inherited done_register_allocators;
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end;
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function tcgjvm.getintregister(list:TAsmList;size:Tcgsize):Tregister;
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begin
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if not(size in [OS_64,OS_S64]) then
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result:=rg[R_INTREGISTER].getregister(list,R_SUBD)
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else
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result:=rg[R_INTREGISTER].getregister(list,R_SUBQ);
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end;
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function tcgjvm.getfpuregister(list:TAsmList;size:Tcgsize):Tregister;
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begin
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if size=OS_F64 then
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result:=rg[R_FPUREGISTER].getregister(list,R_SUBFD)
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else
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result:=rg[R_FPUREGISTER].getregister(list,R_SUBFS);
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end;
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function tcgjvm.getaddressregister(list:TAsmList):Tregister;
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begin
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{ avoid problems in the compiler where int and addr registers are
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mixed for now; we currently don't have to differentiate between the
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two as far as the jvm backend is concerned }
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result:=rg[R_INTREGISTER].getregister(list,R_SUBD)
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end;
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procedure tcgjvm.do_register_allocation(list:TAsmList;headertai:tai);
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var
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rt : tregistertype;
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begin
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{ We only run the "register allocation" once for an arbitrary allocator,
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which will perform the register->temp mapping for all register types.
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This allows us to easily reuse temps. }
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trgcpu(rg[R_INTREGISTER]).do_all_register_allocation(list,headertai);
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end;
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procedure create_codegen;
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begin
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cg:=tcgjvm.Create;
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end;
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end.
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