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00cb8f5725
as well as insert_regalloc_info_all()
+ "register" allocator for the jvm target, which simply replaces every
virtual register with a temp. This is done for all register types in
one pass, so that the temps can be easily reused without worrying
about conflicts. Small optimisation: alloc/store/dealloc/load
sequences for a single reg are removed (many of these are generated
because most cg nodes return their value in a register which is then
immediately consumed by the parent)
* map addressregisters to integer registers with size R_SUBD, because
they require one stackslot (the subregister type is used by rgcpu
to determine the size of the temp it has to allocate)
git-svn-id: branches/jvmbackend@18316 -
286 lines
9.7 KiB
ObjectPascal
286 lines
9.7 KiB
ObjectPascal
{
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Copyright (c) 2010 by Jonas Maebe
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This unit implements the JVM specific class for the register
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allocator
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************}
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unit rgcpu;
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{$i fpcdefs.inc}
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interface
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uses
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aasmbase,aasmcpu,aasmtai,aasmdata,
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cgbase,cgutils,
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cpubase,
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rgobj;
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type
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tspilltemps = array[tregistertype] of ^Tspill_temp_list;
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{ trgcpu }
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trgcpu=class(trgobj)
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protected
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class function do_spill_replace_all(list:TAsmList;instr:taicpu;const spilltemps: tspilltemps):boolean;
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class procedure remove_dummy_load_stores(list: TAsmList; headertai: tai);
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public
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{ performs the register allocation for *all* register types }
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class procedure do_all_register_allocation(list: TAsmList; headertai: tai);
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end;
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implementation
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uses
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verbose,cutils,
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globtype,globals,
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cgobj,
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tgobj;
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{ trgcpu }
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class function trgcpu.do_spill_replace_all(list:TAsmList;instr:taicpu;const spilltemps: tspilltemps):boolean;
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var
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l: longint;
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reg: tregister;
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begin
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{ jvm instructions never have more than one memory (virtual register)
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operand, so there is no danger of superregister conflicts }
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for l:=0 to instr.ops-1 do
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if instr.oper[l]^.typ=top_reg then
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begin
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reg:=instr.oper[l]^.reg;
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instr.loadref(l,spilltemps[getregtype(reg)]^[getsupreg(reg)]);
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end;
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end;
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class procedure trgcpu.remove_dummy_load_stores(list: TAsmList; headertai: tai);
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function issimpleregstore(p: tai; reg: tregister; doubleprecisionok: boolean): boolean;
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const
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simplestoressp = [a_astore,a_fstore,a_istore];
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simplestoresdp = [a_dstore,a_lstore];
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begin
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result:=
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assigned(p) and
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(p.typ=ait_instruction) and
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((taicpu(p).opcode in simplestoressp) or
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(doubleprecisionok and
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(taicpu(p).opcode in simplestoresdp))) and
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((reg=NR_NO) or
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(taicpu(p).oper[0]^.typ=top_reg) and
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(taicpu(p).oper[0]^.reg=reg));
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end;
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function issimpleregload(p: tai; reg: tregister; doubleprecisionok: boolean): boolean;
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const
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simpleloadssp = [a_aload,a_fload,a_iload];
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simpleloadsdp = [a_dload,a_lload];
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begin
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result:=
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assigned(p) and
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(p.typ=ait_instruction) and
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((taicpu(p).opcode in simpleloadssp) or
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(doubleprecisionok and
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(taicpu(p).opcode in simpleloadsdp))) and
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((reg=NR_NO) or
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(taicpu(p).oper[0]^.typ=top_reg) and
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(taicpu(p).oper[0]^.reg=reg));
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end;
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function try_remove_alloc_store_dealloc_load(var p: tai; reg: tregister): boolean;
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var
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q: tai;
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begin
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result:=false;
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{ check for:
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alloc regx
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store regx
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dealloc regx
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load regx
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and remove. We don't have to check that the load/store
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types match, because they have to for this to be
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valid JVM code }
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if issimpleregstore(tai(p.next),reg,true) and
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assigned(p.next.next) and
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(tai(p.next.next).typ=ait_regalloc) and
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(tai_regalloc(p.next.next).ratype=ra_dealloc) and
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(tai_regalloc(p.next.next).reg=reg) and
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issimpleregload(tai(p.next.next.next),reg,true) then
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begin
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{ remove the whole sequence: the allocation }
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q:=Tai(p.next);
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list.remove(p);
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p.free;
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p:=q;
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{ the store }
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q:=Tai(p.next);
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list.remove(p);
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p.free;
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p:=q;
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{ the dealloc }
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q:=Tai(p.next);
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list.remove(p);
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p.free;
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p:=q;
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{ the load }
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q:=Tai(p.next);
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list.remove(p);
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p.free;
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p:=q;
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result:=true;
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end;
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end;
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var
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p: tai;
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reg: tregister;
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removedsomething: boolean;
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begin
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repeat
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removedsomething:=false;
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p:=headertai;
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while assigned(p) do
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begin
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case p.typ of
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ait_regalloc:
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begin
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if (tai_regalloc(p).ratype=ra_alloc) then
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begin
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reg:=tai_regalloc(p).reg;
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if try_remove_alloc_store_dealloc_load(p,reg) then
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begin
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removedsomething:=true;
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continue;
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end;
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{ todo in peephole optimizer:
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alloc regx // not double precision
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store regx // not double precision
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load regy or memy
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dealloc regx
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load regx
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-> change into
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load regy or memy
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swap // can only handle single precision
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and then
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swap
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<commutative op>
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-> remove swap
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}
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end;
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end;
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end;
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p:=tai(p.next);
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end;
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until not removedsomething;
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end;
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class procedure trgcpu.do_all_register_allocation(list: TAsmList; headertai: tai);
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var
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spill_temps : tspilltemps;
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templist : TAsmList;
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intrg,
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fprg : trgcpu;
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p,q : tai;
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size : longint;
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begin
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{ Since there are no actual registers, we simply spill everything. We
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use tt_regallocator temps, which are not used by the temp allocator
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during code generation, so that we cannot accidentally overwrite
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any temporary values }
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{ get references to all register allocators }
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intrg:=trgcpu(cg.rg[R_INTREGISTER]);
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fprg:=trgcpu(cg.rg[R_FPUREGISTER]);
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{ determine the live ranges of all registers }
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intrg.insert_regalloc_info_all(list);
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fprg.insert_regalloc_info_all(list);
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{ Don't do the actual allocation when -sr is passed }
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if (cs_no_regalloc in current_settings.globalswitches) then
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exit;
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{ remove some simple useless store/load sequences }
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remove_dummy_load_stores(list,headertai);
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{ allocate room to store the virtual register -> temp mapping }
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spill_temps[R_INTREGISTER]:=allocmem(sizeof(treference)*intrg.maxreg);
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spill_temps[R_FPUREGISTER]:=allocmem(sizeof(treference)*fprg.maxreg);
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{ List to insert temp allocations into }
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templist:=TAsmList.create;
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{ allocate/replace all registers }
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p:=headertai;
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while assigned(p) do
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begin
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case p.typ of
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ait_regalloc:
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with Tai_regalloc(p) do
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begin
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case getregtype(reg) of
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R_INTREGISTER:
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if getsubreg(reg)=R_SUBD then
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size:=4
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else
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size:=8;
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R_ADDRESSREGISTER:
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size:=4;
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R_FPUREGISTER:
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if getsubreg(reg)=R_SUBFS then
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size:=4
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else
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size:=8;
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else
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internalerror(2010122912);
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end;
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case ratype of
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ra_alloc :
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tg.gettemp(templist,
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size,1,
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tt_regallocator,spill_temps[getregtype(reg)]^[getsupreg(reg)]);
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ra_dealloc :
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begin
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tg.ungettemp(templist,spill_temps[getregtype(reg)]^[getsupreg(reg)]);
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{ don't invalidate the temp reference, may still be used one instruction
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later }
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end;
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end;
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{ insert the tempallocation/free at the right place }
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list.insertlistbefore(p,templist);
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{ remove the register allocation info for the register
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(p.previous is valid because we just inserted the temp
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allocation/free before p) }
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q:=Tai(p.previous);
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list.remove(p);
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p.free;
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p:=q;
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end;
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ait_instruction:
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do_spill_replace_all(list,taicpu(p),spill_temps);
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end;
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p:=Tai(p.next);
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end;
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freemem(spill_temps[R_INTREGISTER]);
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freemem(spill_temps[R_FPUREGISTER]);
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end;
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end.
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