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625 lines
24 KiB
ObjectPascal
625 lines
24 KiB
ObjectPascal
{
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$Id$
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Copyright (c) 1998-2000 by Florian Klaempfl
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Generate PowerPC assembler for math nodes
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit nppcmat;
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{$i defines.inc}
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interface
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uses
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node,nmat;
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type
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tppcmoddivnode = class(tmoddivnode)
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procedure pass_2;override;
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end;
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tppcshlshrnode = class(tshlshrnode)
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procedure pass_2;override;
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end;
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tppcunaryminusnode = class(tunaryminusnode)
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procedure pass_2;override;
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end;
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tppcnotnode = class(tnotnode)
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procedure pass_2;override;
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end;
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implementation
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uses
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globtype,systems,
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cutils,verbose,globals,
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symconst,symdef,aasm,types,
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cgbase,cgobj,temp_gen,pass_1,pass_2,
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ncon,
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cpubase,
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cga,tgcpu,nppcutil,cgcpu,cg64f32;
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{*****************************************************************************
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TPPCMODDIVNODE
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*****************************************************************************}
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procedure tppcmoddivnode.pass_2;
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const
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{ signed overflow }
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divops: array[boolean, boolean] of tasmop =
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((A_DIVWU,A_DIVWUO),(A_DIVW,A_DIVWO));
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var
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power,
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l1, l2 : longint;
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op : tasmop;
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numerator,
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divider,
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resultreg : tregister;
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saved : boolean;
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begin
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secondpass(left);
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saved:=maybe_savetotemp(right.registers32,left,is_64bitint(left.resulttype.def));
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secondpass(right);
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if saved then
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restorefromtemp(left,is_64bitint(left.resulttype.def));
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set_location(location,left.location);
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resultreg := R_NO;
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{ put numerator in register }
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if (left.location.loc in [LOC_REFERENCE,LOC_MEM]) then
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begin
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del_reference(left.location.reference);
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numerator := getregisterint;
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{ OS_32 because everything is always converted to longint/ }
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{ cardinal in the resulttype pass (JM) }
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cg.a_load_ref_reg(expraslist,OS_32,left.location.reference,
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numerator);
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resultreg := numerator;
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end
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else
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begin
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numerator := left.location.register;
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if left.location.loc = LOC_CREGISTER then
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resultreg := getregisterint
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else
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resultreg := numerator;
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end;
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if (nodetype = divn) and
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(right.nodetype = ordconstn) and
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ispowerof2(tordconstnode(right).value,power) then
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begin
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{ From 'The PowerPC Compiler Writer's Guide": }
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{ This code uses the fact that, in the PowerPC architecture, }
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{ the shift right algebraic instructions set the Carry bit if }
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{ the source register contains a negative number and one or }
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{ more 1-bits are shifted out. Otherwise, the carry bit is }
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{ cleared. The addze instruction corrects the quotient, if }
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{ necessary, when the dividend is negative. For example, if }
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{ n = -13, (0xFFFF_FFF3), and k = 2, after executing the srawi }
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{ instruction, q = -4 (0xFFFF_FFFC) and CA = 1. After executing }
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{ the addze instruction, q = -3, the correct quotient. }
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cg.a_op_const_reg_reg(list,OP_SAR,OS_32,aword(power),numerator,resultreg);
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exprasmlist.concat(taicpu.op_reg_reg(A_ADDZE,resultreg,resultreg));
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end
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else
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begin
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{ load divider in a register if necessary }
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case right.location.loc of
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LOC_CREGISTER, LOC_REGISTER:
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divider := right.location.register;
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LOC_REFERENCE, LOC_MEM:
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begin
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divider := cg.get_scratch_reg(exprasmlist);
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cg.a_load_ref_reg(exprasmlist,OS_32,
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right.location.reference,divider);
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del_reference(right.location.reference);
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end;
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end;
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{ needs overflow checking, (-maxlongint-1) div (-1) overflows! }
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{ And on PPC, the only way to catch a div-by-0 is by checking }
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{ the overflow flag (JM) }
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op := divops[is_signed(right.resulttype.def),
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cs_check_overflow in aktlocalswitches];
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exprasmlist(taicpu.op_reg_reg_reg(op,resultreg,numerator,
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divider))
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end;
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{ free used registers }
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if right.location.loc in [LOC_REFERENCE,LOC_MEM] then
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cg.free_scratch_reg(exprasmlist,divider)
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else
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ungetregister(divider);
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if numerator <> resultreg then
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ungetregisterint(numerator);
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{ set result location }
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location.loc:=LOC_REGISTER;
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location.register:=resultreg;
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emitoverflowcheck(self);
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end;
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{*****************************************************************************
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TPPCSHLRSHRNODE
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*****************************************************************************}
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procedure tppcshlshrnode.pass_2;
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var
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resultreg, hregister1,hregister2,
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hregisterhigh,hregisterlow : tregister;
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op : topcg;
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asmop1, asmop2: tasmop;
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shiftval: aword;
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saved : boolean;
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begin
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secondpass(left);
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saved:=maybe_savetotemp(right.registers32,left,is_64bitint(left.resulttype.def));
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secondpass(right);
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if saved then
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restorefromtemp(left,is_64bitint(left.resulttype.def));
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if is_64bitint(left.resulttype.def) then
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begin
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case left.location.loc of
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LOC_REGISTER, LOC_CREGISTER:
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begin
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hregisterhigh := left.location.registerhigh;
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hregisterlow := left.location.registerlow;
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if left.location.loc = LOC_REGISTER then
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begin
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location.registerhigh := hregisterhigh;
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location.registerlow := hregisterlow
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end
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else
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begin
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location.registerhigh := getregisterint;
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location.registerlow := getregisterint;
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end;
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end;
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LOC_REFERENCE,LOC_MEM:
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begin
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{ !!!!!!!! not good, registers are release too soon this way !!!! (JM) }
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del_reference(left.location.reference);
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hregisterhigh := getregisterint;
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location.registerhigh := hregisterhigh;
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hregisterlow := getregisterint;
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location.registerlow := hregisterlow;
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tcg64f32(cg).a_load64_ref_reg(list,left.location.reference,
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hregisterlow,hregisterhigh);
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end;
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end;
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if (right.nodetype = ordconstn) then
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begin
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if tordconstnode(right).value > 31 then
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begin
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if nodetype = shln then
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begin
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if (value and 31) <> 0 then
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cg.a_op_const_reg_reg(exprasmlist,OP_SHL,OS_32,value and 31,
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hregisterlow,location.registerhigh)
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cg.a_load_const_reg(exprasmlist,OS_32,0,location.registerlow);
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end
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else
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begin
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if (value and 31) <> 0 then
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cg.a_op_const_reg_reg(exprasmlist,OP_SHR,OS_32,value and 31,
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hregisterhigh,location.registerlow);
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cg.a_load_const_reg(exprasmlist,OS_32,0,location.registerhigh);
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end;
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end
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else
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begin
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shiftval := aword(tordconstnode(right).value;
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if nodetype = shln then
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begin
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exprasmlist.concat(taicpu.op_reg_reg_const_const_const(
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A_RLWINM,location.registerhigh,hregisterhigh,shiftval,
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0,31-shiftval));
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exprasmlist.concat(taicpu.op_reg_reg_const_const_const(
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A_RLWIMI,location.registerhigh,hregisterlow,shiftval,
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32-shiftval,31));
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exprasmlist.concat(taicpu.op_reg_reg_const_const_const(
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A_RLWINM,location.registerlow,hregisterlow,shiftval,
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0,31-shiftval));
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end
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else
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begin
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exprasmlist.concat(taicpu.op_reg_reg_const_const_const(
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A_RLWINM,location.registerlow,hregisterlow,32-shiftval,
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shiftval,31));
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exprasmlist.concat(taicpu.op_reg_reg_const_const_const(
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A_RLWIMI,location.registerlow,hregisterhigh,32-shiftval,
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0,shiftval-1));
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exprasmlist.concat(taicpu.op_reg_reg_const_const_const(
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A_RLWINM,location.registerhigh,hregisterhigh,32-shiftval,
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shiftval,31));
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end;
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end;
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end
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else
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{ no constant shiftcount }
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begin
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case right.location.loc of
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LOC_REGISTER,LOC_CREGISTER:
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begin
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hregister1 := right.location.register;
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end;
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LOC_REFERENCE,LOC_MEM:
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begin
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hregister1 := get_scratch_reg(exprasmlist);
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cg.a_load_ref_reg(exprasmlist,OS_S32,
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right.location.reference,hregister1);
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end;
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end;
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if nodetype = shln then
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begin
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asmop1 := A_SLW;
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asmop2 := A_SRW;
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end
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else
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begin
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asmop1 := A_SRW;
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asmop2 := A_SLW;
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resultreg := location.registerhigh;
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location.registerhigh := location.registerlow;
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location.registerlow := resultreg;
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end;
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getexplicitregisterint(R_0);
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exprasmlist.concat(taicpu.op_reg_reg_const(A_SUBFIC,
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R_0,hregister1,32));
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exprasmlist.concat(taicpu.op_reg_reg_reg(asmop1,
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location.registerhigh,hregisterhigh,hregister1));
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exprasmlist.concat(taicpu.op_reg_reg_reg(asmop2,
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R_0,hregisterlow,R_0));
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exprasmlist.concat(taicpu.op_reg_reg_reg(A_OR,
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location.registerhigh,location.registerhigh,R_0));
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exprasmlist.concat(taicpu.op_reg_reg_const(A_SUBI,
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R_0,hregister1,32));
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exprasmlist.concat(taicpu.op_reg_reg_reg(asmop1,
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R_0,hregisterlow,R_0));
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exprasmlist.concat(taicpu.op_reg_reg_reg(A_OR,
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location.registerhigh,location.registerhigh,R_0));
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exprasmlist.concat(taicpu.op_reg_reg_reg(asmop1,
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location.registerlow,hregisterlow,hregister1));
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ungetregister(R_0);
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if right.location.loc in [LOC_MEM,LOC_REFERENCE] then
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free_scratch_reg(exprasmlist,hregister1)
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else
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ungetregister(hregister1);
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end
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end
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else
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begin
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{ load left operators in a register }
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if (left.location.loc in [LOC_REFERENCE,LOC_MEM]) then
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begin
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del_reference(left.location.reference);
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hregister1 := getregisterint;
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{ OS_32 because everything is always converted to longint/ }
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{ cardinal in the resulttype pass (JM) }
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cg.a_load_ref_reg(expraslist,OS_32,left.location.reference,
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hregister1);
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resultreg := hregister1;
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end
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else
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begin
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hregister1 := left.location.register;
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if left.location.loc = LOC_CREGISTER then
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resultreg := getregisterint
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else
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resultreg := hregister1;
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end;
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{ determine operator }
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if nodetype=shln then
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op:=OP_SHL
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else
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op:=OP_SHR;
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{ shifting by a constant directly coded: }
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if (right.nodetype=ordconstn) then
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cg.a_op_reg_reg_const(exprasmlist,op,OS_32,resultreg,
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hregister1,tordconstnode(right).value and 31)
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else
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begin
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{ load shift count in a register if necessary }
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case right.location.loc of
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LOC_CREGISTER, LOC_REGISTER:
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hregister2 := right.location.register;
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LOC_REFERENCE, LOC_MEM:
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begin
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hregister2 := cg.get_scratch_reg(exprasmlist);
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cg.a_load_ref_reg(exprasmlist,OS_32,
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right.location.reference,hregister2);
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del_reference(right.location.reference);
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end;
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end;
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tcgppc(cg).a_op_reg_reg_reg(exprasmlist,op,hregister1,
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hregister2,resultreg);
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if right.location.loc in [LOC_REFERENCE,LOC_MEM] then
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cg.free_scratch_reg(exprasmlist,hregister2)
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else
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ungetregister(hregister2);
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end;
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{ set result location }
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location.loc:=LOC_REGISTER;
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location.register:=resultreg;
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end;
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end;
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{*****************************************************************************
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TPPCUNARYMINUSNODE
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*****************************************************************************}
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procedure tppcunaryminusnode.pass_2;
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var
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src1, src2, tmp: tregister;
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op: tasmop;
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begin
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secondpass(left);
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if is_64bitint(left.resulttype.def) then
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begin
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clear_location(location);
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location.loc:=LOC_REGISTER;
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case left.location.loc of
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LOC_REGISTER, LOC_CREGISTER :
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begin
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src1 := left.location.registerlow;
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src2 := left.location.registerhigh;
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if left.location.loc = LOC_REGISTER then
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begin
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location.registerlow:=src1;
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location.registerhigh:=src2;
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end
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else
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begin
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location.registerlow := getregisterint;
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location.registerhigh := getregisterint;
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end;
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end;
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LOC_REFERENCE,LOC_MEM :
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begin
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del_reference(left.location.reference);
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location.registerlow:=getregisterint;
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src1 := location.registerlow;
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location.registerhigh:=getregisterint;
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src2 := location.registerhigh;
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tcg64f32(cg).a_load64_ref_reg(exprasmlist,left.location.reference,
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location.registerlow,
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location.registerhigh);
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end;
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end;
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exprasmlist.concat(taicpu.op_reg_reg(A_NEG,location.registerlow,
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src1));
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cg.a_op_reg_reg(OP_NOT,OS_32,src2,location.registerhigh);
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tmp := cg.get_scratch_reg(exprasmlist);
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tcgppc(cg).a_op_const_reg_reg(OP_SAR,31,location.registerlow,tmp);
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if not(cs_check_overflow in aktlocalswitches) then
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cg.a_op_reg_reg(OP_ADD,OS_32,location.registerhigh,tmp)
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else
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exprasmlist.concat(taicpu.op_reg_reg_reg(A_ADDO,tmp,
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location.registerhigh,tmp));
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cg.free_scratch_reg(exprasmlist,tmp);
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end
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else
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begin
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location.loc:=LOC_REGISTER;
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case left.location.loc of
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LOC_FPU, LOC_REGISTER:
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begin
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src1 := left.location.register;
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location.register := src1;
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end;
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LOC_CFPUREGISTER, LOC_CREGISTER:
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begin
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src1 := left.location.register;
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if left.location.loc = LOC_CREGISTER then
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location.register := getregisterint
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else
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location.register := getregisterfpu;
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end;
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LOC_REFERENCE,LOC_MEM:
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begin
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del_reference(left.location.reference);
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if (left.resulttype.def.deftype=floatdef) then
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begin
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src1 := getregisterfpu;
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location.register := src1;
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floatload(tfloatdef(left.resulttype.def).typ,
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left.location.reference,src1);
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end
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else
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begin
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src1 := getregisterint;
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location.register:= src1;
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cg.a_load_ref_reg(exprasmlist,OS_32,
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left.location.reference,src1);
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end;
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end;
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end;
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{ choose appropriate operand }
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if left.resulttype.def <> floatdef then
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if not(cs_check_overflow in aktlocalswitches) then
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op := A_NEG
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else
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op := A_NEGO
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else
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op := A_FNEG;
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{ emit operation }
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eprasmlist.concat(taicpu.op_reg_reg(op,location.register,src1));
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end;
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{ Here was a problem... }
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{ Operand to be negated always }
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{ seems to be converted to signed }
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{ 32-bit before doing neg!! }
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{ So this is useless... }
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{ that's not true: -2^31 gives an overflow error if it is negated (FK) }
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emitoverflowcheck(self);
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end;
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{*****************************************************************************
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TPPCNOTNODE
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*****************************************************************************}
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procedure tppcnotnode.pass_2;
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var
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hl : tasmlabel;
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regl, regh: tregister;
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begin
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if is_boolean(resulttype.def) then
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begin
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{ the second pass could change the location of left }
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{ if it is a register variable, so we've to do }
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{ this before the case statement }
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if left.location.loc in [LOC_REFERENCE,LOC_MEM,
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LOC_FLAGS,LOC_REGISTER,LOC_CREGISTER] then
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secondpass(left);
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case left.location.loc of
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LOC_JUMP :
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begin
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hl:=truelabel;
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truelabel:=falselabel;
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falselabel:=hl;
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secondpass(left);
|
|
maketojumpbool(left,lr_load_regvars);
|
|
hl:=truelabel;
|
|
truelabel:=falselabel;
|
|
falselabel:=hl;
|
|
end;
|
|
LOC_FLAGS :
|
|
location.resflags:=inverse_flags(left.location.resflags);
|
|
LOC_REGISTER, LOC_CREGISTER, LOC_REFERENCE, LOC_MEM :
|
|
begin
|
|
if left.location.loc in [LOC_REGISTER,LOC_CREGISTER] then
|
|
regl := left.location.register
|
|
else
|
|
begin
|
|
regl := getregisterint;
|
|
cg.a_load_ref_reg(exprasmlist,def_cgsize(left.resulttype.def),
|
|
left.location.reference,regl);
|
|
end;
|
|
location.loc:=LOC_FLAGS;
|
|
location.resflags.cr:=0;
|
|
location.resflags.flag:=F_EQ;
|
|
exprasmlist.concat(taicpu.op_reg_const(A_CMPWI,regl,0));
|
|
ungetregister(regl);
|
|
end;
|
|
end;
|
|
end
|
|
else if is_64bitint(left.resulttype.def) then
|
|
begin
|
|
secondpass(left);
|
|
clear_location(location);
|
|
location.loc:=LOC_REGISTER;
|
|
{ make sure left is in a register and set the dest register }
|
|
case left.location.loc of
|
|
LOC_REFERENCE, LOC_MEM, LOC_CREGISTER:
|
|
begin
|
|
location.registerlow := getregisterint;
|
|
location.registerhigh := getregisterint;
|
|
if left.location.loc <> LOC_CREGISTER then
|
|
begin
|
|
tcg64f32(cg).a_load64_ref_reg(exprasmlist,
|
|
left.location.reference,location.registerlow,
|
|
location.registerhigh);
|
|
regl := location.registerlow;
|
|
regh := location.registerhigh;
|
|
end
|
|
else
|
|
begin
|
|
regl := left.location.registerlow;
|
|
regh := left.location.registerhigh;
|
|
end;
|
|
end;
|
|
LOC_REGISTER:
|
|
begin
|
|
regl := left.location.registerlow;
|
|
location.registerlow := regl;
|
|
regh := left.location.registerhigh;
|
|
location.registerhigh := regh;
|
|
end;
|
|
end;
|
|
{ perform the NOT operation }
|
|
exprasmlist.concat(taicpu.op_reg_reg(A_NOT,location.registerhigh,
|
|
regh);
|
|
exprasmlist.concat(taicpu.op_reg_reg(A_NOT,location.registerlow,
|
|
regl);
|
|
end
|
|
else
|
|
begin
|
|
secondpass(left);
|
|
clear_location(location);
|
|
location.loc:=LOC_REGISTER;
|
|
{ make sure left is in a register and set the dest register }
|
|
case left.location.loc of
|
|
LOC_REFERENCE, LOC_MEM, LOC_CREGISTER:
|
|
begin
|
|
location.register := getregisterint;
|
|
if left.location.loc <> LOC_CREGISTER then
|
|
begin
|
|
cg.a_load_ref_reg(exprasmlist,left.location.reference,
|
|
location.register);
|
|
regl := location.register;
|
|
end
|
|
else
|
|
regl := left.location.register;
|
|
end;
|
|
LOC_REGISTER:
|
|
regl := left.location.register;
|
|
end;
|
|
{ perform the NOT operation }
|
|
exprasmlist.concat(taicpu.op_reg_reg(A_NOT,location.register,
|
|
regl);
|
|
{ release the source reg if it wasn't reused }
|
|
if regl <> location.register then
|
|
ungetregisterint(regl);
|
|
end;
|
|
end;
|
|
|
|
begin
|
|
cmoddivnode:=tppcmoddivnode;
|
|
cshlshrnode:=tppcshlshrnode;
|
|
cunaryminusnode:=tppcunaryminusnode;
|
|
cnotnode:=tppcnotnode;
|
|
end.
|
|
{
|
|
$Log$
|
|
Revision 1.2 2002-01-03 14:57:52 jonas
|
|
* completed (not compilale yet though)
|
|
|
|
Revision 1.1 2001/12/29 15:28:58 jonas
|
|
* powerpc/cgcpu.pas compiles :)
|
|
* several powerpc-related fixes
|
|
* cpuasm unit is now based on common tainst unit
|
|
+ nppcmat unit for powerpc (almost complete)
|
|
|
|
|
|
}
|