J. Gareth "Curious Kit" Moreton 83c9b17ec5 * x86: Fixed oversight in LeaLea2LeaLea optimisations where bad code is ... generated if the intermediate register appears in the first reference		2025-02-27 21:25:23 +00:00
..
aasmcpu.pas
agx86att.pas
agx86int.pas
agx86nsm.pas	+ zen5 architecture for completeness	2024-12-07 22:23:35 +01:00
aoptx86.pas	* x86: Fixed oversight in LeaLea2LeaLea optimisations where bad code is	2025-02-27 21:25:23 +00:00
cga.pas
cgx86.pas	+ x86: proper flag (de)alloc in a_bit_scan	2025-02-15 22:19:05 +01:00
cpubase.pas
cx86innr.inc
cx86mminnr.inc
hlcgx86.pas
itcpugas.pas
itx86int.pas
ni86mem.pas
nx86add.pas
nx86bas.pas
nx86cal.pas
nx86cnv.pas	* change some getglobaldatalabel into getlocaldatalabel to simplify code if pic is used	2025-01-13 22:34:31 +01:00
nx86con.pas
nx86inl.pas
nx86ld.pas
nx86mat.pas	* change some getglobaldatalabel into getlocaldatalabel to simplify code if pic is used	2025-01-13 22:34:31 +01:00
nx86mem.pas
nx86set.pas	* change some getglobaldatalabel into getlocaldatalabel to simplify code if pic is used	2025-01-13 22:34:31 +01:00
rax86.pas
rax86att.pas
rax86int.pas
rgx86.pas
symi86.pas
symx86.pas
x86ins.dat	cmpxchg16b instruction uses no size suffix in ATT syntax	2024-12-06 14:45:44 +01:00
x86intr.dat
x86mmfirst.inc
x86mmsecond.inc
x86mmtype.inc
x86reg.dat