mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-04-27 12:53:42 +02:00
d1538ab023
+ RTL support:
o VFP exceptions are disabled by default on Darwin,
because they cause kernel panics on iPhoneOS 2.2.1 at least
o all denormals are truncated to 0 on Darwin, because disabling
that also causes kernel panics on iPhoneOS 2.2.1 (probably
because otherwise denormals can also cause exceptions)
* set softfloat rounding mode correctly for non-wince/darwin/vfp
targets
+ compiler support: only half the number of single precision
registers is available due to limitations of the register
allocator
+ added a number of comments about why the stackframe on ARM is
set up the way it is by the compiler
+ added regtype and subregtype info to regsets, because they're
also used for VFP registers (+ support in assembler reader)
+ various generic support routines for dealing with floating point
values located in integer registers that have to be transferred to
mm registers (needed for VFP)
* renamed use_sse() to use_vectorfpu() and also use it for
ARM/vfp support
o only superficially tested for Linux (compiler compiled with -Cpvfpv6
-Cfvfpv2 works on a Cortex-A8, no testsuite run performed -- at least
the fpu exception handler still needs to be implemented), Darwin has
been tested more thoroughly
+ added ARMv6 cpu type and made it default for Darwin/ARM
+ ARMv6+ implementations of atomic operations using ldrex/strex
* don't use r9 on Darwin/ARM, as it's reserved under certain
circumstances (don't know yet which ones)
* changed C-test object files for ARM/Darwin to ARMv6 versions
* check in assembler reader that regsets are not empty, because
instructions with a regset operand have undefined behaviour in that
case
* fixed resultdef of tarmtypeconvnode.first_int_to_real in case of
int64->single type conversion
* fixed constant pool locations in case 64 bit constants are generated,
and/or when vfp instructions with limited reach are present
WARNING: when using VFP on an ARMv6 or later cpu, you *must* compile all
code with -Cparmv6 (or higher), or you will get crashes. The reason is
that storing/restoring multiple VFP registers must happen using
different instructions on pre/post-ARMv6.
git-svn-id: trunk@14317 -
91 lines
2.8 KiB
ObjectPascal
91 lines
2.8 KiB
ObjectPascal
{
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Copyright (c) 1998-2002 by Florian Klaempfl
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Generate i386 assembler for constants
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit nx86con;
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{$i fpcdefs.inc}
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interface
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uses
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node,ncon,ncgcon;
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type
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tx86realconstnode = class(tcgrealconstnode)
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function pass_1 : tnode;override;
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procedure pass_generate_code;override;
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end;
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implementation
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uses
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systems,globals,
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symdef,
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defutil,
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cpubase,
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cga,cgx86,cgobj,cgbase,cgutils;
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{*****************************************************************************
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TI386REALCONSTNODE
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*****************************************************************************}
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function tx86realconstnode.pass_1 : tnode;
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begin
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result:=nil;
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if is_number_float(value_real) and not(use_vectorfpu(resultdef)) and (value_real=1.0) or (value_real=0.0) then
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expectloc:=LOC_FPUREGISTER
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else
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expectloc:=LOC_CREFERENCE;
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end;
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procedure tx86realconstnode.pass_generate_code;
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begin
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if is_number_float(value_real) then
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begin
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if (value_real=1.0) and not(use_vectorfpu(resultdef)) then
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begin
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emit_none(A_FLD1,S_NO);
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location_reset(location,LOC_FPUREGISTER,def_cgsize(resultdef));
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location.register:=NR_ST;
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tcgx86(cg).inc_fpu_stack;
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end
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else if (value_real=0.0) and not(use_vectorfpu(resultdef)) then
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begin
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emit_none(A_FLDZ,S_NO);
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if (get_real_sign(value_real) < 0) then
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emit_none(A_FCHS,S_NO);
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location_reset(location,LOC_FPUREGISTER,def_cgsize(resultdef));
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location.register:=NR_ST;
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tcgx86(cg).inc_fpu_stack;
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end
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else
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inherited pass_generate_code;
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end
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else
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inherited pass_generate_code;
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end;
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begin
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crealconstnode:=tx86realconstnode;
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end.
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