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81 lines
2.1 KiB
ObjectPascal
81 lines
2.1 KiB
ObjectPascal
{
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System register definitions and utility code for Cortex-M0
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Created by Jeppe Johansen 2012 - jeppe@j-software.dk
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Modified for M0 by Michael Ring 2013 - mail@michael-ring.org
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}
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{$IFNDEF FPC_DOTTEDUNITS}
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unit cortexm0;
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{$ENDIF FPC_DOTTEDUNITS}
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interface
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{$PACKRECORDS 2}
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const
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SCS_BASE = $E000E000;
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SysTick_BASE = SCS_BASE+$0010;
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NVIC_BASE = SCS_BASE+$0100;
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SCB_BASE = SCS_BASE+$0D00;
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DWT_BASE = $E0001000;
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FP_BASE = $E0002000;
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ITM_BASE = $E0000000;
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TPIU_BASE = $E0040000;
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ETM_BASE = $E0041000;
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type
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TNVICRegisters = record
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ISER : dword;
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RESERVED0 : array[0..30] of dword;
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ICER : dword;
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RSERVED1 : array[0..30] of dword;
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ISPR : dword;
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RESERVED2 : array[0..30] of dword;
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ICPR : dword;
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RESERVED3 : array[0..30] of dword;
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RESERVED4 : array[0..63] of dword;
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IPR : array[0..7] of dword;
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end;
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TSCBRegisters = record
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CPUID, {!< CPU ID Base Register }
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ICSR, {!< Interrupt Control State Register }
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RESERVED0,
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AIRCR, {!< Application Interrupt / Reset Control Register }
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SCR, {!< System Control Register }
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CCR: dword; {!< Configuration Control Register }
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RESERVED1 : dword;
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SHP: array[0..1] of dword; {!< System Handlers Priority Registers (4-7, 8-11, 12-15) }
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end;
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TSysTickRegisters = record
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Ctrl,
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Load,
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Val,
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Calib: dword;
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end;
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TCoreDebugRegisters = record
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DHCSR,
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DCRSR,
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DCRDR,
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DEMCR: longword;
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end;
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var
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// System Control
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InterruptControlType: longword absolute (SCS_BASE+$0004);
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SCB: TSCBRegisters absolute (SCS_BASE+$0D00);
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SysTick: TSysTickRegisters absolute (SCS_BASE+$0010);
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NVIC: TNVICRegisters absolute (SCS_BASE+$0100);
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SoftwareTriggerInterrupt: longword absolute (SCS_BASE+$0000);
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// Core Debug
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CoreDebug: TCoreDebugRegisters absolute (SCS_BASE+$0DF0);
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implementation
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end.
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