mirror of
https://gitlab.com/freepascal.org/fpc/source.git
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a25ebbba3e
o separate information for reading and writing, because e.g. in a
try-block, only the writes to local variables and parameters are
volatile (they have to be committed immediately in case the next
instruction causes an exception)
o for now, only references to absolute memory addresses are marked
as volatile
o the volatily information is (should be) properly maintained throughout
all code generators for all archictures with this patch
o no optimizers or other compiler infrastructure uses the volatility
information yet
o this functionality is not (yet) exposed at the language level, it
is only for internal code generator use right now
git-svn-id: trunk@34996 -
600 lines
22 KiB
ObjectPascal
600 lines
22 KiB
ObjectPascal
{
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Copyright (c) 2000-2002 by Florian Klaempfl
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Code generation for add nodes on the i386
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit n386add;
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{$i fpcdefs.inc}
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interface
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uses
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node,nadd,cpubase,nx86add;
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type
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ti386addnode = class(tx86addnode)
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function use_generic_mul32to64: boolean; override;
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function use_generic_mul64bit: boolean; override;
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procedure second_addordinal; override;
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procedure second_add64bit;override;
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procedure second_cmp64bit;override;
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procedure second_mul(unsigned: boolean);
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procedure second_mul64bit;
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protected
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procedure set_mul_result_location;
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end;
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implementation
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uses
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globtype,systems,
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cutils,verbose,globals,
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symconst,symdef,paramgr,defutil,
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aasmbase,aasmtai,aasmdata,aasmcpu,
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cgbase,procinfo,
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ncon,nset,cgutils,tgobj,
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cga,ncgutil,cgobj,cg64f32,cgx86,
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hlcgobj;
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{*****************************************************************************
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use_generic_mul32to64
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*****************************************************************************}
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function ti386addnode.use_generic_mul32to64: boolean;
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begin
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result := False;
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end;
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function ti386addnode.use_generic_mul64bit: boolean;
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begin
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result:=(cs_check_overflow in current_settings.localswitches) or
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(cs_opt_size in current_settings.optimizerswitches);
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end;
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{ handles all unsigned multiplications, and 32->64 bit signed ones.
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32bit-only signed mul is handled by generic codegen }
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procedure ti386addnode.second_addordinal;
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var
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unsigned: boolean;
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begin
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unsigned:=not(is_signed(left.resultdef)) or
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not(is_signed(right.resultdef));
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{ use IMUL instead of MUL in case overflow checking is off and we're
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doing a 32->32-bit multiplication }
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if not (cs_check_overflow in current_settings.localswitches) and
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not is_64bit(resultdef) then
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unsigned:=false;
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if (nodetype=muln) and (unsigned or is_64bit(resultdef)) then
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second_mul(unsigned)
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else
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inherited second_addordinal;
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end;
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{*****************************************************************************
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Add64bit
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*****************************************************************************}
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procedure ti386addnode.second_add64bit;
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var
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op : TOpCG;
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op1,op2 : TAsmOp;
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opsize : TOpSize;
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hregister,
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hregister2 : tregister;
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hl4 : tasmlabel;
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mboverflow,
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unsigned:boolean;
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r:Tregister;
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begin
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pass_left_right;
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op1:=A_NONE;
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op2:=A_NONE;
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mboverflow:=false;
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opsize:=S_L;
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unsigned:=((left.resultdef.typ=orddef) and
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(torddef(left.resultdef).ordtype=u64bit)) or
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((right.resultdef.typ=orddef) and
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(torddef(right.resultdef).ordtype=u64bit));
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case nodetype of
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addn :
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begin
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op:=OP_ADD;
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mboverflow:=true;
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end;
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subn :
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begin
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op:=OP_SUB;
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op1:=A_SUB;
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op2:=A_SBB;
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mboverflow:=true;
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end;
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xorn:
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op:=OP_XOR;
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orn:
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op:=OP_OR;
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andn:
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op:=OP_AND;
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muln:
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begin
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second_mul64bit;
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exit;
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end
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else
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begin
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{ everything should be handled in pass_1 (JM) }
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internalerror(200109051);
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end;
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end;
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{ left and right no register? }
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{ then one must be demanded }
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if (left.location.loc<>LOC_REGISTER) then
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begin
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if (right.location.loc<>LOC_REGISTER) then
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begin
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hregister:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
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hregister2:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
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cg64.a_load64_loc_reg(current_asmdata.CurrAsmList,left.location,joinreg64(hregister,hregister2));
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location_reset(left.location,LOC_REGISTER,left.location.size);
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left.location.register64.reglo:=hregister;
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left.location.register64.reghi:=hregister2;
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end
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else
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begin
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location_swap(left.location,right.location);
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toggleflag(nf_swapped);
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end;
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end;
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{ at this point, left.location.loc should be LOC_REGISTER }
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if right.location.loc=LOC_REGISTER then
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begin
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{ when swapped another result register }
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if (nodetype=subn) and (nf_swapped in flags) then
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begin
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cg64.a_op64_reg_reg(current_asmdata.CurrAsmList,op,location.size,
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left.location.register64,
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right.location.register64);
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location_swap(left.location,right.location);
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toggleflag(nf_swapped);
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end
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else
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begin
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cg64.a_op64_reg_reg(current_asmdata.CurrAsmList,op,location.size,
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right.location.register64,
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left.location.register64);
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end;
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end
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else
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begin
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{ right.location<>LOC_REGISTER }
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if (nodetype=subn) and (nf_swapped in flags) then
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begin
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r:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
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cg64.a_load64low_loc_reg(current_asmdata.CurrAsmList,right.location,r);
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cg.a_reg_alloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
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emit_reg_reg(op1,opsize,left.location.register64.reglo,r);
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emit_reg_reg(A_MOV,opsize,r,left.location.register64.reglo);
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cg64.a_load64high_loc_reg(current_asmdata.CurrAsmList,right.location,r);
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{ the carry flag is still ok }
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emit_reg_reg(op2,opsize,left.location.register64.reghi,r);
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cg.a_reg_dealloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
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emit_reg_reg(A_MOV,opsize,r,left.location.register64.reghi);
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end
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else
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begin
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cg64.a_op64_loc_reg(current_asmdata.CurrAsmList,op,location.size,right.location,
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left.location.register64);
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end;
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location_freetemp(current_asmdata.CurrAsmList,right.location);
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end;
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{ only in case of overflow operations }
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{ produce overflow code }
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{ we must put it here directly, because sign of operation }
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{ is in unsigned VAR!! }
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if mboverflow then
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begin
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if cs_check_overflow in current_settings.localswitches then
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begin
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current_asmdata.getjumplabel(hl4);
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if unsigned then
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cg.a_jmp_flags(current_asmdata.CurrAsmList,F_AE,hl4)
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else
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cg.a_jmp_flags(current_asmdata.CurrAsmList,F_NO,hl4);
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cg.a_call_name(current_asmdata.CurrAsmList,'FPC_OVERFLOW',false);
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cg.a_label(current_asmdata.CurrAsmList,hl4);
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end;
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end;
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location_copy(location,left.location);
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end;
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procedure ti386addnode.second_cmp64bit;
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var
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truelabel,
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falselabel,
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hlab : tasmlabel;
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href : treference;
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unsigned : boolean;
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procedure firstjmp64bitcmp;
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var
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oldnodetype : tnodetype;
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begin
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{$ifdef OLDREGVARS}
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load_all_regvars(current_asmdata.CurrAsmList);
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{$endif OLDREGVARS}
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{ the jump the sequence is a little bit hairy }
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case nodetype of
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ltn,gtn:
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begin
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if (hlab<>location.truelabel) then
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cg.a_jmp_flags(current_asmdata.CurrAsmList,getresflags(unsigned),location.truelabel);
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{ cheat a little bit for the negative test }
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toggleflag(nf_swapped);
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if (hlab<>location.falselabel) then
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cg.a_jmp_flags(current_asmdata.CurrAsmList,getresflags(unsigned),location.falselabel);
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toggleflag(nf_swapped);
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end;
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lten,gten:
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begin
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oldnodetype:=nodetype;
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if nodetype=lten then
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nodetype:=ltn
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else
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nodetype:=gtn;
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if (hlab<>location.truelabel) then
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cg.a_jmp_flags(current_asmdata.CurrAsmList,getresflags(unsigned),location.truelabel);
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{ cheat for the negative test }
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if nodetype=ltn then
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nodetype:=gtn
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else
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nodetype:=ltn;
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if (hlab<>location.falselabel) then
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cg.a_jmp_flags(current_asmdata.CurrAsmList,getresflags(unsigned),location.falselabel);
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nodetype:=oldnodetype;
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end;
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equaln:
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cg.a_jmp_flags(current_asmdata.CurrAsmList,F_NE,location.falselabel);
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unequaln:
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cg.a_jmp_flags(current_asmdata.CurrAsmList,F_NE,location.truelabel);
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end;
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end;
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procedure secondjmp64bitcmp;
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begin
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{ the jump the sequence is a little bit hairy }
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case nodetype of
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ltn,gtn,lten,gten:
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begin
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{ the comparisaion of the low dword have to be }
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{ always unsigned! }
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cg.a_jmp_flags(current_asmdata.CurrAsmList,getresflags(true),location.truelabel);
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cg.a_jmp_always(current_asmdata.CurrAsmList,location.falselabel);
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end;
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equaln:
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begin
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cg.a_jmp_flags(current_asmdata.CurrAsmList,F_NE,location.falselabel);
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cg.a_jmp_always(current_asmdata.CurrAsmList,location.truelabel);
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end;
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unequaln:
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begin
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cg.a_jmp_flags(current_asmdata.CurrAsmList,F_NE,location.truelabel);
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cg.a_jmp_always(current_asmdata.CurrAsmList,location.falselabel);
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end;
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end;
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end;
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begin
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truelabel:=nil;
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falselabel:=nil;
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pass_left_right;
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unsigned:=((left.resultdef.typ=orddef) and
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(torddef(left.resultdef).ordtype=u64bit)) or
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((right.resultdef.typ=orddef) and
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(torddef(right.resultdef).ordtype=u64bit));
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{ we have LOC_JUMP as result }
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current_asmdata.getjumplabel(truelabel);
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current_asmdata.getjumplabel(falselabel);
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location_reset_jump(location,truelabel,falselabel);
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{ Relational compares against constants having low dword=0 can omit the
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second compare based on the fact that any unsigned value is >=0 }
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hlab:=nil;
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if (right.location.loc=LOC_CONSTANT) and
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(lo(right.location.value64)=0) then
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begin
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case getresflags(true) of
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F_AE: hlab:=location.truelabel ;
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F_B: hlab:=location.falselabel;
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end;
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end;
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if (right.location.loc=LOC_CONSTANT) and
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(left.location.loc in [LOC_REFERENCE,LOC_CREFERENCE]) then
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begin
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tcgx86(cg).make_simple_ref(current_asmdata.CurrAsmList,left.location.reference);
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href:=left.location.reference;
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inc(href.offset,4);
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emit_const_ref(A_CMP,S_L,aint(hi(right.location.value64)),href);
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firstjmp64bitcmp;
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if assigned(hlab) then
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cg.a_jmp_always(current_asmdata.CurrAsmList,hlab)
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else
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begin
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emit_const_ref(A_CMP,S_L,aint(lo(right.location.value64)),left.location.reference);
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secondjmp64bitcmp;
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end;
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location_freetemp(current_asmdata.CurrAsmList,left.location);
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exit;
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end;
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{ left and right no register? }
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{ then one must be demanded }
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if not (left.location.loc in [LOC_REGISTER,LOC_CREGISTER]) then
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begin
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if not (right.location.loc in [LOC_REGISTER,LOC_CREGISTER]) then
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,true)
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else
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begin
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location_swap(left.location,right.location);
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toggleflag(nf_swapped);
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end;
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end;
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{ at this point, left.location.loc should be LOC_[C]REGISTER }
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case right.location.loc of
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LOC_REGISTER,
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LOC_CREGISTER :
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begin
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emit_reg_reg(A_CMP,S_L,right.location.register64.reghi,left.location.register64.reghi);
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firstjmp64bitcmp;
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emit_reg_reg(A_CMP,S_L,right.location.register64.reglo,left.location.register64.reglo);
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secondjmp64bitcmp;
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end;
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LOC_CREFERENCE,
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LOC_REFERENCE :
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begin
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tcgx86(cg).make_simple_ref(current_asmdata.CurrAsmList,right.location.reference);
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href:=right.location.reference;
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inc(href.offset,4);
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emit_ref_reg(A_CMP,S_L,href,left.location.register64.reghi);
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firstjmp64bitcmp;
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emit_ref_reg(A_CMP,S_L,right.location.reference,left.location.register64.reglo);
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secondjmp64bitcmp;
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location_freetemp(current_asmdata.CurrAsmList,right.location);
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end;
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LOC_CONSTANT :
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begin
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current_asmdata.CurrAsmList.concat(taicpu.op_const_reg(A_CMP,S_L,aint(hi(right.location.value64)),left.location.register64.reghi));
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firstjmp64bitcmp;
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if assigned(hlab) then
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cg.a_jmp_always(current_asmdata.CurrAsmList,hlab)
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else
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begin
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current_asmdata.CurrAsmList.concat(taicpu.op_const_reg(A_CMP,S_L,aint(lo(right.location.value64)),left.location.register64.reglo));
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secondjmp64bitcmp;
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end;
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end;
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else
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internalerror(200203282);
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end;
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end;
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{*****************************************************************************
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x86 MUL
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*****************************************************************************}
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procedure ti386addnode.set_mul_result_location;
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begin
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location_reset(location,LOC_REGISTER,def_cgsize(resultdef));
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{Free EAX,EDX}
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cg.ungetcpuregister(current_asmdata.CurrAsmList,NR_EDX);
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if is_64bit(resultdef) then
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begin
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{Allocate a couple of registers and store EDX:EAX into it}
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location.register64.reghi := cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
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cg.a_load_reg_reg(current_asmdata.CurrAsmList, OS_INT, OS_INT, NR_EDX, location.register64.reghi);
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cg.ungetcpuregister(current_asmdata.CurrAsmList,NR_EAX);
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location.register64.reglo := cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
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cg.a_load_reg_reg(current_asmdata.CurrAsmList, OS_INT, OS_INT, NR_EAX, location.register64.reglo);
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end
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else
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begin
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{Allocate a new register and store the result in EAX in it.}
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location.register:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
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cg.ungetcpuregister(current_asmdata.CurrAsmList,NR_EAX);
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cg.a_load_reg_reg(current_asmdata.CurrAsmList,OS_INT,OS_INT,NR_EAX,location.register);
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end;
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location_freetemp(current_asmdata.CurrAsmList,left.location);
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location_freetemp(current_asmdata.CurrAsmList,right.location);
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end;
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procedure ti386addnode.second_mul(unsigned: boolean);
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var reg:Tregister;
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ref:Treference;
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use_ref:boolean;
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hl4 : tasmlabel;
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const
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asmops: array[boolean] of tasmop = (A_IMUL, A_MUL);
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begin
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pass_left_right;
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reg:=NR_NO;
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reference_reset(ref,sizeof(pint),[]);
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{ Mul supports registers and references, so if not register/reference,
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load the location into a register.
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The variant of IMUL which is capable of doing 32->64 bits has the same restrictions. }
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use_ref:=false;
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if left.location.loc in [LOC_REGISTER,LOC_CREGISTER] then
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reg:=left.location.register
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else if left.location.loc in [LOC_REFERENCE,LOC_CREFERENCE] then
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begin
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tcgx86(cg).make_simple_ref(current_asmdata.CurrAsmList,left.location.reference);
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ref:=left.location.reference;
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use_ref:=true;
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end
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else
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begin
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{LOC_CONSTANT for example.}
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reg:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
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hlcg.a_load_loc_reg(current_asmdata.CurrAsmList,left.resultdef,osuinttype,left.location,reg);
|
|
end;
|
|
{Allocate EAX.}
|
|
cg.getcpuregister(current_asmdata.CurrAsmList,NR_EAX);
|
|
{Load the right value.}
|
|
hlcg.a_load_loc_reg(current_asmdata.CurrAsmList,right.resultdef,osuinttype,right.location,NR_EAX);
|
|
{Also allocate EDX, since it is also modified by a mul (JM).}
|
|
cg.getcpuregister(current_asmdata.CurrAsmList,NR_EDX);
|
|
if use_ref then
|
|
emit_ref(asmops[unsigned],S_L,ref)
|
|
else
|
|
emit_reg(asmops[unsigned],S_L,reg);
|
|
if (cs_check_overflow in current_settings.localswitches) and
|
|
{ 32->64 bit cannot overflow }
|
|
(not is_64bit(resultdef)) then
|
|
begin
|
|
current_asmdata.getjumplabel(hl4);
|
|
cg.a_jmp_flags(current_asmdata.CurrAsmList,F_AE,hl4);
|
|
cg.a_call_name(current_asmdata.CurrAsmList,'FPC_OVERFLOW',false);
|
|
cg.a_label(current_asmdata.CurrAsmList,hl4);
|
|
end;
|
|
set_mul_result_location;
|
|
end;
|
|
|
|
|
|
procedure ti386addnode.second_mul64bit;
|
|
var
|
|
list: TAsmList;
|
|
hreg1,hreg2: tregister;
|
|
begin
|
|
{ 64x64 multiplication yields 128-bit result, but we're only
|
|
interested in its lower 64 bits. This lower part is independent
|
|
of operand signs, and so is the generated code. }
|
|
{ pass_left_right already called from second_add64bit }
|
|
list:=current_asmdata.CurrAsmList;
|
|
if left.location.loc in [LOC_REFERENCE,LOC_CREFERENCE] then
|
|
tcgx86(cg).make_simple_ref(list,left.location.reference);
|
|
if right.location.loc in [LOC_REFERENCE,LOC_CREFERENCE] then
|
|
tcgx86(cg).make_simple_ref(list,right.location.reference);
|
|
|
|
{ calculate 32-bit terms lo(right)*hi(left) and hi(left)*lo(right) }
|
|
if (right.location.loc=LOC_CONSTANT) then
|
|
begin
|
|
{ Omit zero terms, if any }
|
|
hreg1:=NR_NO;
|
|
hreg2:=NR_NO;
|
|
if lo(right.location.value64)<>0 then
|
|
hreg1:=cg.getintregister(list,OS_INT);
|
|
if hi(right.location.value64)<>0 then
|
|
hreg2:=cg.getintregister(list,OS_INT);
|
|
|
|
{ Take advantage of 3-operand form of IMUL }
|
|
case left.location.loc of
|
|
LOC_REGISTER,LOC_CREGISTER:
|
|
begin
|
|
if hreg1<>NR_NO then
|
|
emit_const_reg_reg(A_IMUL,S_L,longint(lo(right.location.value64)),left.location.register64.reghi,hreg1);
|
|
if hreg2<>NR_NO then
|
|
emit_const_reg_reg(A_IMUL,S_L,longint(hi(right.location.value64)),left.location.register64.reglo,hreg2);
|
|
end;
|
|
LOC_REFERENCE,LOC_CREFERENCE:
|
|
begin
|
|
if hreg2<>NR_NO then
|
|
list.concat(taicpu.op_const_ref_reg(A_IMUL,S_L,longint(hi(right.location.value64)),left.location.reference,hreg2));
|
|
inc(left.location.reference.offset,4);
|
|
if hreg1<>NR_NO then
|
|
list.concat(taicpu.op_const_ref_reg(A_IMUL,S_L,longint(lo(right.location.value64)),left.location.reference,hreg1));
|
|
dec(left.location.reference.offset,4);
|
|
end;
|
|
else
|
|
InternalError(2014011602);
|
|
end;
|
|
end
|
|
else
|
|
begin
|
|
hreg1:=cg.getintregister(list,OS_INT);
|
|
hreg2:=cg.getintregister(list,OS_INT);
|
|
cg64.a_load64low_loc_reg(list,left.location,hreg1);
|
|
cg64.a_load64high_loc_reg(list,left.location,hreg2);
|
|
case right.location.loc of
|
|
LOC_REGISTER,LOC_CREGISTER:
|
|
begin
|
|
emit_reg_reg(A_IMUL,S_L,right.location.register64.reghi,hreg1);
|
|
emit_reg_reg(A_IMUL,S_L,right.location.register64.reglo,hreg2);
|
|
end;
|
|
LOC_REFERENCE,LOC_CREFERENCE:
|
|
begin
|
|
emit_ref_reg(A_IMUL,S_L,right.location.reference,hreg2);
|
|
inc(right.location.reference.offset,4);
|
|
emit_ref_reg(A_IMUL,S_L,right.location.reference,hreg1);
|
|
dec(right.location.reference.offset,4);
|
|
end;
|
|
else
|
|
InternalError(2014011603);
|
|
end;
|
|
end;
|
|
{ add hi*lo and lo*hi terms together }
|
|
if (hreg1<>NR_NO) and (hreg2<>NR_NO) then
|
|
emit_reg_reg(A_ADD,S_L,hreg2,hreg1);
|
|
|
|
{ load lo(right) into EAX }
|
|
cg.getcpuregister(list,NR_EAX);
|
|
cg64.a_load64low_loc_reg(list,right.location,NR_EAX);
|
|
|
|
{ multiply EAX by lo(left), producing 64-bit value in EDX:EAX }
|
|
cg.getcpuregister(list,NR_EDX);
|
|
if (left.location.loc in [LOC_REGISTER,LOC_CREGISTER]) then
|
|
emit_reg(A_MUL,S_L,left.location.register64.reglo)
|
|
else if (left.location.loc in [LOC_REFERENCE,LOC_CREFERENCE]) then
|
|
emit_ref(A_MUL,S_L,left.location.reference)
|
|
else
|
|
InternalError(2014011604);
|
|
{ add previously calculated terms to the high half }
|
|
if (hreg1<>NR_NO) then
|
|
emit_reg_reg(A_ADD,S_L,hreg1,NR_EDX)
|
|
else if (hreg2<>NR_NO) then
|
|
emit_reg_reg(A_ADD,S_L,hreg2,NR_EDX)
|
|
else
|
|
InternalError(2014011604);
|
|
|
|
{ Result is now in EDX:EAX. Copy it to virtual registers. }
|
|
set_mul_result_location;
|
|
end;
|
|
|
|
|
|
begin
|
|
caddnode:=ti386addnode;
|
|
end.
|