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362 lines
15 KiB
ObjectPascal
362 lines
15 KiB
ObjectPascal
{
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Copyright (c) 1998-2002 by Florian Klaempfl
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Generate 680x0 assembler for math nodes
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit n68kmat;
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{$i fpcdefs.inc}
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interface
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uses
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node,nmat,ncgmat,cpubase,cgbase;
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type
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tm68knotnode = class(tnotnode)
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procedure pass_generate_code;override;
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end;
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tm68kmoddivnode = class(tcgmoddivnode)
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procedure emit_div_reg_reg(signed: boolean;denum,num : tregister);override;
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procedure emit_mod_reg_reg(signed: boolean;denum,num : tregister);override;
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end;
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tm68kshlshrnode = class(tshlshrnode)
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procedure pass_generate_code;override;
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{ everything will be handled in pass_2 }
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function first_shlshr64bitint: tnode; override;
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end;
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implementation
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uses
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globtype,systems,
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cutils,verbose,globals,
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symconst,symdef,aasmbase,aasmtai,aasmdata,aasmcpu,
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pass_1,pass_2,procinfo,
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ncon,
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cpuinfo,paramgr,defutil,parabase,
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tgobj,ncgutil,cgobj,cgutils,rgobj,rgcpu,cgcpu,cg64f32;
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{*****************************************************************************
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TM68KNOTNODE
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*****************************************************************************}
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procedure tm68knotnode.pass_generate_code;
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var
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hl : tasmlabel;
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opsize : tcgsize;
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begin
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opsize:=def_cgsize(resultdef);
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if is_boolean(resultdef) then
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begin
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{ the second pass could change the location of left }
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{ if it is a register variable, so we've to do }
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{ this before the case statement }
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if left.location.loc<>LOC_JUMP then
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secondpass(left);
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case left.location.loc of
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LOC_JUMP :
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begin
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location_reset(location,LOC_JUMP,OS_NO);
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hl:=current_procinfo.CurrTrueLabel;
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current_procinfo.CurrTrueLabel:=current_procinfo.CurrFalseLabel;
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current_procinfo.CurrFalseLabel:=hl;
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secondpass(left);
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maketojumpbool(current_asmdata.CurrAsmList,left,lr_load_regvars);
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hl:=current_procinfo.CurrTrueLabel;
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current_procinfo.CurrTrueLabel:=current_procinfo.CurrFalseLabel;
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current_procinfo.CurrFalseLabel:=hl;
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end;
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LOC_FLAGS :
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begin
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location_copy(location,left.location);
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// location_release(current_asmdata.CurrAsmList,left.location);
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inverse_flags(location.resflags);
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end;
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LOC_CONSTANT,
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LOC_REGISTER,
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LOC_CREGISTER,
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LOC_REFERENCE,
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LOC_CREFERENCE :
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begin
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location_force_reg(current_asmdata.CurrAsmList,left.location,def_cgsize(resultdef),true);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg(A_TST,tcgsize2opsize[opsize],left.location.register));
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// location_release(current_asmdata.CurrAsmList,left.location);
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location_reset(location,LOC_FLAGS,OS_NO);
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location.resflags:=F_E;
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end;
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else
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internalerror(200203224);
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end;
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end
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else if is_64bitint(left.resultdef) then
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begin
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secondpass(left);
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location_copy(location,left.location);
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location_force_reg(current_asmdata.CurrAsmList,location,OS_64,false);
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cg64.a_op64_loc_reg(current_asmdata.CurrAsmList,OP_NOT,OS_64,location,
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joinreg64(location.register64.reglo,location.register64.reghi));
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end
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else
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begin
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secondpass(left);
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location_force_reg(current_asmdata.CurrAsmList,left.location,def_cgsize(left.resultdef),false);
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location_copy(location,left.location);
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if location.loc=LOC_CREGISTER then
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location.register := cg.getintregister(current_asmdata.CurrAsmList,opsize);
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{ perform the NOT operation }
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cg.a_op_reg_reg(current_asmdata.CurrAsmList,OP_NOT,opsize,location.register,left.location.register);
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end;
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end;
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{*****************************************************************************
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TM68KMODDIVNODE
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*****************************************************************************}
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procedure tm68kmoddivnode.emit_div_reg_reg(signed: boolean;denum,num : tregister);
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var
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continuelabel : tasmlabel;
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reg_d0,reg_d1 : tregister;
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paraloc1 : tcgpara;
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begin
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{ no RTL call, so inline a zero denominator verification }
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if current_settings.cputype <> cpu_MC68000 then
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begin
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{ verify if denominator is zero }
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current_asmdata.getjumplabel(continuelabel);
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{ compare against zero, if not zero continue }
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cg.a_cmp_const_reg_label(current_asmdata.CurrAsmList,OS_S32,OC_NE,0,denum,continuelabel);
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// paraloc1.init;
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// cg.a_load_const_cgpara(current_asmdata.CurrAsmList,OS_S32,200,paramanager.getintparaloc(pocall_default,1,paraloc1));
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cg.a_call_name(current_asmdata.CurrAsmList,'FPC_HANDLEERROR',false);
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cg.a_label(current_asmdata.CurrAsmList, continuelabel);
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if signed then
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_DIVS,S_L,denum,num))
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else
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_DIVU,S_L,denum,num));
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{ result should be in denuminator }
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cg.a_load_reg_reg(current_asmdata.CurrAsmList,OS_INT,OS_INT,num,denum);
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end
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else
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begin
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{ On MC68000/68010 mw must pass through RTL routines }
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reg_d0:=NR_D0;
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cg.getcpuregister(current_asmdata.CurrAsmList,NR_D0);
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reg_d1:=NR_D1;
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cg.getcpuregister(current_asmdata.CurrAsmList,NR_D1);
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{ put numerator in d0 }
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cg.a_load_reg_reg(current_asmdata.CurrAsmList,OS_INT,OS_INT,num,reg_d0);
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{ put denum in D1 }
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cg.a_load_reg_reg(current_asmdata.CurrAsmList,OS_INT,OS_INT,denum,reg_d1);
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if signed then
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cg.a_call_name(current_asmdata.CurrAsmList,'FPC_DIV_LONGINT',false)
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else
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cg.a_call_name(current_asmdata.CurrAsmList,'FPC_DIV_CARDINAL',false);
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cg.a_load_reg_reg(current_asmdata.CurrAsmList,OS_INT,OS_INT,reg_d0,denum);
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cg.ungetcpuregister(current_asmdata.CurrAsmList,reg_d0);
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cg.ungetcpuregister(current_asmdata.CurrAsmList,reg_d1);
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end;
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end;
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procedure tm68kmoddivnode.emit_mod_reg_reg(signed: boolean;denum,num : tregister);
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var tmpreg : tregister;
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continuelabel : tasmlabel;
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signlabel : tasmlabel;
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reg_d0,reg_d1 : tregister;
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begin
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// writeln('emit mod reg reg');
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{ no RTL call, so inline a zero denominator verification }
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if current_settings.cputype <> cpu_MC68000 then
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begin
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{ verify if denominator is zero }
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current_asmdata.getjumplabel(continuelabel);
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{ compare against zero, if not zero continue }
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cg.a_cmp_const_reg_label(current_asmdata.CurrAsmList,OS_S32,OC_NE,0,denum,continuelabel);
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// cg.a_load_const_cgpara(current_asmdata.CurrAsmList, OS_S32,200,paramanager.getintparaloc(pocall_default,1));
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cg.a_call_name(current_asmdata.CurrAsmList,'FPC_HANDLEERROR',false);
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cg.a_label(current_asmdata.CurrAsmList, continuelabel);
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tmpreg:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
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{ we have to prepare the high register with the }
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{ correct sign. i.e we clear it, check if the low dword reg }
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{ which will participate in the division is signed, if so we}
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{ we extend the sign to the high doword register by inverting }
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{ all the bits. }
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current_asmdata.CurrAsmList.concat(taicpu.op_reg(A_CLR,S_L,tmpreg));
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current_asmdata.getjumplabel(signlabel);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg(A_TST,S_L,tmpreg));
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cg.a_cmp_const_reg_label(current_asmdata.CurrAsmList,OS_S32,OC_A,0,tmpreg,signlabel);
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{ its a negative value, therefore change sign }
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cg.a_label(current_asmdata.CurrAsmList,signlabel);
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{ tmpreg:num / denum }
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if signed then
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_DIVSL,S_L,denum,tmpreg,num))
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else
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_DIVUL,S_L,denum,tmpreg,num));
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{ remainder in tmpreg }
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cg.a_load_reg_reg(current_asmdata.CurrAsmList,OS_INT,OS_INT,tmpreg,denum);
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// cg.ungetcpuregister(current_asmdata.CurrAsmList,tmpreg);
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end
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else
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begin
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{ On MC68000/68010 mw must pass through RTL routines }
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Reg_d0:=NR_D0;
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cg.getcpuregister(current_asmdata.CurrAsmList,NR_D0);
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Reg_d1:=NR_D1;
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cg.getcpuregister(current_asmdata.CurrAsmList,NR_D1);
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{ put numerator in d0 }
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cg.a_load_reg_reg(current_asmdata.CurrAsmList,OS_INT,OS_INT,num,Reg_D0);
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{ put denum in D1 }
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cg.a_load_reg_reg(current_asmdata.CurrAsmList,OS_INT,OS_INT,denum,Reg_D1);
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if signed then
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cg.a_call_name(current_asmdata.CurrAsmList,'FPC_MOD_LONGINT',false)
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else
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cg.a_call_name(current_asmdata.CurrAsmList,'FPC_MOD_CARDINAL',false);
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cg.a_load_reg_reg(current_asmdata.CurrAsmList,OS_INT,OS_INT,Reg_D0,denum);
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cg.ungetcpuregister(current_asmdata.CurrAsmList,Reg_D0);
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cg.ungetcpuregister(current_asmdata.CurrAsmList,Reg_D1);
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end;
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// writeln('exits');
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end;
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{*****************************************************************************
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TM68KSHLRSHRNODE
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*****************************************************************************}
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function tm68kShlShrNode.first_shlshr64bitint:TNode;
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begin
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{ 2nd pass is our friend }
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result := nil;
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end;
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{ TODO: FIX ME!!! shlshrnode needs review}
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procedure tm68kshlshrnode.pass_generate_code;
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var
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hregister,resultreg,hregister1,
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hreg64hi,hreg64lo : tregister;
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op : topcg;
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shiftval: aint;
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begin
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secondpass(left);
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secondpass(right);
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if is_64bit(left.resultdef) then
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begin
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location_reset(location,LOC_REGISTER,OS_64);
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{ load left operator in a register }
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location_force_reg(current_asmdata.CurrAsmList,left.location,OS_64,false);
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hreg64hi:=left.location.register64.reghi;
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hreg64lo:=left.location.register64.reglo;
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shiftval := tordconstnode(right).value.svalue;
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shiftval := shiftval and 63;
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if shiftval > 31 then
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begin
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if nodetype = shln then
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begin
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cg.a_load_const_reg(current_asmdata.CurrAsmList,OS_32,0,hreg64hi);
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if (shiftval and 31) <> 0 then
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SHL,OS_32,shiftval and 31,hreg64lo,hreg64lo);
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end
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else
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begin
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cg.a_load_const_reg(current_asmdata.CurrAsmList,OS_32,0,hreg64lo);
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if (shiftval and 31) <> 0 then
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SHR,OS_32,shiftval and 31,hreg64hi,hreg64hi);
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end;
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location.register64.reglo:=hreg64hi;
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location.register64.reghi:=hreg64lo;
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end
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else
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begin
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hregister:=cg.getintregister(current_asmdata.CurrAsmList,OS_32);
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if nodetype = shln then
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begin
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SHR,OS_32,32-shiftval,hreg64lo,hregister);
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SHL,OS_32,shiftval,hreg64hi,hreg64hi);
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cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList,OP_OR,OS_32,hregister,hreg64hi,hreg64hi);
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SHL,OS_32,shiftval,hreg64lo,hreg64lo);
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end
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else
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begin
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SHL,OS_32,32-shiftval,hreg64hi,hregister);
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SHR,OS_32,shiftval,hreg64lo,hreg64lo);
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cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList,OP_OR,OS_32,hregister,hreg64lo,hreg64lo);
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SHR,OS_32,shiftval,hreg64hi,hreg64hi);
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end;
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location.register64.reghi:=hreg64hi;
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location.register64.reglo:=hreg64lo;
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end;
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end
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else
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begin
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{ load left operators in a register }
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location_force_reg(current_asmdata.CurrAsmList,left.location,def_cgsize(left.resultdef),true);
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location_copy(location,left.location);
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resultreg := location.register;
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hregister1 := location.register;
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if (location.loc = LOC_CREGISTER) then
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begin
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location.loc := LOC_REGISTER;
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resultreg := cg.GetIntRegister(current_asmdata.CurrAsmList,OS_INT);
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location.register := resultreg;
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end;
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{ determine operator }
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if nodetype=shln then
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op:=OP_SHL
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else
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op:=OP_SHR;
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{ shifting by a constant directly coded: }
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if (right.nodetype=ordconstn) then
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begin
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if tordconstnode(right).value.svalue and 31<>0 then
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,op,OS_32,tordconstnode(right).value.svalue and 31,hregister1,resultreg)
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end
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else
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begin
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{ load shift count in a register if necessary }
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location_force_reg(current_asmdata.CurrAsmList,right.location,def_cgsize(right.resultdef),true);
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cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList,op,OS_32,right.location.register,hregister1,resultreg);
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end;
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end;
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end;
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begin
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cnotnode:=tm68knotnode;
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cmoddivnode:=tm68kmoddivnode;
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cshlshrnode:=tm68kshlshrnode;
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end.
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