mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-11-04 11:39:40 +01:00
55669f62b1
Made absolutevarsym use PUint instead of AWord for its offset to fix range errors. git-svn-id: trunk@31242 -
446 lines
18 KiB
ObjectPascal
446 lines
18 KiB
ObjectPascal
unit ATA6286;
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{$goto on}
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interface
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var
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// SENSOR_INTERFACE
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MSVCAL : byte absolute $00+$67; // Motion Sensor Voltage Calibration Register
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SCR : byte absolute $00+$48; // Sensor Control Register
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SCCR : byte absolute $00+$49; // Sensor Capacitor Control Register
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SVCR : byte absolute $00+$47; // Sensor Voltage Control Register
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SIMSK : byte absolute $00+$61; // Sensor Interrupt Mask register
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SSFR : byte absolute $00+$39; // Sensor Status + Flag Register
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TSCR : byte absolute $00+$64; // Temperature Sensor Control Register
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// SPI
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SPDR : byte absolute $00+$4E; // SPI Data Register
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SPSR : byte absolute $00+$4D; // SPI Status Register
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SPCR : byte absolute $00+$4C; // SPI Control Register
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// CPU
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CLKPR : byte absolute $00+$5C; // Clock Prescaler Register
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CMCR : byte absolute $00+$2F; // Clock Management Control Register
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CMSR : byte absolute $00+$30; // Clock Management Status Register
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CMIMR : byte absolute $00+$5B; // Clock Management Interrupt Mask Register
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FRCCAL : byte absolute $00+$66; // FRC-Oscillator Calibration Register
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SRCCAL : byte absolute $00+$65; // SRC-Oscillator Calibration Register
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VMCSR : byte absolute $00+$36; // Voltage Monitor Control and Status Register
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SREG : byte absolute $00+$5F; // Status Register
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SP : word absolute $00+$5D; // Stack Pointer
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SPL : byte absolute $00+$5D; // Stack Pointer
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SPH : byte absolute $00+$5D+1; // Stack Pointer
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SPMCSR : byte absolute $00+$57; // Store Program Memory Control Register
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MCUCR : byte absolute $00+$55; // MCU Control Register
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MCUSR : byte absolute $00+$54; // MCU Status Register
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SMCR : byte absolute $00+$53; // Sleep Mode Control Register
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GPIOR2 : byte absolute $00+$4B; // General Purpose I/O Register 2
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GPIOR1 : byte absolute $00+$4A; // General Purpose I/O Register 1
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GPIOR0 : byte absolute $00+$3E; // General Purpose I/O Register 0
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// LFRX
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LFRCR : byte absolute $00+$82; // Low Frequency Receiver Control Register
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LFCDR : byte absolute $00+$52; // LF receiver Control und Data Register
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LFRB : byte absolute $00+$56; // Low Frequency Receive data Buffer
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LFRR : byte absolute $00+$50; // LF RSSI Data Register
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LFHCR : byte absolute $00+$83; // LF Header Compare Register
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LFIDC : word absolute $00+$84; // LF ID Compare Register
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LFIDCL : byte absolute $00+$84; // LF ID Compare Register
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LFIDCH : byte absolute $00+$84+1; // LF ID Compare Register
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LFIMR : byte absolute $00+$81; // Low Frequency Interrupt Mask Register
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LFFR : byte absolute $00+$38; // Low Frequency Flag Register
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LFCAL : word absolute $00+$86; // LF Calibration Register Bytes
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LFCALL : byte absolute $00+$86; // LF Calibration Register Bytes
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LFCALH : byte absolute $00+$86+1; // LF Calibration Register Bytes
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// EXTERNAL_INTERRUPT
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EICRA : byte absolute $00+$69; // External Interrupt Control Register
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EIMSK : byte absolute $00+$44; // External Interrupt Mask Register
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EIFR : byte absolute $00+$3D; // External Interrupt Flag Register
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PCMSK0 : byte absolute $00+$6A; // Pin Change Mask Register 0
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PCMSK1 : byte absolute $00+$6B; // Pin Change Mask Register 1
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PCMSK2 : byte absolute $00+$6C; // Pin Change Mask Register 2
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PCIFR : byte absolute $00+$37; // Pin Change Interrupt Flag Register
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PCICR : byte absolute $00+$43; // Pin Change Interrupt Control Register
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// PORTB
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PORTB : byte absolute $00+$25; // Port B Data Register
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DDRB : byte absolute $00+$24; // Port B Data Direction Register
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PINB : byte absolute $00+$23; // Port B Input Pins
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// PORTD
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PORTD : byte absolute $00+$2B; // Port D Data Register
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DDRD : byte absolute $00+$2A; // Port D Data Direction Register
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PIND : byte absolute $00+$29; // Port D Input Pins
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// TIMER_COUNTER_1
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T1CR : byte absolute $00+$58; // Timer 1 Control Register
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T10IFR : byte absolute $00+$3A; // Timer1/0 Interrupt Flag Register
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// TIMER_COUNTER_2
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T2CRA : byte absolute $00+$31; // Timer 2 Control Register A
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T2CRB : byte absolute $00+$32; // Timer 2 Control Register B
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T2MDR : byte absolute $00+$4F; // Timer 2 Modulator Data Register
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T2ICR : byte absolute $00+$6F; // Timer 2 Input Capture Register High Byte
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T2ICRL : byte absolute $00+$6E; // Timer 2 Input Capture Register Low Byte
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T2COR : word absolute $00+$70; // Timer2 Compare Register Bytes
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T2CORL : byte absolute $00+$70; // Timer2 Compare Register Bytes
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T2CORH : byte absolute $00+$70+1; // Timer2 Compare Register Bytes
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T2IFR : byte absolute $00+$3B; // Timer2 Interrupt Flag Register
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T2IMR : byte absolute $00+$74; // Timer 2 Interrupt Mask Register
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T2MRA : byte absolute $00+$72; // Timer 2 Mode Register A
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T2MRB : byte absolute $00+$73; // Timer 2 Mode Register B
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// TIMER_COUNTER_3
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T3CRA : byte absolute $00+$34; // Timer 3 Control Register A
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T3CRB : byte absolute $00+$7E; // Timer 3 Control Register B
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T3MRA : byte absolute $00+$7C; // Timer 3 Mode Register A
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T3IFR : byte absolute $00+$3C; // Timer3 Interrupt Flag Register
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T3IMR : byte absolute $00+$7F; // Timer3 Interrupt Mask Register
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T3MRB : byte absolute $00+$7D; // Timer 3 Mode Register B
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T3ICR : word absolute $00+$76; // Timer3 Input Capture Register Bytes
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T3ICRL : byte absolute $00+$76; // Timer3 Input Capture Register Bytes
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T3ICRH : byte absolute $00+$76+1; // Timer3 Input Capture Register Bytes
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T3CORA : word absolute $00+$78; // Timer3 COmpare Register A Bytes
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T3CORAL : byte absolute $00+$78; // Timer3 COmpare Register A Bytes
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T3CORAH : byte absolute $00+$78+1; // Timer3 COmpare Register A Bytes
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T3CORB : word absolute $00+$7A; // Timer3 COmpare Register B Bytes
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T3CORBL : byte absolute $00+$7A; // Timer3 COmpare Register B Bytes
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T3CORBH : byte absolute $00+$7A+1; // Timer3 COmpare Register B Bytes
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// WATCHDOG
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WDTCR : byte absolute $00+$60; // Watchdog Timer Control Register
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// TIMER_COUNTER_0
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T0CR : byte absolute $00+$59; // Timer 0 Control Register
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// EEPROM
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EEAR : word absolute $00+$41; // EEPROM Address Register Bytes
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EEARL : byte absolute $00+$41; // EEPROM Address Register Bytes
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EEARH : byte absolute $00+$41+1; // EEPROM Address Register Bytes
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EEDR : byte absolute $00+$40; // EEPROM Data Register
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EECR : byte absolute $00+$3F; // EEPROM Control Register
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// PORTC
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PORTC : byte absolute $00+$28; // Port C Data Register
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DDRC : byte absolute $00+$27; // Port C Data Direction Register
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PINC : byte absolute $00+$26; // Port C Input Pins
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const
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// SCR
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SMEN = 3; // Sensor Motion Enable Bit
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SEN = 1; // Sensor enable Bits
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SMS = 0; // Sensor Measurement Start Bit
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// SCCR
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SCCS = 2; // Sensor Capacitor Channel Select Bit2
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SRCC = 0; // Sensor Reference Charge Current Bit1
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// SIMSK
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MSIE = 0; // Motion Sensor Interrupt Enable Bit
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// SSFR
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MSENO = 1; // Motion Sensor Output
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MSENF = 0; // Motion Sensor Flag
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// TSCR
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TSSD = 0; // Temperature Sensor Shutdown mode Disable
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// SPSR
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SPIF = 7; // SPI Interrupt Flag
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WCOL = 6; // Write Collision Flag
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SPI2X = 0; // Double SPI Speed Bit
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// SPCR
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SPIE = 7; // SPI Interrupt Enable
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SPE = 6; // SPI Enable
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DORD = 5; // Data Order
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MSTR = 4; // Master/Slave Select
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CPOL = 3; // Clock polarity
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CPHA = 2; // Clock Phase
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SPR = 0; // SPI Clock Rate Selects
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// CLKPR
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CLPCE = 7; // Clock Prescaler Change Enable Bit
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CLTPS = 3; // Clock Timer Prescaler Select Bits
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CLKPS = 0; // Clock system Prescaler Select Bits
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// CMCR
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CMCCE = 7; // Clock Management Control Change Enable Bit
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ECINS = 5; // External Clock Input Select Bit
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CCS = 4; // Core Clock Select Bit
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CMONEN = 3; // Clock Monitoring Enable
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SRCD = 2; // Slow RC-oscillator Disable Bit
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CMM = 0; // Clock Management Mode Bitss
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// CMSR
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ECF = 0; // External Clock input Flag Bit
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// CMIMR
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ECIE = 0; // External Clock input Interrupt Enable Bit
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// VMCSR
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BODLS = 7; // Brown-Out Detection Level Select Bit
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BODPD = 6; // Brown-Out Detection on Power-Down Bit
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VMF = 5; // Voltage Monitor Flag
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VMIM = 4; // Voltage Monitor Interrupt Mask Bit
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VMLS = 1; // Voltage Monitor Level Select Bits
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VMEN = 0; // Voltage Monitor Enable Bit
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// SREG
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I = 7; // Global Interrupt Enable
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T = 6; // Bit Copy Storage
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H = 5; // Half Carry Flag
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S = 4; // Sign Bit
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V = 3; // Two's Complement Overflow Flag
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N = 2; // Negative Flag
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Z = 1; // Zero Flag
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C = 0; // Carry Flag
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// SPMCSR
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SPMIE = 7; // SPM Interrupt Enable
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RWWSB = 6; // Read-While-Write Section Busy
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RWWSRE = 4; // Read-While-Write section read enable
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BLBSET = 3; // Boot Lock Bit Set
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PGWRT = 2; // Page Write
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PGERS = 1; // Page Erase
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SELFPRGEN = 0; // Self Programming Enable
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// MCUCR
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PUD = 4; //
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IVSEL = 1; // Interrupt Vector Select
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IVCE = 0; // Interrupt Vector Change Enable
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// MCUSR
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TSRF = 5; // Temperature Shutdown Reset Flag
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WDRF = 3; // Watchdog Reset Flag
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BORF = 2; // Brown-out Reset Flag
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EXTRF = 1; // External Reset Flag
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PORF = 0; // Power-on reset flag
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// SMCR
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SM = 1; //
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SE = 0; //
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// LFRCR
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LFCS = 5; // LF receiver Capacitor Select Bits
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LFRSS = 4; // LF Receiver Sensitivity Select Bit
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LFWM = 2; // LF receiver Wake-up Mode Bits
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LFBM = 1; // LF receiver Burst Mode enable Bit
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LFEN = 0; // LF receiver Enable Bit
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// LFCDR
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LFSCE = 7; // LF receiver RSSI Software Capture Enable Bit
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LFRST = 6; // LF receiver Reset Bit
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LFDO = 0; // LF receiver Data Output Bit
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// LFIMR
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LFEIM = 2; // LF receiver End of data Interrupt Mask bit
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LFBIM = 1; // LF receiver data Buffer Interrupt Mask bit
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LFWIM = 0; // LF receiver Wake-up Interrupt Mask bit
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// LFFR
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LFRF = 3; // LF receiver Rssi data Flag
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LFEDF = 2; // LF receiver End of data Flag
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LFBF = 1; // LF receiver data Buffer full Flag
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LFWPF = 0; // LF receiver Wake-up Flag
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// EICRA
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ISC1 = 2; // External Interrupt Sense Control 1 Bits
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ISC0 = 0; // External Interrupt Sense Control 0 Bits
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// EIMSK
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INT = 0; // External Interrupt Request 1 Enable
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// EIFR
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INTF = 0; // External Interrupt Flags
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// PCMSK0
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PCINT = 0; // Pin Change Enable Masks
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// PCMSK1
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// PCMSK2
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// PCIFR
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PCIF = 0; // Pin Change Interrupt Flags
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// PCICR
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PCIE = 0; // Pin Change Interrupt Enables
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// T1CR
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T1IE = 7; // Timer 1 Interrupt Enable Bit
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T1CS = 3; // Timer 1 Clock Select Bits
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T1PS = 0; // Timer 1 Prescaler Select Bits
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// T10IFR
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T1F = 1; // Timer 1 Flag Bit
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T0F = 0; // Timer 0 Flag Bit
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// T2CRA
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T2E = 7; // Timer 2 Enable Bit
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T2TS = 6; // Timer 2 Toggle with Start Bit
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T2ICS = 5; // Timer Input Capture Select Bit
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T2CRM = 3; // Timer 2 Compare Reset Mask Bit
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T2CR = 2; // Timer2 Counter Reset
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T2CTM = 1; // Timer 2 Compare Toggle Mask Bit
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T2OTM = 0; // Timer 2 Overflow Toggle Mask Bit
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// T2CRB
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T2SCE = 0; // Timer 2 Software Capture Enable Bit
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// T2IFR
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T2TCF = 5; // Timer2 SSI Transmit Complete Flag Bit
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T2TXF = 4; // Timer2 SSI Transmit Flag Bit
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T2RXF = 3; // Timer2 SSI Receive Flag Bit
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T2ICF = 2; // Timer2 Input Capture Flag Bit
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T2COF = 1; // Timer 2 Compare Flag Bit
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T2OFF = 0; // Timer 2 Overflow Flag Bit
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// T2IMR
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T2TCIM = 5; // Timer2 SSI Transmit Complete Interrupt Mask Bit
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T2TXIM = 4; // Timer2 SSI Transmit Interrupt Mask Bit
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T2RXIM = 3; // Timer2 SSI Receive Interrupt Mask Bit
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T2CPIM = 2; // Timer 2 Capture Interrupt Mask Bit
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T2CIM = 1; // Timer 2 Compare Interrupt Mask Bit
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T2OIM = 0; // Timer 2 Overflow Interrupt Mask Bit
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// T2MRA
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T2TP = 6; // Timer 2 Top select Bits
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T2CNC = 5; // Timer 2 Input Capture Noise Canceler Bit
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T2CE = 3; // Timer 2 Capture Edge Select Bits
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T2CS = 0; // Timer 2 Clock Select Bits
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// T2MRB
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T2SSIE = 7; // Timer 2 SSI Enable Bit
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T2CPOL = 6; // Timer2 Clock Polarity for SSI shift clock
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T2TOP = 4; // Timer 2 Toggle Output Preset Bit
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T2M = 0; // Timer 2 Mode Bits
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// T3CRA
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T3E = 7; // Timer 3 Enable Bit
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T3TS = 6; // Timer 3 Toggle with Start Bit
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T3CR = 2; // Timer3 Counter Reset
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T3SCE = 1; // Timer 3 Software Capture Enable Bit
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T3AC = 0; // Timer 3 Alternate Compare register sequence bit
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// T3CRB
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T3CPRM = 6; // Timer 3 CaPture Reset Mask bit
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T3CRMB = 5; // Timer 3 Compare Reset Mask bit B
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T3SAMB = 4; // Timer 3 Single Action Mask bit B
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T3CTMB = 3; // Timer 3 Compare Toggle Mask bit B
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T3CRMA = 2; // Timer 3 Compare Reset Mask bit A
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T3SAMA = 1; // Timer 3 Single Action Mask bit A
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T3CTMA = 0; // Timer 3 Compare Toggle Mask bit A
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// T3MRA
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T3ICS = 6; // Timer 3 Input Capture Select Bits
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T3CNC = 5; // Timer 3 input Capture Noise Canceler Bit
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T3CE = 3; // Timer 3 Capture Edge select Bits
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T3CS = 0; // Timer 3 Clock Select Bits
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// T3IFR
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T3ICF = 3; // Timer3 Input Capture Flag bit
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T3COBF = 2; // Timer3 Compare B Flag bit
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T3COAF = 1; // Timer3 Compare A Flag bit
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T3OFF = 0; // Timer3 OverFlow Flag bit
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// T3IMR
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T3CPIM = 3; // Timer3 Capture Interrupt Mask bit
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T3CBIM = 2; // Timer3 Compare B Interrupt Mask bit
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T3CAIM = 1; // Timer3 Compare A Interrupt Mask bit
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T3OIM = 0; // Timer3 Overflow Interrupt Mask bit
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// T3MRB
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T3TOP = 4; // Timer 3 Toggle Output Preset Bit
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T3M = 0; // Timer 3 Mode Bits
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// WDTCR
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WDCE = 4; // Watchdog Change Enable
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WDE = 3; // Watch Dog Enable
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WDPS = 0; // Watch Dog Timer Prescaler Select bits
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// T0CR
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T0PBS = 5; // Timer 0 Prescaler B Select Bits
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T0PR = 4; // Timer 0 Prescaler Reset Bit
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T0IE = 3; // Timer 0 Interrupt Enable Bit
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T0PAS = 0; // Timer 0 Prescaler A Select Bits
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// T10IFR
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// EECR
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EEPM = 4; // EEPROM Programming Mode Bits
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EERIE = 3; // EEPROM Ready Interrupt Enable
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EEMWE = 2; // EEPROM Master Write Enable
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EEWE = 1; // EEPROM Write Enable
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EERE = 0; // EEPROM Read Enable
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implementation
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{$define RELBRANCHES}
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{$i avrcommon.inc}
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procedure INT0_ISR; external name 'INT0_ISR'; // Interrupt 1 External Interrupt Request 0
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procedure INT1_ISR; external name 'INT1_ISR'; // Interrupt 2 External Interrupt Request 1
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procedure PCINT0_ISR; external name 'PCINT0_ISR'; // Interrupt 3 Pin Change Interrupt Request 0
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procedure PCINT1_ISR; external name 'PCINT1_ISR'; // Interrupt 4 Pin Change Interrupt Request 1
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procedure PCINT2_ISR; external name 'PCINT2_ISR'; // Interrupt 5 Pin Change Interrupt Request 2
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procedure INTVM_ISR; external name 'INTVM_ISR'; // Interrupt 6 Voltage Monitor Interrupt
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procedure SENINT_ISR; external name 'SENINT_ISR'; // Interrupt 7 Sensor Interface Interrupt
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procedure INTT0_ISR; external name 'INTT0_ISR'; // Interrupt 8 Timer0 Interval Interrupt
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procedure LFWP_ISR; external name 'LFWP_ISR'; // Interrupt 9 LF-Receiver Wake-up Interrupt
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procedure T3CAP_ISR; external name 'T3CAP_ISR'; // Interrupt 10 Timer/Counter3 Capture Event
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procedure T3COMA_ISR; external name 'T3COMA_ISR'; // Interrupt 11 Timer/Counter3 Compare Match A
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procedure T3COMB_ISR; external name 'T3COMB_ISR'; // Interrupt 12 Timer/Counter3 Compare Match B
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procedure T3OVF_ISR; external name 'T3OVF_ISR'; // Interrupt 13 Timer/Counter3 Overflow
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procedure T2CAP_ISR; external name 'T2CAP_ISR'; // Interrupt 14 Timer/Counter2 Capture Event
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procedure T2COM_ISR; external name 'T2COM_ISR'; // Interrupt 15 Timer/Counter2 Compare Match
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procedure T2OVF_ISR; external name 'T2OVF_ISR'; // Interrupt 16 Timer/Counter2 Overflow
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procedure SPISTC_ISR; external name 'SPISTC_ISR'; // Interrupt 17 SPI Serial Transfer Complete
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procedure LFRXB_ISR; external name 'LFRXB_ISR'; // Interrupt 18 LF Receive Buffer Interrupt
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procedure INTT1_ISR; external name 'INTT1_ISR'; // Interrupt 19 Timer1 Interval Interrupt
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procedure T2RXB_ISR; external name 'T2RXB_ISR'; // Interrupt 20 Timer2 SSI Receive Buffer Interrupt
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procedure T2TXB_ISR; external name 'T2TXB_ISR'; // Interrupt 21 Timer2 SSI Transmit Buffer Interrupt
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procedure T2TXC_ISR; external name 'T2TXC_ISR'; // Interrupt 22 Timer2 SSI Transmit Complete Interrupt
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procedure LFREOB_ISR; external name 'LFREOB_ISR'; // Interrupt 23 LF-Receiver End of Burst Interrupt
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procedure EXCM_ISR; external name 'EXCM_ISR'; // Interrupt 24 External Input Clock break down Interrupt
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procedure EEREADY_ISR; external name 'EEREADY_ISR'; // Interrupt 25 EEPROM Ready Interrupt
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procedure SPM_RDY_ISR; external name 'SPM_RDY_ISR'; // Interrupt 26 Store Program Memory Ready
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procedure _FPC_start; assembler; nostackframe;
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label
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_start;
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asm
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.init
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.globl _start
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rjmp _start
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rjmp INT0_ISR
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rjmp INT1_ISR
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rjmp PCINT0_ISR
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rjmp PCINT1_ISR
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rjmp PCINT2_ISR
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rjmp INTVM_ISR
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rjmp SENINT_ISR
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rjmp INTT0_ISR
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rjmp LFWP_ISR
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rjmp T3CAP_ISR
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rjmp T3COMA_ISR
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rjmp T3COMB_ISR
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rjmp T3OVF_ISR
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rjmp T2CAP_ISR
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rjmp T2COM_ISR
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rjmp T2OVF_ISR
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rjmp SPISTC_ISR
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rjmp LFRXB_ISR
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rjmp INTT1_ISR
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rjmp T2RXB_ISR
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rjmp T2TXB_ISR
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rjmp T2TXC_ISR
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rjmp LFREOB_ISR
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rjmp EXCM_ISR
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rjmp EEREADY_ISR
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rjmp SPM_RDY_ISR
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{$i start.inc}
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.weak INT0_ISR
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.weak INT1_ISR
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.weak PCINT0_ISR
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.weak PCINT1_ISR
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.weak PCINT2_ISR
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.weak INTVM_ISR
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.weak SENINT_ISR
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.weak INTT0_ISR
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|
.weak LFWP_ISR
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|
.weak T3CAP_ISR
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|
.weak T3COMA_ISR
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|
.weak T3COMB_ISR
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|
.weak T3OVF_ISR
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|
.weak T2CAP_ISR
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|
.weak T2COM_ISR
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|
.weak T2OVF_ISR
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|
.weak SPISTC_ISR
|
|
.weak LFRXB_ISR
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|
.weak INTT1_ISR
|
|
.weak T2RXB_ISR
|
|
.weak T2TXB_ISR
|
|
.weak T2TXC_ISR
|
|
.weak LFREOB_ISR
|
|
.weak EXCM_ISR
|
|
.weak EEREADY_ISR
|
|
.weak SPM_RDY_ISR
|
|
|
|
.set INT0_ISR, Default_IRQ_handler
|
|
.set INT1_ISR, Default_IRQ_handler
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|
.set PCINT0_ISR, Default_IRQ_handler
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.set PCINT1_ISR, Default_IRQ_handler
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|
.set PCINT2_ISR, Default_IRQ_handler
|
|
.set INTVM_ISR, Default_IRQ_handler
|
|
.set SENINT_ISR, Default_IRQ_handler
|
|
.set INTT0_ISR, Default_IRQ_handler
|
|
.set LFWP_ISR, Default_IRQ_handler
|
|
.set T3CAP_ISR, Default_IRQ_handler
|
|
.set T3COMA_ISR, Default_IRQ_handler
|
|
.set T3COMB_ISR, Default_IRQ_handler
|
|
.set T3OVF_ISR, Default_IRQ_handler
|
|
.set T2CAP_ISR, Default_IRQ_handler
|
|
.set T2COM_ISR, Default_IRQ_handler
|
|
.set T2OVF_ISR, Default_IRQ_handler
|
|
.set SPISTC_ISR, Default_IRQ_handler
|
|
.set LFRXB_ISR, Default_IRQ_handler
|
|
.set INTT1_ISR, Default_IRQ_handler
|
|
.set T2RXB_ISR, Default_IRQ_handler
|
|
.set T2TXB_ISR, Default_IRQ_handler
|
|
.set T2TXC_ISR, Default_IRQ_handler
|
|
.set LFREOB_ISR, Default_IRQ_handler
|
|
.set EXCM_ISR, Default_IRQ_handler
|
|
.set EEREADY_ISR, Default_IRQ_handler
|
|
.set SPM_RDY_ISR, Default_IRQ_handler
|
|
end;
|
|
|
|
end.
|