mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-05-14 12:32:38 +02:00
a4fde73649
* changed command line options meanings for optimizer:
O2 now means peepholopts, CSE and register renaming in 1 pass
O3 is the same, but repeated until no further optimizations are
possible or until 5 passes have been done (to avoid endless loops)
* changed aopt386 so it does this looping
* added some procedures from csopt386 to the interface because they're
used by rropt386 as well
* some changes to csopt386 and daopt386 so that newly added instructions
by the CSE get optimizer info (they were simply skipped previously),
this fixes some bugs
351 lines
11 KiB
ObjectPascal
351 lines
11 KiB
ObjectPascal
{
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$Id$
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Copyright (c) 1998-2000 by Jonas Maebe, member of the Free Pascal
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development team
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This unit contains register renaming functionality
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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Unit rrOpt386;
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{$i defines.inc}
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Interface
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Uses aasm;
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procedure doRenaming(asml: paasmoutput; first, last: pai);
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Implementation
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Uses
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{$ifdef replaceregdebug}cutils,{$endif}
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verbose,globals,cpubase,cpuasm,daopt386,csopt386,tgeni386;
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function canBeFirstSwitch(p: paicpu; reg: tregister): boolean;
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{ checks whether an operation on reg can be switched to another reg without an }
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{ additional mov, e.g. "addl $4,%reg1" can be changed to "leal 4(%reg1),%reg2" }
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begin
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canBeFirstSwitch := false;
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case p^.opcode of
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A_MOV,A_MOVZX,A_MOVSX,A_LEA:
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canBeFirstSwitch :=
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(p^.oper[1].typ = top_reg) and
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(reg32(p^.oper[1].reg) = reg);
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A_IMUL:
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canBeFirstSwitch :=
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(p^.ops >= 2) and
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(reg32(p^.oper[p^.ops-1].reg) = reg);
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A_INC,A_DEC,A_SUB,A_ADD:
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canBeFirstSwitch :=
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(p^.oper[1].typ = top_reg) and
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(p^.opsize = S_L) and
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(reg32(p^.oper[1].reg) = reg) and
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(p^.oper[0].typ <> top_ref) and
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((p^.opcode <> A_SUB) or
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(p^.oper[0].typ = top_const));
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A_SHL:
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canBeFirstSwitch :=
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(p^.opsize = S_L) and
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(p^.oper[1].typ = top_reg) and
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(p^.oper[1].reg = reg) and
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(p^.oper[0].typ = top_const) and
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(p^.oper[0].val in [1,2,3]);
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end;
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end;
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procedure switchReg(var reg: tregister; reg1, reg2: tregister);
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begin
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if reg = reg1 then
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reg := reg2
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else if reg = reg2 then
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reg := reg1
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else if reg = regtoreg8(reg1) then
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reg := regtoreg8(reg2)
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else if reg = regtoreg8(reg2) then
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reg := regtoreg8(reg1)
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else if reg = regtoreg16(reg1) then
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reg := regtoreg16(reg2)
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else if reg = regtoreg16(reg2) then
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reg := regtoreg16(reg1)
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end;
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procedure switchOp(var op: toper; reg1, reg2: tregister);
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begin
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case op.typ of
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top_reg:
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switchReg(op.reg,reg1,reg2);
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top_ref:
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begin
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switchReg(op.ref^.base,reg1,reg2);
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switchReg(op.ref^.index,reg1,reg2);
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end;
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end;
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end;
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procedure doSwitchReg(hp: paicpu; reg1,reg2: tregister);
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var
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opCount: longint;
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begin
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for opCount := 0 to hp^.ops-1 do
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switchOp(hp^.oper[opCount],reg1,reg2);
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end;
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procedure doFirstSwitch(p: paicpu; reg1, reg2: tregister);
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var
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tmpRef: treference;
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begin
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case p^.opcode of
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A_MOV,A_MOVZX,A_MOVSX,A_LEA:
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begin
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changeOp(p^.oper[1],reg1,reg2);
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changeOp(p^.oper[0],reg2,reg1);
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end;
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A_IMUL:
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begin
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p^.ops := 3;
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p^.loadreg(2,p^.oper[1].reg);
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changeOp(p^.oper[2],reg1,reg2);
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end;
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A_INC,A_DEC:
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begin
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reset_reference(tmpref);
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tmpref.base := reg1;
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case p^.opcode of
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A_INC:
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tmpref.offset := 1;
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A_DEC:
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tmpref.offset := -1;
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end;
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p^.ops := 2;
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p^.opcode := A_LEA;
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p^.loadreg(1,reg2);
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p^.loadref(0,newreference(tmpref));
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end;
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A_SUB,A_ADD:
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begin
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reset_reference(tmpref);
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tmpref.base := reg1;
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case p^.oper[0].typ of
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top_const:
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begin
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tmpref.offset := p^.oper[0].val;
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if p^.opcode = A_SUB then
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tmpref.offset := - tmpRef.offset;
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end;
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top_symbol:
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tmpref.symbol := p^.oper[0].sym;
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top_reg:
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begin
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tmpref.index := p^.oper[0].reg;
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tmpref.scalefactor := 1;
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end;
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else internalerror(200010031);
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end;
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p^.opcode := A_LEA;
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p^.loadref(0,newreference(tmpref));
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p^.loadreg(1,reg2);
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end;
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A_SHL:
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begin
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reset_reference(tmpref);
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tmpref.base := reg1;
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tmpref.scalefactor := 1 shl p^.oper[0].val;
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p^.opcode := A_LEA;
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p^.loadref(0,newreference(tmpref));
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p^.loadreg(1,reg2);
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end;
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else internalerror(200010032);
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end;
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end;
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function switchRegs(asml: paasmoutput; reg1, reg2: tregister; start: pai): Boolean;
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{ change movl %reg1,%reg2 ... bla ... to ... bla with reg1 and reg2 switched }
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var
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endP, hp: pai;
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switchDone, switchLast, tmpResult, sequenceEnd, reg1Modified, reg2Modified: boolean;
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reg1StillUsed, reg2StillUsed, isInstruction: boolean;
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begin
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switchRegs := false;
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tmpResult := true;
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sequenceEnd := false;
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reg1Modified := false;
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reg2Modified := false;
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endP := start;
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while tmpResult and not sequenceEnd do
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begin
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tmpResult :=
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getNextInstruction(endP,endP);
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If tmpResult and
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not ppaiprop(endP^.optinfo)^.canBeRemoved then
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begin
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{ if the newReg gets stored back to the oldReg, we can change }
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{ "mov %oldReg,%newReg; <operations on %newReg>; mov %newReg, }
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{ %oldReg" to "<operations on %oldReg>" }
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switchLast := storeBack(endP,reg1,reg2);
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reg1StillUsed := reg1 in ppaiprop(endP^.optinfo)^.usedregs;
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reg2StillUsed := reg2 in ppaiprop(endP^.optinfo)^.usedregs;
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isInstruction := endP^.typ = ait_instruction;
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sequenceEnd :=
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switchLast or
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{ if both registers are released right before an instruction }
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{ that contains hardcoded regs, it's ok too }
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(not reg1StillUsed and not reg2StillUsed) or
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{ no support for (i)div, mul and imul with hardcoded operands }
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(((not isInstruction) or
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noHardCodedRegs(paicpu(endP),reg1,reg2)) and
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(not reg1StillUsed or
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(isInstruction and findRegDealloc(reg1,endP) and
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regLoadedWithNewValue(reg1,false,paicpu(endP)))) and
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(not reg2StillUsed or
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(isInstruction and findRegDealloc(reg2,endP) and
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regLoadedWithNewValue(reg2,false,paicpu(endP)))));
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{ we can't switch reg1 and reg2 in something like }
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{ movl %reg1,%reg2 }
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{ movl (%reg2),%reg2 }
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{ movl 4(%reg1),%reg1 }
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if reg2Modified and not(reg1Modified) and
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regReadByInstruction(reg1,endP) then
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begin
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tmpResult := false;
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break
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end;
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if not reg1Modified then
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begin
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reg1Modified := regModifiedByInstruction(reg1,endP);
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if reg1Modified and not canBeFirstSwitch(paicpu(endP),reg1) then
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begin
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tmpResult := false;
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break;
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end;
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end;
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if not reg2Modified then
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reg2Modified := regModifiedByInstruction(reg2,endP);
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if sequenceEnd then
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break;
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tmpResult :=
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(endP^.typ <> ait_label) and
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((not isInstruction) or
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(NoHardCodedRegs(paicpu(endP),reg1,reg2) and
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RegSizesOk(reg1,reg2,paicpu(endP))));
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end;
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end;
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if tmpResult and sequenceEnd then
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begin
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switchRegs := true;
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reg1Modified := false;
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reg2Modified := false;
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getNextInstruction(start,hp);
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while hp <> endP do
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begin
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if (not ppaiprop(hp^.optinfo)^.canberemoved) and
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(hp^.typ = ait_instruction) then
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begin
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switchDone := false;
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if not reg1Modified then
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begin
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reg1Modified := regModifiedByInstruction(reg1,hp);
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if reg1Modified then
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begin
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doFirstSwitch(paicpu(hp),reg1,reg2);
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switchDone := true;
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end;
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end;
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if not switchDone then
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if reg1Modified then
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doSwitchReg(paicpu(hp),reg1,reg2)
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else
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doReplaceReg(paicpu(hp),reg2,reg1);
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end;
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getNextInstruction(hp,hp);
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end;
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if switchLast then
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doSwitchReg(paicpu(hp),reg1,reg2)
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else getLastInstruction(hp,hp);
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allocRegBetween(asmL,reg1,start,hp);
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allocRegBetween(asmL,reg2,start,hp);
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end;
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end;
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procedure doRenaming(asml: paasmoutput; first, last: pai);
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var
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p: pai;
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begin
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p := First;
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SkipHead(p);
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while p <> last do
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begin
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case p^.typ of
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ait_instruction:
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begin
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case paicpu(p)^.opcode of
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A_MOV:
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begin
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if not(ppaiprop(p^.optinfo)^.canBeRemoved) and
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(paicpu(p)^.oper[0].typ = top_reg) and
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(paicpu(p)^.oper[1].typ = top_reg) and
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(paicpu(p)^.opsize = S_L) and
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(paicpu(p)^.oper[0].reg in (usableregs+[R_EDI])) and
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(paicpu(p)^.oper[1].reg in (usableregs+[R_EDI])) then
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if switchRegs(asml,paicpu(p)^.oper[0].reg,
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paicpu(p)^.oper[1].reg,p) then
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begin
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{ getnextinstruction(p,hp);
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asmL^.remove(p);
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dispose(p,done);
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p := hp;
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continue }
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ppaiprop(p^.optinfo)^.canBeRemoved := true;
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end;
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end;
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end;
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end;
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end;
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getNextInstruction(p,p);
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end;
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end;
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End.
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{
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$Log$
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Revision 1.1 2000-10-24 10:40:54 jonas
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+ register renaming ("fixes" bug1088)
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* changed command line options meanings for optimizer:
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O2 now means peepholopts, CSE and register renaming in 1 pass
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O3 is the same, but repeated until no further optimizations are
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possible or until 5 passes have been done (to avoid endless loops)
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* changed aopt386 so it does this looping
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* added some procedures from csopt386 to the interface because they're
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used by rropt386 as well
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* some changes to csopt386 and daopt386 so that newly added instructions
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by the CSE get optimizer info (they were simply skipped previously),
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this fixes some bugs
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|
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}
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