Jonas Maebe a637fbe596 * moved all g_exception_*() methods to hlcgobj and cleaned them up (no more ... hardcoded registers for the most part) + added extra g_exception_discard_reason() that can be called when we only want to get rid of the currently pushed exception reason, and don't have to load it (so it can do nothing on platforms that don't use push/pop) git-svn-id: branches/hlcgllvm@28481 -		2014-08-19 20:22:24 +00:00
..
aoptcpu.pas
aoptcpub.pas
aoptcpud.pas
cgcpu.pas	* moved all g_exception_*() methods to hlcgobj and cleaned them up (no more	2014-08-19 20:22:24 +00:00
cpubase.inc
cpuinfo.pas	* Included cs_opt_peephole into genericlevel1optimizerswitches, so it is re-enabled for all targets after r27106.	2014-03-15 21:23:29 +00:00
cpunode.pas	+ generate the stack segment for i8086 far data memory models from within fpc	2014-05-27 23:29:50 +00:00
cpupara.pas	* synchronized with trunk up to r27758	2014-05-12 16:12:34 +00:00
cpupi.pas
cputarg.pas
hlcgcpu.pas	* moved all g_exception_*() methods to hlcgobj and cleaned them up (no more	2014-08-19 20:22:24 +00:00
i8086att.inc	* x86: Completely skip instructions that do not exist for target CPU bit width. The existing behavior of writing mnemonics and properties but no encoding allows an invalid instruction to be recognized by assembler reader or even generated by compiler, but it but won't assemble anyway.	2014-06-11 22:31:40 +00:00
i8086atts.inc	* x86: Completely skip instructions that do not exist for target CPU bit width. The existing behavior of writing mnemonics and properties but no encoding allows an invalid instruction to be recognized by assembler reader or even generated by compiler, but it but won't assemble anyway.	2014-06-11 22:31:40 +00:00
i8086int.inc	* x86: Completely skip instructions that do not exist for target CPU bit width. The existing behavior of writing mnemonics and properties but no encoding allows an invalid instruction to be recognized by assembler reader or even generated by compiler, but it but won't assemble anyway.	2014-06-11 22:31:40 +00:00
i8086nop.inc	+ prove of concept how FMA4 could be supported in inline assembler	2014-03-20 21:25:38 +00:00
i8086op.inc	* x86: Completely skip instructions that do not exist for target CPU bit width. The existing behavior of writing mnemonics and properties but no encoding allows an invalid instruction to be recognized by assembler reader or even generated by compiler, but it but won't assemble anyway.	2014-06-11 22:31:40 +00:00
i8086prop.inc	* x86: Completely skip instructions that do not exist for target CPU bit width. The existing behavior of writing mnemonics and properties but no encoding allows an invalid instruction to be recognized by assembler reader or even generated by compiler, but it but won't assemble anyway.	2014-06-11 22:31:40 +00:00
i8086tab.inc	+ prove of concept how FMA4 could be supported in inline assembler	2014-03-20 21:25:38 +00:00
n8086add.pas	* is_farpointer and is_hugepointer moved from defutil to symcpu	2014-08-06 20:32:41 +00:00
n8086cal.pas	* synchronized with trunk up to r27758	2014-05-12 16:12:34 +00:00
n8086cnv.pas	* converted tcgtypeconvnode.second_nil_to_methodprocvar to the high level code	2014-04-28 01:05:14 +00:00
n8086con.pas	* moved x86-specific tpointerdef functionality to architecture-specific	2014-03-30 21:04:36 +00:00
n8086inl.pas	* is_farpointer and is_hugepointer moved from defutil to symcpu	2014-08-06 20:32:41 +00:00
n8086ld.pas	* fixed nested access to parent local variables in i8086 far data memory models	2014-03-30 17:50:35 +00:00
n8086mat.pas
n8086mem.pas	* synchronised with trunk up till r28402	2014-08-13 16:04:30 +00:00
n8086tcon.pas	* synchronised with trunk up till r28402	2014-08-13 16:04:30 +00:00
n8086util.pas	+ added heapmax support to the $M directive on i8086-msdos. It is currently	2014-06-23 20:17:17 +00:00
r8086ari.inc
r8086att.inc
r8086con.inc
r8086dwrf.inc
r8086int.inc
r8086iri.inc
r8086nasm.inc
r8086nor.inc
r8086nri.inc
r8086num.inc
r8086ot.inc
r8086rni.inc
r8086sri.inc
r8086stab.inc
r8086std.inc
ra8086att.pas
ra8086int.pas
rgcpu.pas	* synchronized with trunk up to r27758	2014-05-12 16:12:34 +00:00
symcpu.pas	* reimplemented r28329 in a different way, as suggested by Jonas	2014-08-07 19:36:52 +00:00
tgcpu.pas	+ set ref.segment to NR_SS for all temps/localvars on i8086. This allows the	2014-05-01 21:18:47 +00:00