mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-10-31 06:11:29 +01:00
360 lines
15 KiB
ObjectPascal
360 lines
15 KiB
ObjectPascal
unit ATmega32A;
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interface
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var
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// EEPROM
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EEAR : word absolute $00+$3E; // EEPROM Read/Write Access Bytes
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EEARL : byte absolute $00+$3E; // EEPROM Read/Write Access Bytes
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EEARH : byte absolute $00+$3E+1; // EEPROM Read/Write Access Bytes
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EEDR : byte absolute $00+$3D; // EEPROM Data Register
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EECR : byte absolute $00+$3C; // EEPROM Control Register
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// WATCHDOG
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WDTCR : byte absolute $00+$41; // Watchdog Timer Control Register
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// EXTERNAL_INTERRUPT
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GICR : byte absolute $00+$5B; // General Interrupt Control Register
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GIFR : byte absolute $00+$5A; // General Interrupt Flag Register
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MCUCR : byte absolute $00+$55; // General Interrupt Control Register
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MCUCSR : byte absolute $00+$54; // MCU Control And Status Register
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// TIMER_COUNTER_0
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TCCR0 : byte absolute $00+$53; // Timer/Counter Control Register
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TCNT0 : byte absolute $00+$52; // Timer/Counter Register
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OCR0 : byte absolute $00+$5C; // Output Compare Register
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TIMSK : byte absolute $00+$59; // Timer/Counter Interrupt Mask Register
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TIFR : byte absolute $00+$58; // Timer/Counter Interrupt Flag register
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// TIMER_COUNTER_2
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TCCR2 : byte absolute $00+$45; // Timer/Counter2 Control Register
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TCNT2 : byte absolute $00+$44; // Timer/Counter2
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OCR2 : byte absolute $00+$43; // Timer/Counter2 Output Compare Register
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ASSR : byte absolute $00+$42; // Asynchronous Status Register
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// TIMER_COUNTER_1
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TCCR1A : byte absolute $00+$4F; // Timer/Counter1 Control Register A
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TCCR1B : byte absolute $00+$4E; // Timer/Counter1 Control Register B
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TCNT1 : word absolute $00+$4C; // Timer/Counter1 Bytes
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TCNT1L : byte absolute $00+$4C; // Timer/Counter1 Bytes
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TCNT1H : byte absolute $00+$4C+1; // Timer/Counter1 Bytes
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OCR1A : word absolute $00+$4A; // Timer/Counter1 Output Compare Register Bytes
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OCR1AL : byte absolute $00+$4A; // Timer/Counter1 Output Compare Register Bytes
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OCR1AH : byte absolute $00+$4A+1; // Timer/Counter1 Output Compare Register Bytes
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OCR1B : word absolute $00+$48; // Timer/Counter1 Output Compare Register Bytes
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OCR1BL : byte absolute $00+$48; // Timer/Counter1 Output Compare Register Bytes
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OCR1BH : byte absolute $00+$48+1; // Timer/Counter1 Output Compare Register Bytes
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ICR1 : word absolute $00+$46; // Timer/Counter1 Input Capture Register Bytes
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ICR1L : byte absolute $00+$46; // Timer/Counter1 Input Capture Register Bytes
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ICR1H : byte absolute $00+$46+1; // Timer/Counter1 Input Capture Register Bytes
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// SPI
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SPDR : byte absolute $00+$2F; // SPI Data Register
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SPSR : byte absolute $00+$2E; // SPI Status Register
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SPCR : byte absolute $00+$2D; // SPI Control Register
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// USART
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UDR : byte absolute $00+$2C; // USART I/O Data Register
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UCSRA : byte absolute $00+$2B; // USART Control and Status Register A
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UCSRB : byte absolute $00+$2A; // USART Control and Status Register B
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UCSRC : byte absolute $00+$40; // USART Control and Status Register C
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UBRRH : byte absolute $00+$40; // USART Baud Rate Register Hight Byte
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UBRRL : byte absolute $00+$29; // USART Baud Rate Register Low Byte
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// ANALOG_COMPARATOR
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SFIOR : byte absolute $00+$50; // Special Function IO Register
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ACSR : byte absolute $00+$28; // Analog Comparator Control And Status Register
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// AD_CONVERTER
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ADMUX : byte absolute $00+$27; // The ADC multiplexer Selection Register
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ADCSRA : byte absolute $00+$26; // The ADC Control and Status register
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ADC : word absolute $00+$24; // ADC Data Register Bytes
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ADCL : byte absolute $00+$24; // ADC Data Register Bytes
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ADCH : byte absolute $00+$24+1; // ADC Data Register Bytes
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// PORTA
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PORTA : byte absolute $00+$3B; // Port A Data Register
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DDRA : byte absolute $00+$3A; // Port A Data Direction Register
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PINA : byte absolute $00+$39; // Port A Input Pins
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// PORTB
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PORTB : byte absolute $00+$38; // Port B Data Register
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DDRB : byte absolute $00+$37; // Port B Data Direction Register
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PINB : byte absolute $00+$36; // Port B Input Pins
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// PORTC
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PORTC : byte absolute $00+$35; // Port C Data Register
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DDRC : byte absolute $00+$34; // Port C Data Direction Register
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PINC : byte absolute $00+$33; // Port C Input Pins
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// PORTD
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PORTD : byte absolute $00+$32; // Port D Data Register
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DDRD : byte absolute $00+$31; // Port D Data Direction Register
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PIND : byte absolute $00+$30; // Port D Input Pins
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// CPU
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SREG : byte absolute $00+$5F; // Status Register
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SP : word absolute $00+$5D; // Stack Pointer
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SPL : byte absolute $00+$5D; // Stack Pointer
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SPH : byte absolute $00+$5D+1; // Stack Pointer
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OSCCAL : byte absolute $00+$51; // Oscillator Calibration Value
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// BOOT_LOAD
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SPMCR : byte absolute $00+$57; // Store Program Memory Control Register
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// TWI
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TWBR : byte absolute $00+$20; // TWI Bit Rate register
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TWCR : byte absolute $00+$56; // TWI Control Register
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TWSR : byte absolute $00+$21; // TWI Status Register
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TWDR : byte absolute $00+$23; // TWI Data register
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TWAR : byte absolute $00+$22; // TWI (Slave) Address register
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const
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// EECR
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EERIE = 3; // EEPROM Ready Interrupt Enable
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EEMWE = 2; // EEPROM Master Write Enable
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EEWE = 1; // EEPROM Write Enable
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EERE = 0; // EEPROM Read Enable
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// WDTCR
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WDTOE = 4; // RW
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WDE = 3; // Watch Dog Enable
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WDP = 0; // Watch Dog Timer Prescaler bits
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// GICR
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INT = 6; // External Interrupt Request 1 Enable
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INT2 = 5; // External Interrupt Request 2 Enable
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IVSEL = 1; // Interrupt Vector Select
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IVCE = 0; // Interrupt Vector Change Enable
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// GIFR
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INTF = 6; // External Interrupt Flags
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INTF2 = 5; // External Interrupt Flag 2
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// MCUCR
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ISC1 = 2; // Interrupt Sense Control 1 Bits
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ISC0 = 0; // Interrupt Sense Control 0 Bits
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// MCUCSR
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ISC2 = 6; // Interrupt Sense Control 2
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// TCCR0
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FOC0 = 7; // Force Output Compare
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WGM00 = 6; // Waveform Generation Mode
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COM0 = 4; // Compare Match Output Modes
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WGM01 = 3; // Waveform Generation Mode 1
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CS0 = 0; // Clock Selects
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// TIMSK
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OCIE0 = 1; // Timer/Counter0 Output Compare Match Interrupt register
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TOIE0 = 0; // Timer/Counter0 Overflow Interrupt Enable
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// TIFR
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OCF0 = 1; // Output Compare Flag 0
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TOV0 = 0; // Timer/Counter0 Overflow Flag
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// TIMSK
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OCIE2 = 7; // Timer/Counter2 Output Compare Match Interrupt Enable
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TOIE2 = 6; // Timer/Counter2 Overflow Interrupt Enable
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// TIFR
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OCF2 = 7; // Output Compare Flag 2
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TOV2 = 6; // Timer/Counter2 Overflow Flag
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// TCCR2
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FOC2 = 7; // Force Output Compare
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WGM20 = 6; // Pulse Width Modulator Enable
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COM2 = 4; // Compare Output Mode bits
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WGM21 = 3; // Clear Timer/Counter2 on Compare Match
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CS2 = 0; // Clock Select bits
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// ASSR
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AS2 = 3; // Asynchronous Timer/counter2
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TCN2UB = 2; // Timer/Counter2 Update Busy
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OCR2UB = 1; // Output Compare Register2 Update Busy
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TCR2UB = 0; // Timer/counter Control Register2 Update Busy
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// TIMSK
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TICIE1 = 5; // Timer/Counter1 Input Capture Interrupt Enable
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OCIE1A = 4; // Timer/Counter1 Output CompareA Match Interrupt Enable
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OCIE1B = 3; // Timer/Counter1 Output CompareB Match Interrupt Enable
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TOIE1 = 2; // Timer/Counter1 Overflow Interrupt Enable
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// TIFR
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ICF1 = 5; // Input Capture Flag 1
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OCF1A = 4; // Output Compare Flag 1A
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OCF1B = 3; // Output Compare Flag 1B
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TOV1 = 2; // Timer/Counter1 Overflow Flag
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// TCCR1A
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COM1A = 6; // Compare Output Mode 1A, bits
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COM1B = 4; // Compare Output Mode 1B, bits
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FOC1A = 3; // Force Output Compare 1A
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FOC1B = 2; // Force Output Compare 1B
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WGM1 = 0; // Waveform Generation Mode
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// TCCR1B
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ICNC1 = 7; // Input Capture 1 Noise Canceler
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ICES1 = 6; // Input Capture 1 Edge Select
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CS1 = 0; // Prescaler source of Timer/Counter 1
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// SPSR
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SPIF = 7; // SPI Interrupt Flag
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WCOL = 6; // Write Collision Flag
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SPI2X = 0; // Double SPI Speed Bit
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// SPCR
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SPIE = 7; // SPI Interrupt Enable
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SPE = 6; // SPI Enable
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DORD = 5; // Data Order
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MSTR = 4; // Master/Slave Select
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CPOL = 3; // Clock polarity
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CPHA = 2; // Clock Phase
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SPR = 0; // SPI Clock Rate Selects
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// UCSRA
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RXC = 7; // USART Receive Complete
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TXC = 6; // USART Transmitt Complete
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UDRE = 5; // USART Data Register Empty
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FE = 4; // Framing Error
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DOR = 3; // Data overRun
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UPE = 2; // Parity Error
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U2X = 1; // Double the USART transmission speed
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MPCM = 0; // Multi-processor Communication Mode
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// UCSRB
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RXCIE = 7; // RX Complete Interrupt Enable
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TXCIE = 6; // TX Complete Interrupt Enable
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UDRIE = 5; // USART Data register Empty Interrupt Enable
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RXEN = 4; // Receiver Enable
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TXEN = 3; // Transmitter Enable
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UCSZ2 = 2; // Character Size
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RXB8 = 1; // Receive Data Bit 8
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TXB8 = 0; // Transmit Data Bit 8
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// UCSRC
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URSEL = 7; // Register Select
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UMSEL = 6; // USART Mode Select
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UPM = 4; // Parity Mode Bits
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USBS = 3; // Stop Bit Select
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UCSZ = 1; // Character Size
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UCPOL = 0; // Clock Polarity
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// SFIOR
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ACME = 3; // Analog Comparator Multiplexer Enable
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// ACSR
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ACD = 7; // Analog Comparator Disable
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ACBG = 6; // Analog Comparator Bandgap Select
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ACO = 5; // Analog Compare Output
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ACI = 4; // Analog Comparator Interrupt Flag
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ACIE = 3; // Analog Comparator Interrupt Enable
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ACIC = 2; // Analog Comparator Input Capture Enable
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ACIS = 0; // Analog Comparator Interrupt Mode Select bits
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// ADMUX
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REFS = 6; // Reference Selection Bits
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ADLAR = 5; // Left Adjust Result
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MUX = 0; // Analog Channel and Gain Selection Bits
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// ADCSRA
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ADEN = 7; // ADC Enable
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ADSC = 6; // ADC Start Conversion
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ADATE = 5; // When this bit is written to one,the Timer/Counter2 prescaler will be reset.The bit will be cleared by hardware after the operation is performed.Writing a zero to this bit will have no effect.This bit will always be read as zero if Timer/Counter2 is clocked by the internal CPU clock.If this bit is written when Timer/Counter2 is operating in asynchronous mode,the bit will remain one until the prescaler has been reset.
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ADIF = 4; // ADC Interrupt Flag
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ADIE = 3; // ADC Interrupt Enable
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ADPS = 0; // ADC Prescaler Select Bits
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// SFIOR
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ADTS = 5; // ADC Auto Trigger Sources
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// SREG
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I = 7; // Global Interrupt Enable
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T = 6; // Bit Copy Storage
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H = 5; // Half Carry Flag
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S = 4; // Sign Bit
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V = 3; // Two's Complement Overflow Flag
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N = 2; // Negative Flag
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Z = 1; // Zero Flag
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C = 0; // Carry Flag
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// MCUCR
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SE = 7; // Sleep Enable
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SM = 4; // Sleep Mode Select
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// MCUCSR
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JTD = 7; // JTAG Interface Disable
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JTRF = 4; // JTAG Reset Flag
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WDRF = 3; // Watchdog Reset Flag
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BORF = 2; // Brown-out Reset Flag
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EXTRF = 1; // External Reset Flag
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PORF = 0; // Power-on reset flag
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// SPMCR
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SPMIE = 7; // SPM Interrupt Enable
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RWWSB = 6; // Read While Write Section Busy
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RWWSRE = 4; // Read While Write secion read enable
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BLBSET = 3; // Boot Lock Bit Set
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PGWRT = 2; // Page Write
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PGERS = 1; // Page Erase
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SPMEN = 0; // Store Program Memory Enable
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// TWCR
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TWINT = 7; // TWI Interrupt Flag
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TWEA = 6; // TWI Enable Acknowledge Bit
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TWSTA = 5; // TWI Start Condition Bit
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TWSTO = 4; // TWI Stop Condition Bit
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TWWC = 3; // TWI Write Collition Flag
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TWEN = 2; // TWI Enable Bit
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TWIE = 0; // TWI Interrupt Enable
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// TWSR
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TWS = 3; // TWI Status
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TWPS = 0; // TWI Prescaler bits
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implementation
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{$i avrcommon.inc}
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procedure INT0_ISR; external name 'INT0_ISR'; // Interrupt 1 External Interrupt Request 0
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procedure INT1_ISR; external name 'INT1_ISR'; // Interrupt 2 External Interrupt Request 1
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procedure INT2_ISR; external name 'INT2_ISR'; // Interrupt 3 External Interrupt Request 2
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procedure TIMER2_COMP_ISR; external name 'TIMER2_COMP_ISR'; // Interrupt 4 Timer/Counter2 Compare Match
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procedure TIMER2_OVF_ISR; external name 'TIMER2_OVF_ISR'; // Interrupt 5 Timer/Counter2 Overflow
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procedure TIMER1_CAPT_ISR; external name 'TIMER1_CAPT_ISR'; // Interrupt 6 Timer/Counter1 Capture Event
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procedure TIMER1_COMPA_ISR; external name 'TIMER1_COMPA_ISR'; // Interrupt 7 Timer/Counter1 Compare Match A
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procedure TIMER1_COMPB_ISR; external name 'TIMER1_COMPB_ISR'; // Interrupt 8 Timer/Counter1 Compare Match B
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procedure TIMER1_OVF_ISR; external name 'TIMER1_OVF_ISR'; // Interrupt 9 Timer/Counter1 Overflow
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procedure TIMER0_COMP_ISR; external name 'TIMER0_COMP_ISR'; // Interrupt 10 Timer/Counter0 Compare Match
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procedure TIMER0_OVF_ISR; external name 'TIMER0_OVF_ISR'; // Interrupt 11 Timer/Counter0 Overflow
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procedure SPI__STC_ISR; external name 'SPI__STC_ISR'; // Interrupt 12 Serial Transfer Complete
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procedure USART__RXC_ISR; external name 'USART__RXC_ISR'; // Interrupt 13 USART, Rx Complete
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procedure USART__UDRE_ISR; external name 'USART__UDRE_ISR'; // Interrupt 14 USART Data Register Empty
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procedure USART__TXC_ISR; external name 'USART__TXC_ISR'; // Interrupt 15 USART, Tx Complete
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procedure ADC_ISR; external name 'ADC_ISR'; // Interrupt 16 ADC Conversion Complete
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procedure EE_RDY_ISR; external name 'EE_RDY_ISR'; // Interrupt 17 EEPROM Ready
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procedure ANA_COMP_ISR; external name 'ANA_COMP_ISR'; // Interrupt 18 Analog Comparator
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procedure TWI_ISR; external name 'TWI_ISR'; // Interrupt 19 2-wire Serial Interface
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procedure SPM_RDY_ISR; external name 'SPM_RDY_ISR'; // Interrupt 20 Store Program Memory Ready
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procedure _FPC_start; assembler; nostackframe; noreturn; public name '_START'; section '.init';
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asm
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jmp __dtors_end
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jmp INT0_ISR
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jmp INT1_ISR
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jmp INT2_ISR
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jmp TIMER2_COMP_ISR
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jmp TIMER2_OVF_ISR
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jmp TIMER1_CAPT_ISR
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jmp TIMER1_COMPA_ISR
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jmp TIMER1_COMPB_ISR
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jmp TIMER1_OVF_ISR
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jmp TIMER0_COMP_ISR
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jmp TIMER0_OVF_ISR
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jmp SPI__STC_ISR
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jmp USART__RXC_ISR
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jmp USART__UDRE_ISR
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jmp USART__TXC_ISR
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jmp ADC_ISR
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jmp EE_RDY_ISR
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jmp ANA_COMP_ISR
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jmp TWI_ISR
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jmp SPM_RDY_ISR
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.weak INT0_ISR
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.weak INT1_ISR
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.weak INT2_ISR
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.weak TIMER2_COMP_ISR
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.weak TIMER2_OVF_ISR
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.weak TIMER1_CAPT_ISR
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.weak TIMER1_COMPA_ISR
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.weak TIMER1_COMPB_ISR
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.weak TIMER1_OVF_ISR
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.weak TIMER0_COMP_ISR
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.weak TIMER0_OVF_ISR
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.weak SPI__STC_ISR
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.weak USART__RXC_ISR
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.weak USART__UDRE_ISR
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.weak USART__TXC_ISR
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.weak ADC_ISR
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.weak EE_RDY_ISR
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.weak ANA_COMP_ISR
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.weak TWI_ISR
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.weak SPM_RDY_ISR
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.set INT0_ISR, Default_IRQ_handler
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.set INT1_ISR, Default_IRQ_handler
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.set INT2_ISR, Default_IRQ_handler
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.set TIMER2_COMP_ISR, Default_IRQ_handler
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.set TIMER2_OVF_ISR, Default_IRQ_handler
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.set TIMER1_CAPT_ISR, Default_IRQ_handler
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.set TIMER1_COMPA_ISR, Default_IRQ_handler
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.set TIMER1_COMPB_ISR, Default_IRQ_handler
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.set TIMER1_OVF_ISR, Default_IRQ_handler
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.set TIMER0_COMP_ISR, Default_IRQ_handler
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.set TIMER0_OVF_ISR, Default_IRQ_handler
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.set SPI__STC_ISR, Default_IRQ_handler
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.set USART__RXC_ISR, Default_IRQ_handler
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.set USART__UDRE_ISR, Default_IRQ_handler
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.set USART__TXC_ISR, Default_IRQ_handler
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.set ADC_ISR, Default_IRQ_handler
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.set EE_RDY_ISR, Default_IRQ_handler
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.set ANA_COMP_ISR, Default_IRQ_handler
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.set TWI_ISR, Default_IRQ_handler
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.set SPM_RDY_ISR, Default_IRQ_handler
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end;
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end.
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