mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-10-31 08:31:49 +01:00
565 lines
20 KiB
ObjectPascal
565 lines
20 KiB
ObjectPascal
unit ATmega48PB;
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interface
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var
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PINB: byte absolute $23; // Port B Input Pins
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DDRB: byte absolute $24; // Port B Data Direction Register
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PORTB: byte absolute $25; // Port B Data Register
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PINC: byte absolute $26; // Port C Input Pins
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DDRC: byte absolute $27; // Port C Data Direction Register
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PORTC: byte absolute $28; // Port C Data Register
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PIND: byte absolute $29; // Port D Input Pins
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DDRD: byte absolute $2A; // Port D Data Direction Register
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PORTD: byte absolute $2B; // Port D Data Register
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PINE: byte absolute $2C; // Port E Input Pins
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DDRE: byte absolute $2D; // Port E Data Direction Register
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PORTE: byte absolute $2E; // Port E Data Register
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TIFR0: byte absolute $35; // Timer/Counter0 Interrupt Flag register
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TIFR1: byte absolute $36; // Timer/Counter Interrupt Flag register
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TIFR2: byte absolute $37; // Timer/Counter Interrupt Flag Register
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PCIFR: byte absolute $3B; // Pin Change Interrupt Flag Register
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EIFR: byte absolute $3C; // External Interrupt Flag Register
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EIMSK: byte absolute $3D; // External Interrupt Mask Register
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GPIOR0: byte absolute $3E; // General Purpose I/O Register 0
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EECR: byte absolute $3F; // EEPROM Control Register
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EEDR: byte absolute $40; // EEPROM Data Register
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EEARL: byte absolute $41; // EEPROM Address Register Low Byte
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GTCCR: byte absolute $43; // General Timer/Counter Control Register
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TCCR0A: byte absolute $44; // Timer/Counter Control Register A
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TCCR0B: byte absolute $45; // Timer/Counter Control Register B
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TCNT0: byte absolute $46; // Timer/Counter0
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OCR0A: byte absolute $47; // Timer/Counter0 Output Compare Register
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OCR0B: byte absolute $48; // Timer/Counter0 Output Compare Register
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GPIOR1: byte absolute $4A; // General Purpose I/O Register 1
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GPIOR2: byte absolute $4B; // General Purpose I/O Register 2
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SPCR: byte absolute $4C; // SPI Control Register
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SPSR: byte absolute $4D; // SPI Status Register
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SPDR: byte absolute $4E; // SPI Data Register
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ACSRB: byte absolute $4F; // Analog Comparator Status Register B
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ACSR: byte absolute $50; // Analog Comparator Control And Status Register
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SMCR: byte absolute $53; // Sleep Mode Control Register
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MCUSR: byte absolute $54; // MCU Status Register
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MCUCR: byte absolute $55; // MCU Control Register
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SPMCSR: byte absolute $57; // Store Program Memory Control and Status Register
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SP: word absolute $5D; // Stack Pointer
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SPL: byte absolute $5D; // Stack Pointer
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SPH: byte absolute $5E; // Stack Pointer ;
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SREG: byte absolute $5F; // Status Register
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WDTCSR: byte absolute $60; // Watchdog Timer Control Register
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CLKPR: byte absolute $61; // Clock Prescale Register
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PRR: byte absolute $64; // Power Reduction Register
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OSCCAL: byte absolute $66; // Oscillator Calibration Value
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PCICR: byte absolute $68; // Pin Change Interrupt Control Register
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EICRA: byte absolute $69; // External Interrupt Control Register
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PCMSK0: byte absolute $6B; // Pin Change Mask Register 0
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PCMSK1: byte absolute $6C; // Pin Change Mask Register 1
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PCMSK2: byte absolute $6D; // Pin Change Mask Register 2
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TIMSK0: byte absolute $6E; // Timer/Counter0 Interrupt Mask Register
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TIMSK1: byte absolute $6F; // Timer/Counter Interrupt Mask Register
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TIMSK2: byte absolute $70; // Timer/Counter Interrupt Mask register
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ADC: word absolute $78; // ADC Data Register Bytes
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ADCL: byte absolute $78; // ADC Data Register Bytes
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ADCH: byte absolute $79; // ADC Data Register Bytes;
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ADCSRA: byte absolute $7A; // The ADC Control and Status register A
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ADCSRB: byte absolute $7B; // The ADC Control and Status register B
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ADMUX: byte absolute $7C; // The ADC multiplexer Selection Register
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DIDR0: byte absolute $7E; // Digital Input Disable Register
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DIDR1: byte absolute $7F; // Digital Input Disable Register 1
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TCCR1A: byte absolute $80; // Timer/Counter1 Control Register A
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TCCR1B: byte absolute $81; // Timer/Counter1 Control Register B
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TCCR1C: byte absolute $82; // Timer/Counter1 Control Register C
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TCNT1: word absolute $84; // Timer/Counter1 Bytes
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TCNT1L: byte absolute $84; // Timer/Counter1 Bytes
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TCNT1H: byte absolute $85; // Timer/Counter1 Bytes;
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ICR1: word absolute $86; // Timer/Counter1 Input Capture Register Bytes
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ICR1L: byte absolute $86; // Timer/Counter1 Input Capture Register Bytes
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ICR1H: byte absolute $87; // Timer/Counter1 Input Capture Register Bytes;
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OCR1A: word absolute $88; // Timer/Counter1 Output Compare Register Bytes
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OCR1AL: byte absolute $88; // Timer/Counter1 Output Compare Register Bytes
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OCR1AH: byte absolute $89; // Timer/Counter1 Output Compare Register Bytes;
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OCR1B: word absolute $8A; // Timer/Counter1 Output Compare Register Bytes
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OCR1BL: byte absolute $8A; // Timer/Counter1 Output Compare Register Bytes
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OCR1BH: byte absolute $8B; // Timer/Counter1 Output Compare Register Bytes;
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TCCR2A: byte absolute $B0; // Timer/Counter2 Control Register A
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TCCR2B: byte absolute $B1; // Timer/Counter2 Control Register B
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TCNT2: byte absolute $B2; // Timer/Counter2
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OCR2A: byte absolute $B3; // Timer/Counter2 Output Compare Register A
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OCR2B: byte absolute $B4; // Timer/Counter2 Output Compare Register B
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ASSR: byte absolute $B6; // Asynchronous Status Register
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TWBR: byte absolute $B8; // TWI Bit Rate register
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TWSR: byte absolute $B9; // TWI Status Register
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TWAR: byte absolute $BA; // TWI (Slave) Address register
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TWDR: byte absolute $BB; // TWI Data register
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TWCR: byte absolute $BC; // TWI Control Register
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TWAMR: byte absolute $BD; // TWI (Slave) Address Mask Register
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UCSR0A: byte absolute $C0; // USART Control and Status Register A
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UCSR0B: byte absolute $C1; // USART Control and Status Register B
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UCSR0C: byte absolute $C2; // USART Control and Status Register C
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UCSR0D: byte absolute $C3; // USART Control and Status Register D
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UBRR0: word absolute $C4; // USART Baud Rate Register Bytes
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UBRR0L: byte absolute $C4; // USART Baud Rate Register Bytes
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UBRR0H: byte absolute $C5; // USART Baud Rate Register Bytes;
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UDR0: byte absolute $C6; // USART I/O Data Register
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DEVID0: byte absolute $F0;
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DEVID1: byte absolute $F1;
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DEVID2: byte absolute $F2;
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DEVID3: byte absolute $F3;
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DEVID4: byte absolute $F4;
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DEVID5: byte absolute $F5;
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DEVID6: byte absolute $F6;
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DEVID7: byte absolute $F7;
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DEVID8: byte absolute $F8;
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const
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// Port B Data Register
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PB0 = $00;
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PB1 = $01;
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PB2 = $02;
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PB3 = $03;
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PB4 = $04;
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PB5 = $05;
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PB6 = $06;
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PB7 = $07;
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// Port C Data Register
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PC0 = $00;
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PC1 = $01;
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PC2 = $02;
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PC3 = $03;
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PC4 = $04;
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PC5 = $05;
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PC6 = $06;
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// Port D Data Register
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PD0 = $00;
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PD1 = $01;
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PD2 = $02;
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PD3 = $03;
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PD4 = $04;
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PD5 = $05;
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PD6 = $06;
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PD7 = $07;
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// Port E Data Register
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PE0 = $00;
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PE1 = $01;
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PE2 = $02;
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PE3 = $03;
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// Timer/Counter0 Interrupt Flag register
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TOV0 = $00;
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OCF0A = $01;
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OCF0B = $02;
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// Timer/Counter Interrupt Flag register
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TOV1 = $00;
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OCF1A = $01;
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OCF1B = $02;
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ICF1 = $05;
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// Timer/Counter Interrupt Flag Register
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TOV2 = $00;
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OCF2A = $01;
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OCF2B = $02;
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// Pin Change Interrupt Flag Register
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PCIF0 = $00; // Pin Change Interrupt Flags
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PCIF1 = $01; // Pin Change Interrupt Flags
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PCIF2 = $02; // Pin Change Interrupt Flags
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// External Interrupt Flag Register
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INTF0 = $00; // External Interrupt Flags
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INTF1 = $01; // External Interrupt Flags
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// External Interrupt Mask Register
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INT0 = $00; // External Interrupt Request 1 Enable
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INT1 = $01; // External Interrupt Request 1 Enable
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// EEPROM Control Register
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EERE = $00;
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EEPE = $01;
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EEMPE = $02;
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EERIE = $03;
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EEPM0 = $04; // EEPROM Programming Mode Bits
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EEPM1 = $05; // EEPROM Programming Mode Bits
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// General Timer/Counter Control Register
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PSRSYNC = $00;
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PSRASY = $01;
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TSM = $07;
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// Timer/Counter Control Register A
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WGM00 = $00; // Waveform Generation Mode
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WGM01 = $01; // Waveform Generation Mode
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COM0B0 = $04; // Compare Output Mode, Fast PWm
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COM0B1 = $05; // Compare Output Mode, Fast PWm
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COM0A0 = $06; // Compare Output Mode, Phase Correct PWM Mode
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COM0A1 = $07; // Compare Output Mode, Phase Correct PWM Mode
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// Timer/Counter Control Register B
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CS00 = $00; // Clock Select
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CS01 = $01; // Clock Select
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CS02 = $02; // Clock Select
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WGM02 = $03;
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FOC0B = $06;
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FOC0A = $07;
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// SPI Control Register
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SPR0 = $00; // SPI Clock Rate Selects
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SPR1 = $01; // SPI Clock Rate Selects
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CPHA = $02;
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CPOL = $03;
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MSTR = $04;
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DORD = $05;
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SPE = $06;
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SPIE = $07;
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// SPI Status Register
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SPI2X = $00;
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WCOL = $06;
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SPIF = $07;
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// Analog Comparator Status Register B
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ACOE = $00;
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// Analog Comparator Control And Status Register
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ACIS0 = $00; // Analog Comparator Interrupt Mode Select bits
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ACIS1 = $01; // Analog Comparator Interrupt Mode Select bits
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ACIC = $02;
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ACIE = $03;
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ACI = $04;
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ACO = $05;
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ACBG = $06;
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ACD = $07;
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// Sleep Mode Control Register
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SE = $00;
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SM0 = $01; // Sleep Mode Select Bits
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SM1 = $02; // Sleep Mode Select Bits
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SM2 = $03; // Sleep Mode Select Bits
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// MCU Status Register
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PORF = $00;
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EXTRF = $01;
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BORF = $02;
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WDRF = $03;
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// MCU Control Register
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PUD = $04;
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BODSE = $05;
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BODS = $06;
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// Store Program Memory Control and Status Register
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SELFPRGEN = $00;
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PGERS = $01;
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PGWRT = $02;
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BLBSET = $03;
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RWWSRE = $04;
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RWWSB = $06;
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SPMIE = $07;
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// Status Register
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C = $00;
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Z = $01;
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N = $02;
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V = $03;
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S = $04;
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H = $05;
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T = $06;
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I = $07;
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// Watchdog Timer Control Register
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WDE = $03;
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WDCE = $04;
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WDP0 = $00; // Watchdog Timer Prescaler Bits
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WDP1 = $01; // Watchdog Timer Prescaler Bits
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WDP2 = $02; // Watchdog Timer Prescaler Bits
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WDP3 = $05; // Watchdog Timer Prescaler Bits
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WDIE = $06;
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WDIF = $07;
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// Clock Prescale Register
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CLKPS0 = $00; // Clock Prescaler Select Bits
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CLKPS1 = $01; // Clock Prescaler Select Bits
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CLKPS2 = $02; // Clock Prescaler Select Bits
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CLKPS3 = $03; // Clock Prescaler Select Bits
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CLKPCE = $07;
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// Power Reduction Register
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PRADC = $00;
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PRUSART0 = $01;
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PRSPI = $02;
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PRTIM1 = $03;
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PRTIM0 = $05;
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PRTIM2 = $06;
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PRTWI = $07;
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// Oscillator Calibration Value
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OSCCAL0 = $00; // Oscillator Calibration
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OSCCAL1 = $01; // Oscillator Calibration
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OSCCAL2 = $02; // Oscillator Calibration
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OSCCAL3 = $03; // Oscillator Calibration
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OSCCAL4 = $04; // Oscillator Calibration
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OSCCAL5 = $05; // Oscillator Calibration
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OSCCAL6 = $06; // Oscillator Calibration
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OSCCAL7 = $07; // Oscillator Calibration
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// Pin Change Interrupt Control Register
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PCIE0 = $00; // Pin Change Interrupt Enables
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PCIE1 = $01; // Pin Change Interrupt Enables
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PCIE2 = $02; // Pin Change Interrupt Enables
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// External Interrupt Control Register
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ISC00 = $00; // External Interrupt Sense Control 0 Bits
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ISC01 = $01; // External Interrupt Sense Control 0 Bits
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ISC10 = $02; // External Interrupt Sense Control 1 Bits
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ISC11 = $03; // External Interrupt Sense Control 1 Bits
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// Pin Change Mask Register 2
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PCINT16 = $00; // Pin Change Enable Masks
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PCINT17 = $01; // Pin Change Enable Masks
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PCINT18 = $02; // Pin Change Enable Masks
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PCINT19 = $03; // Pin Change Enable Masks
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PCINT20 = $04; // Pin Change Enable Masks
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PCINT21 = $05; // Pin Change Enable Masks
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PCINT22 = $06; // Pin Change Enable Masks
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PCINT23 = $07; // Pin Change Enable Masks
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// Timer/Counter0 Interrupt Mask Register
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TOIE0 = $00;
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OCIE0A = $01;
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OCIE0B = $02;
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// Timer/Counter Interrupt Mask Register
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TOIE1 = $00;
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OCIE1A = $01;
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OCIE1B = $02;
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ICIE1 = $05;
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// Timer/Counter Interrupt Mask register
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TOIE2 = $00;
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OCIE2A = $01;
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OCIE2B = $02;
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// The ADC Control and Status register A
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ADPS0 = $00; // ADC Prescaler Select Bits
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ADPS1 = $01; // ADC Prescaler Select Bits
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ADPS2 = $02; // ADC Prescaler Select Bits
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ADIE = $03;
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ADIF = $04;
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ADATE = $05;
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ADSC = $06;
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ADEN = $07;
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// The ADC Control and Status register B
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ADTS0 = $00; // ADC Auto Trigger Source bits
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ADTS1 = $01; // ADC Auto Trigger Source bits
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ADTS2 = $02; // ADC Auto Trigger Source bits
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ACME = $06;
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// The ADC multiplexer Selection Register
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MUX0 = $00; // Analog Channel Selection Bits
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MUX1 = $01; // Analog Channel Selection Bits
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MUX2 = $02; // Analog Channel Selection Bits
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MUX3 = $03; // Analog Channel Selection Bits
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ADLAR = $05;
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REFS0 = $06; // Reference Selection Bits
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REFS1 = $07; // Reference Selection Bits
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// Digital Input Disable Register
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ADC0D = $00;
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ADC1D = $01;
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ADC2D = $02;
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ADC3D = $03;
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ADC4D = $04;
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ADC5D = $05;
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// Digital Input Disable Register 1
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AIN0D = $00;
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AIN1D = $01;
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// Timer/Counter1 Control Register A
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WGM10 = $00; // Waveform Generation Mode
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WGM11 = $01; // Waveform Generation Mode
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COM1B0 = $04; // Compare Output Mode 1B, bits
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COM1B1 = $05; // Compare Output Mode 1B, bits
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COM1A0 = $06; // Compare Output Mode 1A, bits
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COM1A1 = $07; // Compare Output Mode 1A, bits
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// Timer/Counter1 Control Register B
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CS10 = $00; // Prescaler source of Timer/Counter 1
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CS11 = $01; // Prescaler source of Timer/Counter 1
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CS12 = $02; // Prescaler source of Timer/Counter 1
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ICES1 = $06;
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ICNC1 = $07;
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// Timer/Counter1 Control Register C
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FOC1B = $06;
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FOC1A = $07;
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// Timer/Counter2 Control Register A
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WGM20 = $00; // Waveform Genration Mode
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WGM21 = $01; // Waveform Genration Mode
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COM2B0 = $04; // Compare Output Mode bits
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COM2B1 = $05; // Compare Output Mode bits
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COM2A0 = $06; // Compare Output Mode bits
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COM2A1 = $07; // Compare Output Mode bits
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// Timer/Counter2 Control Register B
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CS20 = $00; // Clock Select bits
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CS21 = $01; // Clock Select bits
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CS22 = $02; // Clock Select bits
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WGM22 = $03;
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FOC2B = $06;
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FOC2A = $07;
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// Asynchronous Status Register
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TCR2BUB = $00;
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TCR2AUB = $01;
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OCR2BUB = $02;
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OCR2AUB = $03;
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TCN2UB = $04;
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AS2 = $05;
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EXCLK = $06;
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// TWI Status Register
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TWPS0 = $00; // TWI Prescaler
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TWPS1 = $01; // TWI Prescaler
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TWS3 = $03; // TWI Status
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TWS4 = $04; // TWI Status
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TWS5 = $05; // TWI Status
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TWS6 = $06; // TWI Status
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TWS7 = $07; // TWI Status
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// TWI (Slave) Address register
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TWGCE = $00;
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TWA0 = $01; // TWI (Slave) Address register Bits
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TWA1 = $02; // TWI (Slave) Address register Bits
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TWA2 = $03; // TWI (Slave) Address register Bits
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TWA3 = $04; // TWI (Slave) Address register Bits
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TWA4 = $05; // TWI (Slave) Address register Bits
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TWA5 = $06; // TWI (Slave) Address register Bits
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TWA6 = $07; // TWI (Slave) Address register Bits
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// TWI Control Register
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TWIE = $00;
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TWEN = $02;
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TWWC = $03;
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TWSTO = $04;
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TWSTA = $05;
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TWEA = $06;
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TWINT = $07;
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// TWI (Slave) Address Mask Register
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TWAM0 = $01;
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TWAM1 = $02;
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TWAM2 = $03;
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TWAM3 = $04;
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TWAM4 = $05;
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TWAM5 = $06;
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TWAM6 = $07;
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// USART Control and Status Register A
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MPCM0 = $00;
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U2X0 = $01;
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UPE0 = $02;
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DOR0 = $03;
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FE0 = $04;
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UDRE0 = $05;
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TXC0 = $06;
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RXC0 = $07;
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// USART Control and Status Register B
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TXB80 = $00;
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RXB80 = $01;
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UCSZ02 = $02;
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TXEN0 = $03;
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RXEN0 = $04;
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UDRIE0 = $05;
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TXCIE0 = $06;
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RXCIE0 = $07;
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// USART Control and Status Register C
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UCPOL0 = $00;
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UCSZ00 = $01; // Character Size - together with UCSZ2 in UCSR0B
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UCSZ01 = $02; // Character Size - together with UCSZ2 in UCSR0B
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USBS0 = $03;
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UPM00 = $04; // Parity Mode Bits
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UPM01 = $05; // Parity Mode Bits
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UMSEL00 = $06; // USART Mode Select
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UMSEL01 = $07; // USART Mode Select
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// USART Control and Status Register D
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SFDE = $05;
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RXS = $06;
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RXSIE = $07;
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implementation
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{$define RELBRANCHES}
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{$i avrcommon.inc}
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procedure INT0_ISR; external name 'INT0_ISR'; // Interrupt 1 External Interrupt Request 0
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procedure INT1_ISR; external name 'INT1_ISR'; // Interrupt 2 External Interrupt Request 1
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procedure PCINT0_ISR; external name 'PCINT0_ISR'; // Interrupt 3 Pin Change Interrupt Request 0
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procedure PCINT1_ISR; external name 'PCINT1_ISR'; // Interrupt 4 Pin Change Interrupt Request 0
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procedure PCINT2_ISR; external name 'PCINT2_ISR'; // Interrupt 5 Pin Change Interrupt Request 1
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procedure WDT_ISR; external name 'WDT_ISR'; // Interrupt 6 Watchdog Time-out Interrupt
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procedure TIMER2_COMPA_ISR; external name 'TIMER2_COMPA_ISR'; // Interrupt 7 Timer/Counter2 Compare Match A
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procedure TIMER2_COMPB_ISR; external name 'TIMER2_COMPB_ISR'; // Interrupt 8 Timer/Counter2 Compare Match A
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procedure TIMER2_OVF_ISR; external name 'TIMER2_OVF_ISR'; // Interrupt 9 Timer/Counter2 Overflow
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procedure TIMER1_CAPT_ISR; external name 'TIMER1_CAPT_ISR'; // Interrupt 10 Timer/Counter1 Capture Event
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procedure TIMER1_COMPA_ISR; external name 'TIMER1_COMPA_ISR'; // Interrupt 11 Timer/Counter1 Compare Match A
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procedure TIMER1_COMPB_ISR; external name 'TIMER1_COMPB_ISR'; // Interrupt 12 Timer/Counter1 Compare Match B
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procedure TIMER1_OVF_ISR; external name 'TIMER1_OVF_ISR'; // Interrupt 13 Timer/Counter1 Overflow
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procedure TIMER0_COMPA_ISR; external name 'TIMER0_COMPA_ISR'; // Interrupt 14 TimerCounter0 Compare Match A
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procedure TIMER0_COMPB_ISR; external name 'TIMER0_COMPB_ISR'; // Interrupt 15 TimerCounter0 Compare Match B
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procedure TIMER0_OVF_ISR; external name 'TIMER0_OVF_ISR'; // Interrupt 16 Timer/Couner0 Overflow
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procedure SPI_STC_ISR; external name 'SPI_STC_ISR'; // Interrupt 17 SPI Serial Transfer Complete
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procedure USART_RX_ISR; external name 'USART_RX_ISR'; // Interrupt 18 USART Rx Complete
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procedure USART_UDRE_ISR; external name 'USART_UDRE_ISR'; // Interrupt 19 USART, Data Register Empty
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procedure USART_TX_ISR; external name 'USART_TX_ISR'; // Interrupt 20 USART Tx Complete
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procedure ADC_ISR; external name 'ADC_ISR'; // Interrupt 21 ADC Conversion Complete
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procedure EE_READY_ISR; external name 'EE_READY_ISR'; // Interrupt 22 EEPROM Ready
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procedure ANALOG_COMP_ISR; external name 'ANALOG_COMP_ISR'; // Interrupt 23 Analog Comparator
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procedure TWI_ISR; external name 'TWI_ISR'; // Interrupt 24 Two-wire Serial Interface
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procedure SPM_Ready_ISR; external name 'SPM_Ready_ISR'; // Interrupt 25 Store Program Memory Read
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procedure USART_START_ISR; external name 'USART_START_ISR'; // Interrupt 26 USART Start Edge Interrupt
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procedure _FPC_start; assembler; nostackframe; noreturn; public name '_START'; section '.init';
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asm
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rjmp __dtors_end
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rjmp INT0_ISR
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rjmp INT1_ISR
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rjmp PCINT0_ISR
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rjmp PCINT1_ISR
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rjmp PCINT2_ISR
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rjmp WDT_ISR
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rjmp TIMER2_COMPA_ISR
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rjmp TIMER2_COMPB_ISR
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rjmp TIMER2_OVF_ISR
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rjmp TIMER1_CAPT_ISR
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rjmp TIMER1_COMPA_ISR
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rjmp TIMER1_COMPB_ISR
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rjmp TIMER1_OVF_ISR
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rjmp TIMER0_COMPA_ISR
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rjmp TIMER0_COMPB_ISR
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rjmp TIMER0_OVF_ISR
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rjmp SPI_STC_ISR
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rjmp USART_RX_ISR
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rjmp USART_UDRE_ISR
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rjmp USART_TX_ISR
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rjmp ADC_ISR
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rjmp EE_READY_ISR
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rjmp ANALOG_COMP_ISR
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rjmp TWI_ISR
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rjmp SPM_Ready_ISR
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rjmp USART_START_ISR
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.weak INT0_ISR
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.weak INT1_ISR
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.weak PCINT0_ISR
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.weak PCINT1_ISR
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.weak PCINT2_ISR
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.weak WDT_ISR
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.weak TIMER2_COMPA_ISR
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.weak TIMER2_COMPB_ISR
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.weak TIMER2_OVF_ISR
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.weak TIMER1_CAPT_ISR
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.weak TIMER1_COMPA_ISR
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.weak TIMER1_COMPB_ISR
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.weak TIMER1_OVF_ISR
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.weak TIMER0_COMPA_ISR
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.weak TIMER0_COMPB_ISR
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.weak TIMER0_OVF_ISR
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.weak SPI_STC_ISR
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.weak USART_RX_ISR
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.weak USART_UDRE_ISR
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.weak USART_TX_ISR
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.weak ADC_ISR
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.weak EE_READY_ISR
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.weak ANALOG_COMP_ISR
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.weak TWI_ISR
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.weak SPM_Ready_ISR
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.weak USART_START_ISR
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.set INT0_ISR, Default_IRQ_handler
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.set INT1_ISR, Default_IRQ_handler
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.set PCINT0_ISR, Default_IRQ_handler
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.set PCINT1_ISR, Default_IRQ_handler
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.set PCINT2_ISR, Default_IRQ_handler
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.set WDT_ISR, Default_IRQ_handler
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.set TIMER2_COMPA_ISR, Default_IRQ_handler
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.set TIMER2_COMPB_ISR, Default_IRQ_handler
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.set TIMER2_OVF_ISR, Default_IRQ_handler
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.set TIMER1_CAPT_ISR, Default_IRQ_handler
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.set TIMER1_COMPA_ISR, Default_IRQ_handler
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.set TIMER1_COMPB_ISR, Default_IRQ_handler
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.set TIMER1_OVF_ISR, Default_IRQ_handler
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.set TIMER0_COMPA_ISR, Default_IRQ_handler
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.set TIMER0_COMPB_ISR, Default_IRQ_handler
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.set TIMER0_OVF_ISR, Default_IRQ_handler
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.set SPI_STC_ISR, Default_IRQ_handler
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.set USART_RX_ISR, Default_IRQ_handler
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.set USART_UDRE_ISR, Default_IRQ_handler
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.set USART_TX_ISR, Default_IRQ_handler
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.set ADC_ISR, Default_IRQ_handler
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.set EE_READY_ISR, Default_IRQ_handler
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.set ANALOG_COMP_ISR, Default_IRQ_handler
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.set TWI_ISR, Default_IRQ_handler
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.set SPM_Ready_ISR, Default_IRQ_handler
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.set USART_START_ISR, Default_IRQ_handler
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end;
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end.
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