mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-10-31 05:11:34 +01:00
220 lines
8.3 KiB
ObjectPascal
220 lines
8.3 KiB
ObjectPascal
unit ATtiny5;
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interface
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var
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// AD_CONVERTER
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ADMUX : byte absolute $00+$1B; // The ADC multiplexer Selection Register
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ADCL : byte absolute $00+$19; // ADC Data Register
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ADCSRA : byte absolute $00+$1D; // The ADC Control and Status register A
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ADCSRB : byte absolute $00+$1C; // The ADC Control and Status register B
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DIDR0 : byte absolute $00+$17; // Digital Input Disable Register
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// ANALOG_COMPARATOR
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ACSR : byte absolute $00+$1F; // Analog Comparator Control And Status Register
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// CPU
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CCP : byte absolute $00+$3C; // Configuration Change Protection
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SP : word absolute $00+$3D; // Stack Pointer
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SPL : byte absolute $00+$3D; // Stack Pointer
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SPH : byte absolute $00+$3D+1; // Stack Pointer
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SREG : byte absolute $00+$3F; // Status Register
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CLKMSR : byte absolute $00+$37; // Clock Main Settings Register
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CLKPSR : byte absolute $00+$36; // Clock Prescale Register
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OSCCAL : byte absolute $00+$39; // Oscillator Calibration Value
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SMCR : byte absolute $00+$3A; // Sleep Mode Control Register
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PRR : byte absolute $00+$35; // Power Reduction Register
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VLMCSR : byte absolute $00+$34; // Vcc Level Monitoring Control and Status Register
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RSTFLR : byte absolute $00+$3B; // Reset Flag Register
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NVMCSR : byte absolute $00+$32; // Non-Volatile Memory Control and Status Register
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NVMCMD : byte absolute $00+$33; // Non-Volatile Memory Command
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// PORTB
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PORTCR : byte absolute $00+$0C; // Port Control Register
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PUEB : byte absolute $00+$03; // Pull-up Enable Control Register
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DDRB : byte absolute $00+$01; // Data Direction Register, Port B
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PINB : byte absolute $00+$00; // Port B Data register
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PORTB : byte absolute $00+$02; // Input Pins, Port B
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// EXTERNAL_INTERRUPT
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EICRA : byte absolute $00+$15; // External Interrupt Control Register A
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EIMSK : byte absolute $00+$13; // External Interrupt Mask register
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EIFR : byte absolute $00+$14; // External Interrupt Flag register
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PCICR : byte absolute $00+$12; // Pin Change Interrupt Control Register
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PCIFR : byte absolute $00+$11; // Pin Change Interrupt Flag Register
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PCMSK : byte absolute $00+$10; // Pin Change Mask Register
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// TIMER_COUNTER_0
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TCCR0A : byte absolute $00+$2E; // Timer/Counter 0 Control Register A
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TCCR0B : byte absolute $00+$2D; // Timer/Counter 0 Control Register B
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TCCR0C : byte absolute $00+$2C; // Timer/Counter 0 Control Register C
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TCNT0 : word absolute $00+$28; // Timer/Counter0
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TCNT0L : byte absolute $00+$28; // Timer/Counter0
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TCNT0H : byte absolute $00+$28+1; // Timer/Counter0
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OCR0A : word absolute $00+$26; // Timer/Counter 0 Output Compare Register A
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OCR0AL : byte absolute $00+$26; // Timer/Counter 0 Output Compare Register A
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OCR0AH : byte absolute $00+$26+1; // Timer/Counter 0 Output Compare Register A
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OCR0B : word absolute $00+$24; // Timer/Counter0 Output Compare Register B
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OCR0BL : byte absolute $00+$24; // Timer/Counter0 Output Compare Register B
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OCR0BH : byte absolute $00+$24+1; // Timer/Counter0 Output Compare Register B
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ICR0 : word absolute $00+$22; // Input Capture Register Bytes
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ICR0L : byte absolute $00+$22; // Input Capture Register Bytes
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ICR0H : byte absolute $00+$22+1; // Input Capture Register Bytes
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TIMSK0 : byte absolute $00+$2B; // Timer Interrupt Mask Register 0
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TIFR0 : byte absolute $00+$2A; // Overflow Interrupt Enable
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GTCCR : byte absolute $00+$2F; // General Timer/Counter Control Register
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// WATCHDOG
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WDTCSR : byte absolute $00+$31; // Watchdog Timer Control and Status Register
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const
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// ADMUX
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MUX = 0; // Analog Channel Selection Bits
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// ADCSRA
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ADEN = 7; // ADC Enable
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ADSC = 6; // ADC Start Conversion
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ADATE = 5; // ADC Auto Trigger Enable
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ADIF = 4; // ADC Interrupt Flag
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ADIE = 3; // ADC Interrupt Enable
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ADPS = 0; // ADC Prescaler Select Bits
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// ADCSRB
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ADTS = 0; // ADC Auto Trigger Source bits
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// DIDR0
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ADC3D = 3; //
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ADC2D = 2; //
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ADC1D = 1; //
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ADC0D = 0; //
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// ACSR
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ACD = 7; // Analog Comparator Disable
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ACO = 5; // Analog Compare Output
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ACI = 4; // Analog Comparator Interrupt Flag
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ACIE = 3; // Analog Comparator Interrupt Enable
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ACIC = 2; // Analog Comparator Input Capture Enable
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ACIS = 0; // Analog Comparator Interrupt Mode Select bits
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// DIDR0
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AIN1D = 1; // AIN1 Digital Input Disable
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AIN0D = 0; // AIN0 Digital Input Disable
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// SREG
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I = 7; // Global Interrupt Enable
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T = 6; // Bit Copy Storage
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H = 5; // Half Carry Flag
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S = 4; // Sign Bit
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V = 3; // Two's Complement Overflow Flag
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N = 2; // Negative Flag
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Z = 1; // Zero Flag
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C = 0; // Carry Flag
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// CLKMSR
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CLKMS = 0; // Clock Main Select Bits
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// CLKPSR
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CLKPS = 0; // Clock Prescaler Select Bits
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// SMCR
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SM = 1; // Sleep Mode Select Bits
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SE = 0; // Sleep Enable
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// PRR
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PRADC = 1; // Power Reduction ADC
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PRTIM0 = 0; // Power Reduction Timer/Counter0
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// VLMCSR
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VLMF = 7; // VLM Flag
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VLMIE = 6; // VLM Interrupt Enable
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VLM = 0; // Trigger Level of Voltage Level Monitor bits
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// RSTFLR
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WDRF = 3; // Watchdog Reset Flag
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EXTRF = 1; // External Reset Flag
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PORF = 0; // Power-on Reset Flag
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// NVMCSR
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NVMBSY = 7; // Non-Volatile Memory Busy
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// PORTCR
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BBMB = 1; // Break-Before-Make Mode Enable
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// EICRA
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ISC01 = 1; // Interrupt Sense Control 0 Bit 1
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ISC00 = 0; // Interrupt Sense Control 0 Bit 0
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// EIMSK
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INT0 = 0; // External Interrupt Request 0 Enable
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// EIFR
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INTF0 = 0; // External Interrupt Flag 0
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// PCICR
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PCIE0 = 0; // Pin Change Interrupt Enable 0
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// PCIFR
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PCIF0 = 0; // Pin Change Interrupt Flag 0
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// PCMSK
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PCINT = 0; // Pin Change Enable Masks
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// TCCR0A
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COM0A = 6; // Compare Output Mode for Channel A bits
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COM0B = 4; // Compare Output Mode for Channel B bits
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WGM0 = 0; // Waveform Generation Mode
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// TCCR0B
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ICNC0 = 7; // Input Capture Noise Canceler
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ICES0 = 6; // Input Capture Edge Select
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CS0 = 0; // Clock Select
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// TCCR0C
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FOC0A = 7; // Force Output Compare for Channel A
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FOC0B = 6; // Force Output Compare for Channel B
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// TIMSK0
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ICIE0 = 5; // Input Capture Interrupt Enable
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OCIE0B = 2; // Output Compare B Match Interrupt Enable
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OCIE0A = 1; // Output Compare A Match Interrupt Enable
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TOIE0 = 0; // Overflow Interrupt Enable
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// TIFR0
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ICF0 = 5; // Input Capture Flag
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OCF0B = 2; // Timer Output Compare Flag 0B
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OCF0A = 1; // Timer Output Compare Flag 0A
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TOV0 = 0; // Timer Overflow Flag
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// GTCCR
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TSM = 7; // Timer Synchronization Mode
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PSR = 0; // Prescaler Reset
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// WDTCSR
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WDIF = 7; // Watchdog Timer Interrupt Flag
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WDIE = 6; // Watchdog Timer Interrupt Enable
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WDP = 0; // Watchdog Timer Prescaler Bits
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WDE = 3; // Watch Dog Enable
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implementation
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{$define RELBRANCHES}
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{$i avrcommon.inc}
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procedure INT0_ISR; external name 'INT0_ISR'; // Interrupt 1 External Interrupt Request 0
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procedure PCINT0_ISR; external name 'PCINT0_ISR'; // Interrupt 2 Pin Change Interrupt Request 0
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procedure TIM0_CAPT_ISR; external name 'TIM0_CAPT_ISR'; // Interrupt 3 Timer/Counter0 Input Capture
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procedure TIM0_OVF_ISR; external name 'TIM0_OVF_ISR'; // Interrupt 4 Timer/Counter0 Overflow
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procedure TIM0_COMPA_ISR; external name 'TIM0_COMPA_ISR'; // Interrupt 5 Timer/Counter Compare Match A
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procedure TIM0_COMPB_ISR; external name 'TIM0_COMPB_ISR'; // Interrupt 6 Timer/Counter Compare Match B
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procedure ANA_COMP_ISR; external name 'ANA_COMP_ISR'; // Interrupt 7 Analog Comparator
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procedure WDT_ISR; external name 'WDT_ISR'; // Interrupt 8 Watchdog Time-out
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procedure VLM_ISR; external name 'VLM_ISR'; // Interrupt 9 Vcc Voltage Level Monitor
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procedure ADC_ISR; external name 'ADC_ISR'; // Interrupt 10 ADC Conversion Complete
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procedure _FPC_start; assembler; nostackframe; noreturn; public name '_START'; section '.init';
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asm
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rjmp __dtors_end
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rjmp INT0_ISR
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rjmp PCINT0_ISR
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rjmp TIM0_CAPT_ISR
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rjmp TIM0_OVF_ISR
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rjmp TIM0_COMPA_ISR
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rjmp TIM0_COMPB_ISR
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rjmp ANA_COMP_ISR
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rjmp WDT_ISR
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rjmp VLM_ISR
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rjmp ADC_ISR
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.weak INT0_ISR
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.weak PCINT0_ISR
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.weak TIM0_CAPT_ISR
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.weak TIM0_OVF_ISR
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.weak TIM0_COMPA_ISR
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.weak TIM0_COMPB_ISR
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.weak ANA_COMP_ISR
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.weak WDT_ISR
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.weak VLM_ISR
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.weak ADC_ISR
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.set INT0_ISR, Default_IRQ_handler
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.set PCINT0_ISR, Default_IRQ_handler
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.set TIM0_CAPT_ISR, Default_IRQ_handler
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.set TIM0_OVF_ISR, Default_IRQ_handler
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.set TIM0_COMPA_ISR, Default_IRQ_handler
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.set TIM0_COMPB_ISR, Default_IRQ_handler
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.set ANA_COMP_ISR, Default_IRQ_handler
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.set WDT_ISR, Default_IRQ_handler
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.set VLM_ISR, Default_IRQ_handler
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.set ADC_ISR, Default_IRQ_handler
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end;
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end.
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