mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-10-31 12:11:34 +01:00
444 lines
18 KiB
ObjectPascal
444 lines
18 KiB
ObjectPascal
unit ATtiny87;
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interface
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var
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// PORTA
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PORTA : byte absolute $00+$22; // Port A Data Register
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DDRA : byte absolute $00+$21; // Port A Data Direction Register
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PINA : byte absolute $00+$20; // Port A Input Pins
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// PORTB
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PORTB : byte absolute $00+$25; // Port B Data Register
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DDRB : byte absolute $00+$24; // Port B Data Direction Register
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PINB : byte absolute $00+$23; // Port B Input Pins
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// LINUART
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LINCR : byte absolute $00+$C8; // LIN Control Register
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LINSIR : byte absolute $00+$C9; // LIN Status and Interrupt Register
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LINENIR : byte absolute $00+$CA; // LIN Enable Interrupt Register
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LINERR : byte absolute $00+$CB; // LIN Error Register
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LINBTR : byte absolute $00+$CC; // LIN Bit Timing Register
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LINBRRL : byte absolute $00+$CD; // LIN Baud Rate Low Register
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LINBRRH : byte absolute $00+$CE; // LIN Baud Rate High Register
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LINDLR : byte absolute $00+$CF; // LIN Data Length Register
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LINIDR : byte absolute $00+$D0; // LIN Identifier Register
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LINSEL : byte absolute $00+$D1; // LIN Data Buffer Selection Register
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LINDAT : byte absolute $00+$D2; // LIN Data Register
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// USI
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USIPP : byte absolute $00+$BC; // USI Pin Position
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USIBR : byte absolute $00+$BB; // USI Buffer Register
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USIDR : byte absolute $00+$BA; // USI Data Register
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USISR : byte absolute $00+$B9; // USI Status Register
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USICR : byte absolute $00+$B8; // USI Control Register
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// TIMER_COUNTER_0
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TIMSK0 : byte absolute $00+$6E; // Timer/Counter0 Interrupt Mask register
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TIFR0 : byte absolute $00+$35; // Timer/Counter0 Interrupt Flag Register
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TCCR0A : byte absolute $00+$45; // Timer/Counter0 Control Register A
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TCCR0B : byte absolute $00+$46; // Timer/Counter0 Control Register B
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TCNT0 : byte absolute $00+$47; // Timer/Counter0
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OCR0A : byte absolute $00+$48; // Timer/Counter0 Output Compare Register A
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ASSR : byte absolute $00+$B6; // Asynchronous Status Register
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GTCCR : byte absolute $00+$43; // General Timer Counter Control register
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// TIMER_COUNTER_1
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TIMSK1 : byte absolute $00+$6F; // Timer/Counter1 Interrupt Mask Register
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TIFR1 : byte absolute $00+$36; // Timer/Counter1 Interrupt Flag register
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TCCR1A : byte absolute $00+$80; // Timer/Counter1 Control Register A
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TCCR1B : byte absolute $00+$81; // Timer/Counter1 Control Register B
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TCCR1C : byte absolute $00+$82; // Timer/Counter1 Control Register C
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TCCR1D : byte absolute $00+$83; // Timer/Counter1 Control Register D
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TCNT1 : word absolute $00+$84; // Timer/Counter1 Bytes
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TCNT1L : byte absolute $00+$84; // Timer/Counter1 Bytes
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TCNT1H : byte absolute $00+$84+1; // Timer/Counter1 Bytes
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OCR1A : word absolute $00+$88; // Timer/Counter1 Output Compare Register A Bytes
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OCR1AL : byte absolute $00+$88; // Timer/Counter1 Output Compare Register A Bytes
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OCR1AH : byte absolute $00+$88+1; // Timer/Counter1 Output Compare Register A Bytes
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OCR1B : word absolute $00+$8A; // Timer/Counter1 Output Compare Register B Bytes
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OCR1BL : byte absolute $00+$8A; // Timer/Counter1 Output Compare Register B Bytes
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OCR1BH : byte absolute $00+$8A+1; // Timer/Counter1 Output Compare Register B Bytes
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ICR1 : word absolute $00+$86; // Timer/Counter1 Input Capture Register Bytes
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ICR1L : byte absolute $00+$86; // Timer/Counter1 Input Capture Register Bytes
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ICR1H : byte absolute $00+$86+1; // Timer/Counter1 Input Capture Register Bytes
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// WATCHDOG
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WDTCR : byte absolute $00+$60; // Watchdog Timer Control Register
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// EEPROM
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EEAR : word absolute $00+$41; // EEPROM Address Register Bytes
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EEARL : byte absolute $00+$41; // EEPROM Address Register Bytes
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EEARH : byte absolute $00+$41+1; // EEPROM Address Register Bytes
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EEDR : byte absolute $00+$40; // EEPROM Data Register
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EECR : byte absolute $00+$3F; // EEPROM Control Register
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// SPI
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SPDR : byte absolute $00+$4E; // SPI Data Register
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SPSR : byte absolute $00+$4D; // SPI Status Register
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SPCR : byte absolute $00+$4C; // SPI Control Register
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// AD_CONVERTER
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ADMUX : byte absolute $00+$7C; // The ADC multiplexer Selection Register
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ADC : word absolute $00+$78; // ADC Data Register Bytes
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ADCL : byte absolute $00+$78; // ADC Data Register Bytes
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ADCH : byte absolute $00+$78+1; // ADC Data Register Bytes
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ADCSRA : byte absolute $00+$7A; // The ADC Control and Status register A
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ADCSRB : byte absolute $00+$7B; // The ADC Control and Status register B (Shared with ANALOG_COMPARATOR IO_MODULE)
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AMISCR : byte absolute $00+$77; // Analog Miscellaneous Control Register (Shared with CURRENT_SOURCE IO_MODULE)
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DIDR1 : byte absolute $00+$7F; // Digital Input Disable Register 1
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DIDR0 : byte absolute $00+$7E; // Digital Input Disable Register 0
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// CURRENT_SOURCE
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// ANALOG_COMPARATOR
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ACSR : byte absolute $00+$50; // Analog Comparator Control And Status Register
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// EXTERNAL_INTERRUPT
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EICRA : byte absolute $00+$69; // External Interrupt Control Register
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EIMSK : byte absolute $00+$3D; // External Interrupt Mask Register
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EIFR : byte absolute $00+$3C; // External Interrupt Flag Register
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PCICR : byte absolute $00+$68; // Pin Change Interrupt Control Register
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PCIFR : byte absolute $00+$3B; // Pin Change Interrupt Flag Register
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PCMSK1 : byte absolute $00+$6C; // Pin Change Mask Register 1
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PCMSK0 : byte absolute $00+$6B; // Pin Change Mask Register 0
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// BOOT_LOAD
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SPMCSR : byte absolute $00+$57; // Store Program Memory Control Register
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// CPU
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SREG : byte absolute $00+$5F; // Status Register
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PRR : byte absolute $00+$64; // Power Reduction Register
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SP : word absolute $00+$5D; // Stack Pointer Bytes
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SPL : byte absolute $00+$5D; // Stack Pointer Bytes
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SPH : byte absolute $00+$5D+1; // Stack Pointer Bytes
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MCUCR : byte absolute $00+$55; // MCU Control Register
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MCUSR : byte absolute $00+$54; // MCU Status register
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OSCCAL : byte absolute $00+$66; // Oscillator Calibration Register
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CLKPR : byte absolute $00+$61; // Clock Prescale Register
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CLKSELR : byte absolute $00+$63; // Clock Selection Register
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CLKCSR : byte absolute $00+$62; // Clock Control & Status Register
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DWDR : byte absolute $00+$51; // DebugWire data register
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GPIOR2 : byte absolute $00+$4B; // General Purpose IO register 2
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GPIOR1 : byte absolute $00+$4A; // General Purpose register 1
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GPIOR0 : byte absolute $00+$3E; // General purpose register 0
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PORTCR : byte absolute $00+$32; // General purpose register 0
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const
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// LINCR
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LSWRES = 7; // Software Reset
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LIN13 = 6; // LIN Standard
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LCONF = 4; // LIN Configuration bits
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LENA = 3; // LIN or UART Enable
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LCMD = 0; // LIN Command and Mode bits
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// LINSIR
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LIDST = 5; // Identifier Status bits
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LBUSY = 4; // Busy Signal
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LERR = 3; // Error Interrupt
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LIDOK = 2; // Identifier Interrupt
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LTXOK = 1; // Transmit Performed Interrupt
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LRXOK = 0; // Receive Performed Interrupt
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// LINENIR
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LENERR = 3; // Enable Error Interrupt
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LENIDOK = 2; // Enable Identifier Interrupt
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LENTXOK = 1; // Enable Transmit Performed Interrupt
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LENRXOK = 0; // Enable Receive Performed Interrupt
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// LINERR
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LABORT = 7; // Abort Flag
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LTOERR = 6; // Frame Time Out Error Flag
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LOVERR = 5; // Overrun Error Flag
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LFERR = 4; // Framing Error Flag
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LSERR = 3; // Synchronization Error Flag
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LPERR = 2; // Parity Error Flag
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LCERR = 1; // Checksum Error Flag
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LBERR = 0; // Bit Error Flag
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// LINBTR
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LDISR = 7; // Disable Bit Timing Resynchronization
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LBT = 0; // LIN Bit Timing bits
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// LINBRRL
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LDIV = 0; //
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// LINBRRH
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// LINDLR
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LTXDL = 4; // LIN Transmit Data Length bits
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LRXDL = 0; // LIN Receive Data Length bits
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// LINIDR
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LP = 6; // Parity bits
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LID = 0; // Identifier bit 5 or Data Length bits
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// LINSEL
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LAINC = 3; // Auto Increment of Data Buffer Index (Active Low)
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LINDX = 0; // FIFO LIN Data Buffer Index bits
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// LINDAT
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LDATA = 0; //
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// USISR
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USISIF = 7; // Start Condition Interrupt Flag
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USIOIF = 6; // Counter Overflow Interrupt Flag
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USIPF = 5; // Stop Condition Flag
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USIDC = 4; // Data Output Collision
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USICNT = 0; // USI Counter Value Bits
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// USICR
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USISIE = 7; // Start Condition Interrupt Enable
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USIOIE = 6; // Counter Overflow Interrupt Enable
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USIWM = 4; // USI Wire Mode Bits
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USICS = 2; // USI Clock Source Select Bits
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USICLK = 1; // Clock Strobe
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USITC = 0; // Toggle Clock Port Pin
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// TIMSK0
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OCIE0A = 1; // Timer/Counter0 Output Compare Match A Interrupt Enable
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TOIE0 = 0; // Timer/Counter0 Overflow Interrupt Enable
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// TIFR0
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OCF0A = 1; // Output Compare Flag 0A
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TOV0 = 0; // Timer/Counter0 Overflow Flag
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// TCCR0A
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COM0A = 6; // Compare Output Mode bits
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WGM0 = 0; // Waveform Genration Mode bits
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// TCCR0B
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FOC0A = 7; // Force Output Compare A
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CS0 = 0; // Clock Select bits
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// ASSR
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EXCLK = 6; // Enable External Clock Input
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AS0 = 5; // Asynchronous Timer/Counter0
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TCN0UB = 4; // Timer/Counter0 Update Busy
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OCR0AUB = 3; // Output Compare Register 0A Update Busy
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TCR0AUB = 1; // Timer/Counter0 Control Register A Update Busy
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TCR0BUB = 0; // Timer/Counter0 Control Register B Update Busy
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// GTCCR
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TSM = 7; // Timer/Counter Synchronization Mode
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PSR0 = 1; // Prescaler Reset Asynchronous 8-bit Timer/Counter0
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PSR1 = 0; // Prescaler Reset Synchronous 16-bit Timer/Counter1
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// TIMSK1
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ICIE1 = 5; // Timer/Counter1 Input Capture Interrupt Enable
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OCIE1B = 2; // Timer/Counter1 Output Compare B Match Interrupt Enable
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OCIE1A = 1; // Timer/Counter1 Output Compare A Match Interrupt Enable
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TOIE1 = 0; // Timer/Counter1 Overflow Interrupt Enable
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// TIFR1
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ICF1 = 5; // Timer/Counter1 Input Capture Flag
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OCF1B = 2; // Timer/Counter1 Output Compare B Match Flag
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OCF1A = 1; // Timer/Counter1 Output Compare A Match Flag
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TOV1 = 0; // Timer/Counter1 Overflow Flag
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// TCCR1A
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COM1A = 6; // Compare Output Mode 1A, bits
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COM1B = 4; // Compare Output Mode 1B, bits
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WGM1 = 0; // Pulse Width Modulator Select Bits
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// TCCR1B
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ICNC1 = 7; // Input Capture 1 Noise Canceler
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ICES1 = 6; // Input Capture 1 Edge Select
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CS1 = 0; // Timer/Counter1 Clock Select bits
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// TCCR1C
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FOC1A = 7; // Timer/Counter1 Force Output Compare for Channel A
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FOC1B = 6; // Timer/Counter1 Force Output Compare for Channel B
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// TCCR1D
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OC1BX = 7; // Timer/Counter1 Output Compare X-pin Enable for Channel B
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OC1BW = 6; // Timer/Counter1 Output Compare W-pin Enable for Channel B
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OC1BV = 5; // Timer/Counter1 Output Compare V-pin Enable for Channel B
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OC1BU = 4; // Timer/Counter1 Output Compare U-pin Enable for Channel B
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OC1AX = 3; // Timer/Counter1 Output Compare X-pin Enable for Channel A
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OC1AW = 2; // Timer/Counter1 Output Compare W-pin Enable for Channel A
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OC1AV = 1; // Timer/Counter1 Output Compare V-pin Enable for Channel A
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OC1AU = 0; // Timer/Counter1 Output Compare U-pin Enable for Channel A
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// WDTCR
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WDIF = 7; // Watchdog Timeout Interrupt Flag
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WDIE = 6; // Watchdog Timeout Interrupt Enable
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WDP = 0; // Watchdog Timer Prescaler Bits
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WDCE = 4; // Watchdog Change Enable
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WDE = 3; // Watch Dog Enable
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// EECR
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EEPM = 4; // EEPROM Programming Mode Bits
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EERIE = 3; // EEPROM Ready Interrupt Enable
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EEMPE = 2; // EEPROM Master Write Enable
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EEPE = 1; // EEPROM Write Enable
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EERE = 0; // EEPROM Read Enable
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// SPSR
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SPIF = 7; // SPI Interrupt Flag
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WCOL = 6; // Write Collision Flag
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SPI2X = 0; // Double SPI Speed Bit
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// SPCR
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SPIE = 7; // SPI Interrupt Enable
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SPE = 6; // SPI Enable
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DORD = 5; // Data Order
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MSTR = 4; // Master/Slave Select
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CPOL = 3; // Clock polarity
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CPHA = 2; // Clock Phase
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SPR = 0; // SPI Clock Rate Selects
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// ADMUX
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REFS = 6; // Reference Selection Bits
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ADLAR = 5; // Left Adjust Result
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MUX = 0; // Analog Channel and Gain Selection Bits
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// ADCSRA
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ADEN = 7; // ADC Enable
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ADSC = 6; // ADC Start Conversion
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ADATE = 5; // ADC Auto Trigger Enable
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ADIF = 4; // ADC Interrupt Flag
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ADIE = 3; // ADC Interrupt Enable
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ADPS = 0; // ADC Prescaler Select Bits
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// ADCSRB
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BIN = 7; // Bipolar Input Mode
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ADTS = 0; // ADC Auto Trigger Source bits
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// AMISCR
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AREFEN = 2; // External Voltage Reference Input Enable
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XREFEN = 1; // Internal Voltage Reference Output Enable
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// DIDR1
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ADC10D = 2; //
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ADC9D = 1; //
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ADC8D = 0; //
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// DIDR0
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ADC7D = 7; //
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ADC6D = 6; //
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ADC5D = 5; //
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ADC4D = 4; //
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ADC3D = 3; //
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ADC2D = 2; //
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ADC1D = 1; //
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ADC0D = 0; //
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// AMISCR
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ISRCEN = 0; // Current Source Enable
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// ADCSRB
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ACME = 6; // Analog Comparator Multiplexer Enable
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ACIR = 4; // Analog Comparator Internal Voltage Reference Select Bits
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// ACSR
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ACD = 7; // Analog Comparator Disable
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ACIRS = 6; // Analog Comparator Internal Reference Select
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ACO = 5; // Analog Compare Output
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ACI = 4; // Analog Comparator Interrupt Flag
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ACIE = 3; // Analog Comparator Interrupt Enable
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ACIC = 2; // Analog Comparator Input Capture Enable
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ACIS = 0; // Analog Comparator Interrupt Mode Select bits
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// EICRA
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ISC1 = 2; // External Interrupt Sense Control 1 Bits
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ISC0 = 0; // External Interrupt Sense Control 0 Bits
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// EIMSK
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INT = 0; // External Interrupt Request 1 Enable
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// EIFR
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INTF = 0; // External Interrupt Flags
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// PCICR
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PCIE = 0; // Pin Change Interrupt Enable on any PCINT14..8 pin
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// PCIFR
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PCIF = 0; // Pin Change Interrupt Flags
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// PCMSK1
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PCINT = 0; // Pin Change Enable Masks
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// PCMSK0
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// SPMCSR
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RWWSB = 6; // Read While Write Section Busy
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SIGRD = 5; // Signature Row Read
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CTPB = 4; // Clear Temporary Page Buffer
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RFLB = 3; // Read Fuse and Lock Bits
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PGWRT = 2; // Page Write
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PGERS = 1; // Page Erase
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SPMEN = 0; // Store Program Memory Enable
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// SREG
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I = 7; // Global Interrupt Enable
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T = 6; // Bit Copy Storage
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H = 5; // Half Carry Flag
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S = 4; // Sign Bit
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V = 3; // Two's Complement Overflow Flag
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N = 2; // Negative Flag
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Z = 1; // Zero Flag
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C = 0; // Carry Flag
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// PRR
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PRLIN = 5; // Power Reduction LINUART
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PRSPI = 4; // Power Reduction SPI
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PRTIM1 = 3; // Power Reduction Timer/Counter1
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PRTIM0 = 2; // Power Reduction Timer/Counter0
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PRUSI = 1; // Power Reduction USI
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PRADC = 0; // Power Reduction ADC
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// MCUCR
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BODSE = 6; // BOD Sleep Enable
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BODS = 5; // BOD Sleep
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PUD = 4; // Pull-up Disable
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// MCUSR
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WDRF = 3; // Watchdog Reset Flag
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BORF = 2; // Brown-out Reset Flag
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EXTRF = 1; // External Reset Flag
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PORF = 0; // Power-On Reset Flag
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// MCUSR
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SM = 1; // Sleep Mode Select Bits
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SE = 0; // Sleep Enable
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// CLKPR
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CLKPCE = 7; // Clock Prescaler Change Enable
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CLKPS = 0; // Clock Prescaler Select Bits
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// CLKSELR
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COUT = 6; // Clock Out - CKOUT fuse substitution
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CSUT = 4; // Clock Start-up Time bit 1 - SUT1 fuse substitution
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CSEL = 0; // Clock Source Select bit 3 - CKSEL3 fuse substitution
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// CLKCSR
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CLKCCE = 7; // Clock Control Change Enable
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CLKRDY = 4; // Clock Ready Flag
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CLKC = 0; // Clock Control bits
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implementation
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{$define RELBRANCHES}
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{$i avrcommon.inc}
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procedure INT0_ISR; external name 'INT0_ISR'; // Interrupt 1 External Interrupt Request 0
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procedure INT1_ISR; external name 'INT1_ISR'; // Interrupt 2 External Interrupt Request 1
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procedure PCINT0_ISR; external name 'PCINT0_ISR'; // Interrupt 3 Pin Change Interrupt Request 0
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procedure PCINT1_ISR; external name 'PCINT1_ISR'; // Interrupt 4 Pin Change Interrupt Request 1
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procedure WDT_ISR; external name 'WDT_ISR'; // Interrupt 5 Watchdog Time-Out Interrupt
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procedure TIMER1_CAPT_ISR; external name 'TIMER1_CAPT_ISR'; // Interrupt 6 Timer/Counter1 Capture Event
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procedure TIMER1_COMPA_ISR; external name 'TIMER1_COMPA_ISR'; // Interrupt 7 Timer/Counter1 Compare Match 1A
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procedure TIMER1_COMPB_ISR; external name 'TIMER1_COMPB_ISR'; // Interrupt 8 Timer/Counter1 Compare Match 1B
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procedure TIMER1_OVF_ISR; external name 'TIMER1_OVF_ISR'; // Interrupt 9 Timer/Counter1 Overflow
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procedure TIMER0_COMPA_ISR; external name 'TIMER0_COMPA_ISR'; // Interrupt 10 Timer/Counter0 Compare Match 0A
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procedure TIMER0_OVF_ISR; external name 'TIMER0_OVF_ISR'; // Interrupt 11 Timer/Counter0 Overflow
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procedure LIN_TC_ISR; external name 'LIN_TC_ISR'; // Interrupt 12 LIN Transfer Complete
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procedure LIN_ERR_ISR; external name 'LIN_ERR_ISR'; // Interrupt 13 LIN Error
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procedure SPI_STC_ISR; external name 'SPI_STC_ISR'; // Interrupt 14 SPI Serial Transfer Complete
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procedure ADC_ISR; external name 'ADC_ISR'; // Interrupt 15 ADC Conversion Complete
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procedure EE_RDY_ISR; external name 'EE_RDY_ISR'; // Interrupt 16 EEPROM Ready
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procedure ANA_COMP_ISR; external name 'ANA_COMP_ISR'; // Interrupt 34 Analog Comparator
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procedure USI_START_ISR; external name 'USI_START_ISR'; // Interrupt 36 USI Start
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procedure USI_OVF_ISR; external name 'USI_OVF_ISR'; // Interrupt 19 USI Overflow
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procedure _FPC_start; assembler; nostackframe; noreturn; public name '_START'; section '.init';
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asm
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rjmp __dtors_end
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rjmp INT0_ISR
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rjmp INT1_ISR
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rjmp PCINT0_ISR
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rjmp PCINT1_ISR
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rjmp WDT_ISR
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rjmp TIMER1_CAPT_ISR
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rjmp TIMER1_COMPA_ISR
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rjmp TIMER1_COMPB_ISR
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rjmp TIMER1_OVF_ISR
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rjmp TIMER0_COMPA_ISR
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rjmp TIMER0_OVF_ISR
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rjmp LIN_TC_ISR
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rjmp LIN_ERR_ISR
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rjmp SPI_STC_ISR
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rjmp ADC_ISR
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rjmp EE_RDY_ISR
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rjmp ANA_COMP_ISR
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rjmp USI_START_ISR
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rjmp USI_OVF_ISR
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.weak INT0_ISR
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.weak INT1_ISR
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.weak PCINT0_ISR
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.weak PCINT1_ISR
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.weak WDT_ISR
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.weak TIMER1_CAPT_ISR
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.weak TIMER1_COMPA_ISR
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.weak TIMER1_COMPB_ISR
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.weak TIMER1_OVF_ISR
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.weak TIMER0_COMPA_ISR
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.weak TIMER0_OVF_ISR
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.weak LIN_TC_ISR
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.weak LIN_ERR_ISR
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.weak SPI_STC_ISR
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.weak ADC_ISR
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.weak EE_RDY_ISR
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.weak ANA_COMP_ISR
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.weak USI_START_ISR
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.weak USI_OVF_ISR
|
|
|
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.set INT0_ISR, Default_IRQ_handler
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.set INT1_ISR, Default_IRQ_handler
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.set PCINT0_ISR, Default_IRQ_handler
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.set PCINT1_ISR, Default_IRQ_handler
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.set WDT_ISR, Default_IRQ_handler
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.set TIMER1_CAPT_ISR, Default_IRQ_handler
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|
.set TIMER1_COMPA_ISR, Default_IRQ_handler
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.set TIMER1_COMPB_ISR, Default_IRQ_handler
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.set TIMER1_OVF_ISR, Default_IRQ_handler
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.set TIMER0_COMPA_ISR, Default_IRQ_handler
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|
.set TIMER0_OVF_ISR, Default_IRQ_handler
|
|
.set LIN_TC_ISR, Default_IRQ_handler
|
|
.set LIN_ERR_ISR, Default_IRQ_handler
|
|
.set SPI_STC_ISR, Default_IRQ_handler
|
|
.set ADC_ISR, Default_IRQ_handler
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|
.set EE_RDY_ISR, Default_IRQ_handler
|
|
.set ANA_COMP_ISR, Default_IRQ_handler
|
|
.set USI_START_ISR, Default_IRQ_handler
|
|
.set USI_OVF_ISR, Default_IRQ_handler
|
|
end;
|
|
|
|
end.
|