mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-07-19 09:56:20 +02:00
4d86d25c6c
like field reordering (possible problems cracker classes) or using ebp as normal register (broken
stack traces from dump_stack)
+ niln is also valid in a cse domain
* parameters passed by reference shall have a complexity >1
* load nodes from outer scopes shall have a complexity >1
* better cse debugging
+ more node types added to cse
* consider parameters passed by reference in cse
* take care of cse in parameters in simple cases
git-svn-id: trunk@22050 -
82 lines
2.2 KiB
ObjectPascal
82 lines
2.2 KiB
ObjectPascal
{
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Copyright (c) 1998-2002 by the Free Pascal development team
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Basic Processor information for the ARM
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See the file COPYING.FPC, included in this distribution,
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for details about the copyright.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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**********************************************************************}
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Unit CPUInfo;
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Interface
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uses
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globtype;
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Type
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bestreal = double;
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ts32real = single;
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ts64real = double;
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ts80real = type double;
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ts128real = type double;
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ts64comp = comp;
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pbestreal=^bestreal;
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{ possible supported processors for this target }
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tcputype =
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(cpu_none,
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cpu_mips32
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);
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tfputype =(fpu_none,fpu_soft,fpu_mips2,fpu_mips3);
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Const
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{# Size of native extended floating point type }
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extended_size = 8;
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{# Size of a multimedia register }
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mmreg_size = 0;
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{ target cpu string (used by compiler options) }
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{$ifdef MIPSEL}
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target_cpu_string = 'mipsel';
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{$else MIPSEL}
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target_cpu_string = 'mips';
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{$endif MIPSEL}
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{ calling conventions supported by the code generator }
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supported_calling_conventions : tproccalloptions = [
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pocall_internproc,
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pocall_stdcall,
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{ same as stdcall only different name mangling }
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pocall_cdecl,
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{ same as stdcall only different name mangling }
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pocall_cppdecl
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];
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cputypestr : array[tcputype] of string[6] = ('',
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'MIPS32'
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);
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fputypestr : array[tfputype] of string[9] = ('',
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'SOFT',
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'FPU_MIPS2','FPU_MIPS3'
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);
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{ Supported optimizations, only used for information }
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supported_optimizerswitches = [cs_opt_regvar,cs_opt_loopunroll,cs_opt_nodecse,
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cs_opt_reorder_fields,cs_opt_fastmath];
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level1optimizerswitches = [];
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level2optimizerswitches = level1optimizerswitches + [cs_opt_regvar,cs_opt_stackframe,cs_opt_nodecse];
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level3optimizerswitches = level2optimizerswitches + [cs_opt_loopunroll];
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level4optimizerswitches = genericlevel4optimizerswitches + level3optimizerswitches + [];
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Implementation
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end.
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