mirror of
https://gitlab.com/freepascal.org/fpc/source.git
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453 lines
15 KiB
ObjectPascal
453 lines
15 KiB
ObjectPascal
{
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$Id$
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Copyright (c) 1998-2002 by Jonas Maebe, member of the Free Pascal
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development team
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This unit contains register renaming functionality
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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Unit rrOpt386;
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{$i fpcdefs.inc}
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Interface
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Uses aasmbase,aasmtai,aasmcpu;
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procedure doRenaming(asml: TAAsmoutput; first, last: Tai);
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Implementation
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Uses
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{$ifdef replaceregdebug}cutils,{$endif}
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verbose,globals,cpubase,daopt386,csopt386,cginfo,rgobj;
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function canBeFirstSwitch(p: Taicpu; reg: tregister): boolean;
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{ checks whether an operation on reg can be switched to another reg without an }
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{ additional mov, e.g. "addl $4,%reg1" can be changed to "leal 4(%reg1),%reg2" }
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begin
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canBeFirstSwitch := false;
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case p.opcode of
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A_MOV,A_MOVZX,A_MOVSX,A_LEA:
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canBeFirstSwitch :=
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(p.oper[1].typ = top_reg) and
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(reg32(p.oper[1].reg).enum = reg.enum);
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A_IMUL:
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canBeFirstSwitch :=
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(p.ops >= 2) and
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(reg32(p.oper[p.ops-1].reg).enum = reg.enum) and
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(p.oper[0].typ <> top_ref) and
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(not pTaiprop(p.optinfo)^.FlagsUsed);
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A_INC,A_DEC,A_SUB,A_ADD:
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canBeFirstSwitch :=
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(p.oper[1].typ = top_reg) and
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(p.opsize = S_L) and
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(reg32(p.oper[1].reg).enum = reg.enum) and
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(p.oper[0].typ <> top_ref) and
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((p.opcode <> A_SUB) or
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(p.oper[0].typ = top_const)) and
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(not pTaiprop(p.optinfo)^.FlagsUsed);
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A_SHL:
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canBeFirstSwitch :=
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(p.opsize = S_L) and
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(p.oper[1].typ = top_reg) and
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(p.oper[1].reg.enum = reg.enum) and
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(p.oper[0].typ = top_const) and
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(p.oper[0].val in [1,2,3]) and
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(not pTaiprop(p.optinfo)^.FlagsUsed);
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end;
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end;
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procedure switchReg(var reg: tregister; reg1, reg2: tregister);
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begin
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if reg1.enum>lastreg then
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internalerror(2003010801);
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if reg2.enum>lastreg then
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internalerror(2003010801);
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if reg.enum>lastreg then
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internalerror(2003010801);
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if reg.enum = reg1.enum then
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reg := reg2
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else if reg.enum = reg2.enum then
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reg := reg1
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else if (reg.enum in regset8bit) then
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begin
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if (reg.enum = rg.makeregsize(reg1,OS_8).enum) then
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reg := rg.makeregsize(reg2,OS_8)
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else if reg.enum = rg.makeregsize(reg2,OS_8).enum then
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reg := rg.makeregsize(reg1,OS_8);
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end
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else if (reg.enum in regset16bit) then
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begin
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if reg.enum = rg.makeregsize(reg1,OS_16).enum then
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reg := rg.makeregsize(reg2,OS_16)
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else if reg.enum = rg.makeregsize(reg2,OS_16).enum then
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reg := rg.makeregsize(reg1,OS_16);
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end;
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end;
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procedure switchOp(var op: toper; reg1, reg2: tregister);
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begin
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case op.typ of
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top_reg:
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switchReg(op.reg,reg1,reg2);
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top_ref:
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begin
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switchReg(op.ref^.base,reg1,reg2);
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switchReg(op.ref^.index,reg1,reg2);
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end;
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end;
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end;
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procedure doSwitchReg(hp: Taicpu; reg1,reg2: tregister);
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var
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opCount: longint;
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begin
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for opCount := 0 to hp.ops-1 do
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switchOp(hp.oper[opCount],reg1,reg2);
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end;
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procedure doFirstSwitch(p: Taicpu; reg1, reg2: tregister);
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var
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tmpRef: treference;
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begin
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case p.opcode of
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A_MOV,A_MOVZX,A_MOVSX,A_LEA:
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begin
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changeOp(p.oper[1],reg1,reg2);
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changeOp(p.oper[0],reg2,reg1);
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end;
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A_IMUL:
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begin
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p.ops := 3;
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p.loadreg(2,p.oper[1].reg);
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changeOp(p.oper[2],reg1,reg2);
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end;
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A_INC,A_DEC:
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begin
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reference_reset(tmpref);
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tmpref.base := reg1;
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case p.opcode of
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A_INC:
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tmpref.offset := 1;
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A_DEC:
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tmpref.offset := -1;
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end;
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p.ops := 2;
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p.opcode := A_LEA;
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p.loadreg(1,reg2);
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p.loadref(0,tmpref);
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end;
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A_SUB,A_ADD:
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begin
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reference_reset(tmpref);
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tmpref.base := reg1;
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case p.oper[0].typ of
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top_const:
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begin
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tmpref.offset := p.oper[0].val;
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if p.opcode = A_SUB then
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tmpref.offset := - tmpRef.offset;
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end;
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top_symbol:
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tmpref.symbol := p.oper[0].sym;
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top_reg:
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begin
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tmpref.index := p.oper[0].reg;
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tmpref.scalefactor := 1;
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end;
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else internalerror(200010031);
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end;
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p.opcode := A_LEA;
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p.loadref(0,tmpref);
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p.loadreg(1,reg2);
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end;
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A_SHL:
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begin
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reference_reset(tmpref);
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tmpref.index := reg1;
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tmpref.scalefactor := 1 shl p.oper[0].val;
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p.opcode := A_LEA;
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p.loadref(0,tmpref);
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p.loadreg(1,reg2);
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end;
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else internalerror(200010032);
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end;
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end;
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function switchRegs(asml: TAAsmoutput; reg1, reg2: tregister; start: Tai): Boolean;
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{ change movl %reg1,%reg2 ... bla ... to ... bla with reg1 and reg2 switched }
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var
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endP, hp, lastreg1,lastreg2: Tai;
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switchDone, switchLast, tmpResult, sequenceEnd, reg1Modified, reg2Modified: boolean;
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reg1StillUsed, reg2StillUsed, isInstruction: boolean;
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begin
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switchRegs := false;
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tmpResult := true;
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sequenceEnd := false;
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reg1Modified := false;
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reg2Modified := false;
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endP := start;
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while tmpResult and not sequenceEnd do
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begin
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tmpResult :=
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getNextInstruction(endP,endP);
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If tmpResult and
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not pTaiprop(endp.optinfo)^.canBeRemoved then
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begin
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{ if the newReg gets stored back to the oldReg, we can change }
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{ "mov %oldReg,%newReg; <operations on %newReg>; mov %newReg, }
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{ %oldReg" to "<operations on %oldReg>" }
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switchLast := storeBack(endP,reg1,reg2);
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reg1StillUsed := reg1.enum in pTaiprop(endp.optinfo)^.usedregs;
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reg2StillUsed := reg2.enum in pTaiprop(endp.optinfo)^.usedregs;
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isInstruction := endp.typ = ait_instruction;
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sequenceEnd :=
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switchLast or
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{ if both registers are released right before an instruction }
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{ that contains hardcoded regs, it's ok too }
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(not reg1StillUsed and not reg2StillUsed) or
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{ no support for (i)div, mul and imul with hardcoded operands }
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(((not isInstruction) or
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noHardCodedRegs(Taicpu(endP),reg1,reg2)) and
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(not reg1StillUsed or
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(isInstruction and findRegDealloc(reg1,endP) and
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regLoadedWithNewValue(reg1,false,Taicpu(endP)))) and
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(not reg2StillUsed or
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(isInstruction and findRegDealloc(reg2,endP) and
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regLoadedWithNewValue(reg2,false,Taicpu(endP)))));
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{ we can't switch reg1 and reg2 in something like }
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{ movl %reg1,%reg2 }
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{ movl (%reg2),%reg2 }
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{ movl 4(%reg1),%reg1 }
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if reg2Modified and not(reg1Modified) and
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regReadByInstruction(reg1,endP) then
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begin
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tmpResult := false;
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break
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end;
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if not reg1Modified then
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begin
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reg1Modified := regModifiedByInstruction(reg1,endP);
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if reg1Modified and not canBeFirstSwitch(Taicpu(endP),reg1) then
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begin
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tmpResult := false;
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break;
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end;
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end;
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if not reg2Modified then
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reg2Modified := regModifiedByInstruction(reg2,endP);
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if sequenceEnd then
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break;
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tmpResult :=
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(endp.typ <> ait_label) and
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((not isInstruction) or
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(NoHardCodedRegs(Taicpu(endP),reg1,reg2) and
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RegSizesOk(reg1,reg2,Taicpu(endP)) and
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(Taicpu(endp).opcode <> A_JMP)));
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end;
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end;
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if tmpResult and sequenceEnd then
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begin
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switchRegs := true;
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reg1Modified := false;
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reg2Modified := false;
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lastreg1 := start;
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lastreg2 := start;
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getNextInstruction(start,hp);
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while hp <> endP do
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begin
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if (not pTaiprop(hp.optinfo)^.canberemoved) and
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(hp.typ = ait_instruction) then
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begin
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switchDone := false;
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if not reg1Modified then
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begin
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reg1Modified := regModifiedByInstruction(reg1,hp);
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if reg1Modified then
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begin
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doFirstSwitch(Taicpu(hp),reg1,reg2);
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switchDone := true;
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end;
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end;
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if not switchDone then
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if reg1Modified then
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doSwitchReg(Taicpu(hp),reg1,reg2)
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else
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doReplaceReg(Taicpu(hp),reg2,reg1);
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end;
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if regininstruction(reg1.enum,hp) then
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lastreg1 := hp;
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if regininstruction(reg2.enum,hp) then
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lastreg2 := hp;
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getNextInstruction(hp,hp);
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end;
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if switchLast then
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doSwitchReg(Taicpu(hp),reg1,reg2)
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else getLastInstruction(hp,hp);
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allocRegBetween(asmL,reg1,start,lastreg1);
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allocRegBetween(asmL,reg2,start,lastreg2);
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end;
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end;
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procedure doRenaming(asml: TAAsmoutput; first, last: Tai);
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var
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p: Tai;
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begin
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p := First;
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SkipHead(p);
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while p <> last do
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begin
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case p.typ of
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ait_instruction:
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begin
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case Taicpu(p).opcode of
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A_MOV:
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begin
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if not(pTaiprop(p.optinfo)^.canBeRemoved) and
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(Taicpu(p).oper[0].typ = top_reg) and
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(Taicpu(p).oper[1].typ = top_reg) and
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(Taicpu(p).opsize = S_L) and
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{ (Taicpu(p).oper[0].reg.enum in (rg.usableregsint+[R_EDI])) and
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(Taicpu(p).oper[1].reg.enum in (rg.usableregsint+[R_EDI])) then}
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(Taicpu(p).oper[0].reg.enum in ([R_EDI])) and
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(Taicpu(p).oper[1].reg.enum in ([R_EDI])) then
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if switchRegs(asml,Taicpu(p).oper[0].reg,
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Taicpu(p).oper[1].reg,p) then
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begin
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{ getnextinstruction(p,hp);
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asmL^.remove(p);
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dispose(p,done);
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p := hp;
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continue }
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pTaiprop(p.optinfo)^.canBeRemoved := true;
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end;
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end;
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end;
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end;
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end;
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getNextInstruction(p,p);
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end;
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end;
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End.
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{
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$Log$
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Revision 1.21 2003-03-28 19:16:57 peter
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* generic constructor working for i386
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* remove fixed self register
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* esi added as address register for i386
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Revision 1.20 2003/02/19 22:00:16 daniel
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* Code generator converted to new register notation
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- Horribily outdated todo.txt removed
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Revision 1.19 2003/01/08 18:43:57 daniel
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* Tregister changed into a record
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Revision 1.18 2002/07/01 18:46:34 peter
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* internal linker
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* reorganized aasm layer
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Revision 1.17 2002/05/18 13:34:26 peter
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* readded missing revisions
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Revision 1.16 2002/05/16 19:46:52 carl
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+ defines.inc -> fpcdefs.inc to avoid conflicts if compiling by hand
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+ try to fix temp allocation (still in ifdef)
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+ generic constructor calls
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+ start of tassembler / tmodulebase class cleanup
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Revision 1.14 2002/05/12 16:53:18 peter
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* moved entry and exitcode to ncgutil and cgobj
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* foreach gets extra argument for passing local data to the
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iterator function
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* -CR checks also class typecasts at runtime by changing them
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into as
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* fixed compiler to cycle with the -CR option
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* fixed stabs with elf writer, finally the global variables can
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be watched
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* removed a lot of routines from cga unit and replaced them by
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calls to cgobj
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* u32bit-s32bit updates for and,or,xor nodes. When one element is
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u32bit then the other is typecasted also to u32bit without giving
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a rangecheck warning/error.
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* fixed pascal calling method with reversing also the high tree in
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the parast, detected by tcalcst3 test
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Revision 1.13 2002/04/21 15:42:17 carl
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* changeregsize -> rg.makeregsize
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Revision 1.12 2002/04/20 21:37:08 carl
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+ generic FPC_CHECKPOINTER
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+ first parameter offset in stack now portable
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* rename some constants
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+ move some cpu stuff to other units
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- remove unused constents
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* fix stacksize for some targets
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* fix generic size problems which depend now on EXTEND_SIZE constant
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* removing frame pointer in routines is only available for : i386,m68k and vis targets
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Revision 1.11 2002/04/15 19:44:22 peter
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* fixed stackcheck that would be called recursively when a stack
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error was found
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* generic changeregsize(reg,size) for i386 register resizing
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* removed some more routines from cga unit
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* fixed returnvalue handling
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* fixed default stacksize of linux and go32v2, 8kb was a bit small :-)
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Revision 1.10 2002/04/02 17:11:39 peter
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* tlocation,treference update
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* LOC_CONSTANT added for better constant handling
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* secondadd splitted in multiple routines
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* location_force_reg added for loading a location to a register
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of a specified size
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* secondassignment parses now first the right and then the left node
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(this is compatible with Kylix). This saves a lot of push/pop especially
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with string operations
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* adapted some routines to use the new cg methods
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Revision 1.9 2002/03/31 20:26:41 jonas
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+ a_loadfpu_* and a_loadmm_* methods in tcg
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* register allocation is now handled by a class and is mostly processor
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independent (+rgobj.pas and i386/rgcpu.pas)
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* temp allocation is now handled by a class (+tgobj.pas, -i386\tgcpu.pas)
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* some small improvements and fixes to the optimizer
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* some register allocation fixes
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* some fpuvaroffset fixes in the unary minus node
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* push/popusedregisters is now called rg.save/restoreusedregisters and
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(for i386) uses temps instead of push/pop's when using -Op3 (that code is
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also better optimizable)
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* fixed and optimized register saving/restoring for new/dispose nodes
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* LOC_FPU locations now also require their "register" field to be set to
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R_ST, not R_ST0 (the latter is used for LOC_CFPUREGISTER locations only)
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- list field removed of the tnode class because it's not used currently
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and can cause hard-to-find bugs
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}
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