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555 lines
16 KiB
ObjectPascal
555 lines
16 KiB
ObjectPascal
{
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Copyright (c) 1998-2002 by Florian Klaempfl
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Contains the base types for the SPARC
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit cpubase;
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{$i fpcdefs.inc}
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{$ModeSwitch advancedrecords}
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interface
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uses
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globtype,strings,cutils,cclasses,aasmbase,cpuinfo,cgbase;
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{*****************************************************************************
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Assembler Opcodes
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*****************************************************************************}
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type
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{ TODO: CPU32 opcodes do not fully include the Ultra SPRAC instruction set.}
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{ don't change the order of these opcodes! }
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TAsmOp=({$i opcode.inc});
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{# This should define the array of instructions as string }
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op2strtable=array[tasmop] of string[11];
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Const
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{# First value of opcode enumeration }
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firstop = low(tasmop);
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{# Last value of opcode enumeration }
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lastop = high(tasmop);
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std_op2str:op2strtable=({$i strinst.inc});
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{*****************************************************************************
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Registers
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*****************************************************************************}
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{$ifdef SPARC}
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type
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{ Number of registers used for indexing in tables }
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tregisterindex=0..{$i rspnor.inc}-1;
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totherregisterset = set of tregisterindex;
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const
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{ Available Superregisters }
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{$i rspsup.inc}
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{ No Subregisters }
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R_SUBWHOLE = R_SUBNONE;
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{ Available Registers }
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{$i rspcon.inc}
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first_int_imreg = $20;
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first_fpu_imreg = $20;
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{ MM Super register first and last }
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first_mm_supreg = 0;
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first_mm_imreg = 1;
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{ TODO: Calculate bsstart}
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regnumber_count_bsstart = 128;
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regnumber_table : array[tregisterindex] of tregister = (
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{$i rspnum.inc}
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);
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regstabs_table : array[tregisterindex] of ShortInt = (
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{$i rspstab.inc}
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);
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regdwarf_table : array[tregisterindex] of ShortInt = (
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{$i rspdwrf.inc}
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);
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{ Aliases for full register LoadStore instructions }
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A_ST_R = A_ST;
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A_LD_R = A_LD;
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{$endif SPARC}
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{$ifdef SPARC64}
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type
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{ Number of registers used for indexing in tables }
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tregisterindex=0..{$i rsp64nor.inc}-1;
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totherregisterset = set of tregisterindex;
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const
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{ Available Superregisters }
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{$i rsp64sup.inc}
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{ No Subregisters }
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R_SUBWHOLE = R_SUBNONE;
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{ Available Registers }
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{$i rsp64con.inc}
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first_int_imreg = $20;
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first_fpu_imreg = $20;
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{ MM Super register first and last }
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first_mm_supreg = 0;
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first_mm_imreg = 1;
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{ TODO: Calculate bsstart}
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regnumber_count_bsstart = 128;
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regnumber_table : array[tregisterindex] of tregister = (
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{$i rsp64num.inc}
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);
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regstabs_table : array[tregisterindex] of ShortInt = (
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{$i rsp64stab.inc}
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);
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regdwarf_table : array[tregisterindex] of ShortInt = (
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{$i rsp64dwrf.inc}
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);
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{ Aliases for full register LoadStore instructions }
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A_ST_R = A_STX;
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A_LD_R = A_LDX;
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{$endif SPARC64}
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{*****************************************************************************
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Conditions
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*****************************************************************************}
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type
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TAsmCond=(C_None,
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C_A,C_AE,C_B,C_BE,
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C_G,C_GE,C_L,C_LE,
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C_E,C_NE,
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C_POS,C_NEG,C_VC,C_VS,
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C_FE,C_FG,C_FL,C_FGE,C_FLE,C_FNE,
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C_FU,C_FUG,C_FUL,C_FUGE,C_FULE,C_FO,C_FUE,C_FLG
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);
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const
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firstIntCond=C_A;
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lastIntCond=C_VS;
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firstFloatCond=C_FE;
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lastFloatCond=C_FNE;
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floatAsmConds=[C_FE..C_FLG];
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cond2str:array[TAsmCond] of string[3]=('',
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'gu','cc','cs','leu',
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'g','ge','l','le',
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'e','ne',
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'pos','neg','vc','vs',
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'e','g','l','ge','le','ne',
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'u','ug','ul','uge','ule','o','ue','lg'
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);
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{*****************************************************************************
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Flags
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*****************************************************************************}
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type
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TSparcFlags = (
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{ Integer results }
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F_E, {Equal}
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F_NE, {Not Equal}
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F_G, {Greater}
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F_L, {Less}
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F_GE, {Greater or Equal}
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F_LE, {Less or Equal}
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F_A, {Above}
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F_AE, {Above or Equal, synonym: Carry Clear}
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F_B, {Below, synonym: Carry Set}
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F_BE, {Below or Equal}
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{ Floating point results }
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F_FE, {Equal}
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F_FNE, {Not Equal}
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F_FG, {Greater}
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F_FL, {Less}
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F_FGE, {Greater or Equal}
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F_FLE {Less or Equal}
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);
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TResFlags = record
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{ either icc or xcc (64 bit }
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FlagReg : TRegister;
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Flags : TSparcFlags;
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procedure Init(r : TRegister;f : TSparcFlags);
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end;
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{*****************************************************************************
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Operand Sizes
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*****************************************************************************}
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{*****************************************************************************
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Constants
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*****************************************************************************}
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const
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max_operands = 3;
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maxintregs = 8;
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maxfpuregs = 8;
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maxaddrregs = 0;
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maxvarregs = 8;
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varregs : Array [1..maxvarregs] of Tsuperregister =
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(RS_L0,RS_L1,RS_L2,RS_L3,RS_L4,RS_L5,RS_L6,RS_L7);
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maxfpuvarregs = 1;
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fpuvarregs : Array [1..maxfpuvarregs] of TsuperRegister =
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(RS_F2);
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{*****************************************************************************
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Default generic sizes
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*****************************************************************************}
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{$ifdef SPARC64}
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{# Defines the default address size for a processor, }
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OS_ADDR = OS_64;
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{# the natural int size for a processor,
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has to match osuinttype/ossinttype as initialized in psystem }
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OS_INT = OS_64;
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OS_SINT = OS_S64;
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{$else SPARC64}
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{# Defines the default address size for a processor, }
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OS_ADDR = OS_32;
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{# the natural int size for a processor,
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has to match osuinttype/ossinttype as initialized in psystem }
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OS_INT = OS_32;
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OS_SINT = OS_S32;
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{$endif SPARC64}
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{# the maximum float size for a processor, }
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OS_FLOAT = OS_F64;
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{# the size of a vector register for a processor }
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OS_VECTOR = OS_M64;
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{*****************************************************************************
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Generic Register names
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*****************************************************************************}
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{# Stack pointer register }
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NR_STACK_POINTER_REG = NR_O6;
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RS_STACK_POINTER_REG = RS_O6;
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{# Frame pointer register }
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NR_FRAME_POINTER_REG = NR_I6;
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RS_FRAME_POINTER_REG = RS_I6;
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{# Register for addressing absolute data in a position independant way,
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such as in PIC code. The exact meaning is ABI specific. For
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further information look at GCC source : PIC_OFFSET_TABLE_REGNUM
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Taken from GCC rs6000.h
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}
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{ TODO: As indicated in rs6000.h, but can't find it anywhere else!}
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{PIC_OFFSET_REG = R_30;}
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{ Return address for DWARF }
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NR_RETURN_ADDRESS_REG = NR_I7;
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{ the return_result_reg, is used inside the called function to store its return
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value when that is a scalar value otherwise a pointer to the address of the
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result is placed inside it }
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{ Results are returned in this register (32-bit values) }
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NR_FUNCTION_RETURN_REG = NR_I0;
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RS_FUNCTION_RETURN_REG = RS_I0;
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{ Low part of 64bit return value }
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NR_FUNCTION_RETURN64_LOW_REG = NR_I1;
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RS_FUNCTION_RETURN64_LOW_REG = RS_I1;
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{ High part of 64bit return value }
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NR_FUNCTION_RETURN64_HIGH_REG = NR_I0;
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RS_FUNCTION_RETURN64_HIGH_REG = RS_I0;
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{ The value returned from a function is available in this register }
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NR_FUNCTION_RESULT_REG = NR_O0;
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RS_FUNCTION_RESULT_REG = RS_O0;
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{ The lowh part of 64bit value returned from a function }
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NR_FUNCTION_RESULT64_LOW_REG = NR_O1;
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RS_FUNCTION_RESULT64_LOW_REG = RS_O1;
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{ The high part of 64bit value returned from a function }
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NR_FUNCTION_RESULT64_HIGH_REG = NR_O0;
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RS_FUNCTION_RESULT64_HIGH_REG = RS_O0;
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NR_FPU_RESULT_REG = NR_F0;
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NR_MM_RESULT_REG = NR_NO;
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PARENT_FRAMEPOINTER_OFFSET = 68; { o0 }
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NR_DEFAULTFLAGS = NR_PSR;
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RS_DEFAULTFLAGS = RS_PSR;
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{*****************************************************************************
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GCC /ABI linking information
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*****************************************************************************}
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{# Required parameter alignment when calling a routine declared as
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stdcall and cdecl. The alignment value should be the one defined
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by GCC or the target ABI.
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The value of this constant is equal to the constant
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PARM_BOUNDARY / BITS_PER_UNIT in the GCC source.
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}
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std_param_align = sizeof(AWord);
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{$ifdef SPARC64}
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STACK_BIAS = 2047;
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{$endif SPARC64}
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{*****************************************************************************
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CPU Dependent Constants
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*****************************************************************************}
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const
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simm13lo=-4096;
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simm13hi=4095;
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{*****************************************************************************
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Helpers
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*****************************************************************************}
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function is_calljmp(o:tasmop):boolean;
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procedure inverse_flags(var f: TResFlags);
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function inverse_cond(const c: TAsmCond): TAsmCond; {$ifdef USEINLINE}inline;{$endif USEINLINE}
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function conditions_equal(const c1, c2: TAsmCond): boolean; {$ifdef USEINLINE}inline;{$endif USEINLINE}
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function flags_to_cond(const f: TResFlags) : TAsmCond;
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function cgsize2subreg(regtype: tregistertype; s:Tcgsize):Tsubregister;
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function reg_cgsize(const reg: tregister): tcgsize;
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function std_regname(r:Tregister):string;
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function std_regnum_search(const s:string):Tregister;
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function findreg_by_number(r:Tregister):tregisterindex;
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function dwarf_reg(r:tregister):shortint;
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function dwarf_reg_no_error(r:tregister):shortint;
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function eh_return_data_regno(nr: longint): longint;
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implementation
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uses
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rgBase,verbose;
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{$ifdef SPARC}
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const
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std_regname_table : TRegNameTAble = (
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{$i rspstd.inc}
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);
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regnumber_index : TRegisterIndexTable = (
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{$i rsprni.inc}
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);
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std_regname_index : TRegisterIndexTable = (
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{$i rspsri.inc}
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);
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{$endif SPARC}
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{$ifdef SPARC64}
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const
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std_regname_table : TRegNameTAble = (
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{$i rsp64std.inc}
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);
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regnumber_index : TRegisterIndexTable = (
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{$i rsp64rni.inc}
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);
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std_regname_index : TRegisterIndexTable = (
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{$i rsp64sri.inc}
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);
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{$endif SPARC64}
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{*****************************************************************************
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Helpers
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*****************************************************************************}
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function is_calljmp(o:tasmop):boolean;
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const
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CallJmpOp=[A_JMPL..A_CBccc];
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begin
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is_calljmp:=(o in CallJmpOp);
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end;
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procedure inverse_flags(var f: TResFlags);
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const
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inv_flags: array[TSparcFlags] of TSparcFlags =
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(F_NE,F_E,F_LE,F_GE,F_L,F_G,F_BE,F_B,F_AE,F_A,
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F_FNE,F_FE,F_FLE,F_FGE,F_FL,F_FG);
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begin
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f.Flags:=inv_flags[f.Flags];
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end;
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function flags_to_cond(const f:TResFlags):TAsmCond;
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const
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flags_2_cond:array[TSparcFlags] of TAsmCond=
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(C_E,C_NE,C_G,C_L,C_GE,C_LE,C_A,C_AE,C_B,C_BE,
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C_FE,C_FNE,C_FG,C_FL,C_FGE,C_FLE);
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begin
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result:=flags_2_cond[f.Flags];
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end;
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function cgsize2subreg(regtype: tregistertype; s:Tcgsize):Tsubregister;
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begin
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case regtype of
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R_FPUREGISTER:
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case s of
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OS_F32:
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cgsize2subreg:=R_SUBFS;
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OS_F64:
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cgsize2subreg:=R_SUBFD;
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OS_F128:
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cgsize2subreg:=R_SUBFQ;
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else
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internalerror(2009071903);
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end;
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else
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begin
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{$ifdef SPARC32}
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if s in [OS_64,OS_S64] then
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cgsize2subreg:=R_SUBQ
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else
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{$endif SPARC32}
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cgsize2subreg:=R_SUBWHOLE;
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end;
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end;
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end;
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function reg_cgsize(const reg: tregister): tcgsize;
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begin
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case getregtype(reg) of
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R_INTREGISTER :
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result:=OS_INT;
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R_FPUREGISTER :
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begin
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if getsubreg(reg)=R_SUBFD then
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result:=OS_F64
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else
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result:=OS_F32;
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end;
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else
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internalerror(200303181);
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end;
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end;
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function findreg_by_number(r:Tregister):tregisterindex;
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begin
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result:=findreg_by_number_table(r,regnumber_index);
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end;
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function std_regname(r:Tregister):string;
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var
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p : tregisterindex;
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begin
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{ For double floats show a pair like %f0:%f1 }
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if (getsubreg(r)=R_SUBFD) and
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(getsupreg(r)<first_fpu_imreg) then
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begin
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setsubreg(r,R_SUBFS);
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p:=findreg_by_number(r);
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if p<>0 then
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result:=std_regname_table[p]
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else
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result:=generic_regname(r);
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setsupreg(r,getsupreg(r)+1);
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p:=findreg_by_number(r);
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if p<>0 then
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result:=result+':'+std_regname_table[p]
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else
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result:=result+':'+generic_regname(r);
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end
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else
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begin
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p:=findreg_by_number(r);
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if p<>0 then
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result:=std_regname_table[p]
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else
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result:=generic_regname(r);
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end;
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end;
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function std_regnum_search(const s:string):Tregister;
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begin
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result:=regnumber_table[findreg_by_name_table(s,std_regname_table,std_regname_index)];
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end;
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function inverse_cond(const c: TAsmCond): TAsmCond; {$ifdef USEINLINE}inline;{$endif USEINLINE}
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const
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inverse: array[TAsmCond] of TAsmCond=(C_None,
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C_BE,C_B,C_AE,C_A,
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C_LE,C_L,C_GE,C_G,
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C_NE,C_E,
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C_NEG,C_POS,C_VS,C_VC,
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C_FNE,C_FULE,C_FUGE,C_FUL,C_FUG,C_FE,
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C_FO,C_FLE,C_FGE,C_FL,C_FG,C_FU,C_FLG,C_FUE
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);
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begin
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result := inverse[c];
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end;
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function conditions_equal(const c1, c2: TAsmCond): boolean; {$ifdef USEINLINE}inline;{$endif USEINLINE}
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begin
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result := c1 = c2;
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end;
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function dwarf_reg(r:tregister):shortint;
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begin
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result:=regdwarf_table[findreg_by_number(r)];
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if result=-1 then
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internalerror(200603251);
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end;
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function dwarf_reg_no_error(r:tregister):shortint;
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begin
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result:=regdwarf_table[findreg_by_number(r)];
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end;
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function eh_return_data_regno(nr: longint): longint;
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begin
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if (nr>=0) and (nr<2) then
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result:=nr+24
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|
else
|
|
result:=-1;
|
|
end;
|
|
|
|
|
|
procedure TResFlags.Init(r : TRegister; f : TSparcFlags);
|
|
begin
|
|
FlagReg:=r;
|
|
Flags:=f;
|
|
end;
|
|
|
|
end.
|