fpc/compiler/arm/rarmcon.inc
Jonas Maebe d1538ab023 o added ARM VPFv2/VFPv3 support:
+ RTL support:
      o VFP exceptions are disabled by default on Darwin,
        because they cause kernel panics on iPhoneOS 2.2.1 at least
      o all denormals are truncated to 0 on Darwin, because disabling
        that also causes kernel panics on iPhoneOS 2.2.1 (probably
        because otherwise denormals can also cause exceptions)
    * set softfloat rounding mode correctly for non-wince/darwin/vfp
      targets
    + compiler support: only half the number of single precision
      registers is available due to limitations of the register
      allocator
    + added a number of comments about why the stackframe on ARM is
      set up the way it is by the compiler
    + added regtype and subregtype info to regsets, because they're
      also used for VFP registers (+ support in assembler reader)
    + various generic support routines for dealing with floating point
      values located in integer registers that have to be transferred to
      mm registers (needed for VFP)
    * renamed use_sse() to use_vectorfpu() and also use it for
      ARM/vfp support
    o only superficially tested for Linux (compiler compiled with -Cpvfpv6
      -Cfvfpv2 works on a Cortex-A8, no testsuite run performed -- at least
      the fpu exception handler still needs to be implemented), Darwin has
      been tested more thoroughly
  + added ARMv6 cpu type and made it default for Darwin/ARM
  + ARMv6+ implementations of atomic operations using ldrex/strex
  * don't use r9 on Darwin/ARM, as it's reserved under certain
    circumstances (don't know yet which ones)
  * changed C-test object files for ARM/Darwin to ARMv6 versions
  * check in assembler reader that regsets are not empty, because
    instructions with a regset operand have undefined behaviour in that
    case
  * fixed resultdef of tarmtypeconvnode.first_int_to_real in case of
    int64->single type conversion
  * fixed constant pool locations in case 64 bit constants are generated,
    and/or when vfp instructions with limited reach are present

  WARNING: when using VFP on an ARMv6 or later cpu, you *must* compile all
    code with -Cparmv6 (or higher), or you will get crashes. The reason is
    that storing/restoring multiple VFP registers must happen using
    different instructions on pre/post-ARMv6.

git-svn-id: trunk@14317 -
2009-12-03 22:46:30 +00:00

93 lines
2.8 KiB
PHP

{ don't edit, this file is generated from armreg.dat }
NR_NO = tregister($00000000);
NR_R0 = tregister($01000000);
NR_R1 = tregister($01000001);
NR_R2 = tregister($01000002);
NR_R3 = tregister($01000003);
NR_R4 = tregister($01000004);
NR_R5 = tregister($01000005);
NR_R6 = tregister($01000006);
NR_R7 = tregister($01000007);
NR_R8 = tregister($01000008);
NR_R9 = tregister($01000009);
NR_R10 = tregister($0100000a);
NR_R11 = tregister($0100000b);
NR_R12 = tregister($0100000c);
NR_R13 = tregister($0100000d);
NR_R14 = tregister($0100000e);
NR_R15 = tregister($0100000f);
NR_F0 = tregister($02000000);
NR_F1 = tregister($02000001);
NR_F2 = tregister($02000002);
NR_F3 = tregister($02000003);
NR_F4 = tregister($02000004);
NR_F5 = tregister($02000005);
NR_F6 = tregister($02000006);
NR_F7 = tregister($02000007);
NR_S0 = tregister($04060000);
NR_S1 = tregister($04060000);
NR_D0 = tregister($04070000);
NR_S2 = tregister($04060001);
NR_S3 = tregister($04060001);
NR_D1 = tregister($04070001);
NR_S4 = tregister($04060002);
NR_S5 = tregister($04060002);
NR_D2 = tregister($04070002);
NR_S6 = tregister($04060003);
NR_S7 = tregister($04060003);
NR_D3 = tregister($04070003);
NR_S8 = tregister($04060004);
NR_S9 = tregister($04060004);
NR_D4 = tregister($04070004);
NR_S10 = tregister($04060005);
NR_S11 = tregister($04060005);
NR_D5 = tregister($04070005);
NR_S12 = tregister($04060006);
NR_S13 = tregister($04060006);
NR_D6 = tregister($04070006);
NR_S14 = tregister($04060007);
NR_S15 = tregister($04060007);
NR_D7 = tregister($04070007);
NR_S16 = tregister($04060008);
NR_S17 = tregister($04060008);
NR_D8 = tregister($04070008);
NR_S18 = tregister($04060009);
NR_S19 = tregister($04060009);
NR_D9 = tregister($04070009);
NR_S20 = tregister($0406000A);
NR_S21 = tregister($0406000A);
NR_D10 = tregister($0407000A);
NR_S22 = tregister($0406000B);
NR_S23 = tregister($0406000B);
NR_D11 = tregister($0407000B);
NR_S24 = tregister($0406000C);
NR_S25 = tregister($0406000C);
NR_D12 = tregister($0407000C);
NR_S26 = tregister($0406000D);
NR_S27 = tregister($0406000D);
NR_D13 = tregister($0407000D);
NR_S28 = tregister($0406000E);
NR_S29 = tregister($0406000E);
NR_D14 = tregister($0407000E);
NR_S30 = tregister($0406000F);
NR_S31 = tregister($0406000F);
NR_D15 = tregister($0407000F);
NR_D16 = tregister($04070010);
NR_D17 = tregister($04070011);
NR_D18 = tregister($04070012);
NR_D19 = tregister($04070013);
NR_D20 = tregister($04070014);
NR_D21 = tregister($04070015);
NR_D22 = tregister($04070016);
NR_D23 = tregister($04070017);
NR_D24 = tregister($04070018);
NR_D25 = tregister($04070019);
NR_D26 = tregister($0407001A);
NR_D27 = tregister($0407001B);
NR_D28 = tregister($0407001C);
NR_D29 = tregister($0407001D);
NR_D30 = tregister($0407001E);
NR_D31 = tregister($0407001F);
NR_CPSR_C = tregister($05000000);
NR_FPSCR = tregister($05000001);