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https://gitlab.com/freepascal.org/fpc/source.git
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1001 lines
41 KiB
ObjectPascal
1001 lines
41 KiB
ObjectPascal
{
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Copyright (c) 1998-2002 by Florian Klaempfl and Carl Eric Codere
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Generate generic inline nodes
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit ncginl;
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{$i fpcdefs.inc}
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interface
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uses
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node,ninl,symtype;
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type
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tcginlinenode = class(tinlinenode)
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procedure pass_generate_code;override;
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procedure pass_generate_code_cpu;virtual;
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procedure second_sizeoftypeof;virtual;
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procedure second_length;virtual;
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procedure second_predsucc;virtual;
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procedure second_incdec;virtual;
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procedure second_AndOrXorShiftRot_assign;virtual;
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procedure second_NegNot_assign;virtual;
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procedure second_typeinfo;virtual;
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procedure second_includeexclude;virtual;
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procedure second_pi; virtual;
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procedure second_arctan_real; virtual;
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procedure second_abs_real; virtual;
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procedure second_sqr_real; virtual;
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procedure second_sqrt_real; virtual;
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procedure second_ln_real; virtual;
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procedure second_cos_real; virtual;
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procedure second_sin_real; virtual;
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procedure second_assigned; virtual;
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procedure second_get_frame;virtual;
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procedure second_get_caller_frame;virtual;
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procedure second_get_caller_addr;virtual;
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procedure second_prefetch; virtual;
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procedure second_round_real; virtual;
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procedure second_trunc_real; virtual;
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procedure second_int_real; virtual;
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procedure second_abs_long; virtual;
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procedure second_rox_sar; virtual;
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procedure second_bsfbsr; virtual;
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procedure second_new; virtual;
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procedure second_setlength; virtual; abstract;
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procedure second_box; virtual; abstract;
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procedure second_popcnt; virtual;
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procedure second_seg; virtual; abstract;
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procedure second_fma; virtual;
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procedure second_frac_real; virtual;
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procedure second_high; virtual;
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procedure second_minmax; virtual;
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protected
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function second_incdec_tempregdef: tdef;virtual;
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end;
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implementation
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uses
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globtype,constexp,
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verbose,globals,compinnr,
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symconst,symdef,defutil,
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aasmbase,aasmdata,
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cgbase,pass_2,
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cpubase,procinfo,
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ncon,ncal,
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tgobj,ncgutil,
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cgutils,cgobj,hlcgobj,
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defcmp
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{$if not defined(cpu64bitalu) and not defined(cpuhighleveltarget)}
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,cg64f32
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{$endif not cpu64bitalu and not cpuhighleveltarget}
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;
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{*****************************************************************************
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TCGINLINENODE
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*****************************************************************************}
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procedure tcginlinenode.pass_generate_code;
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begin
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location_reset(location,LOC_VOID,OS_NO);
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case inlinenumber of
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in_sizeof_x,
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in_typeof_x :
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second_SizeofTypeOf;
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in_length_x :
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second_Length;
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in_pred_x,
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in_succ_x:
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second_PredSucc;
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in_dec_x,
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in_inc_x :
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second_IncDec;
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in_typeinfo_x:
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second_TypeInfo;
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in_include_x_y,
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in_exclude_x_y:
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second_IncludeExclude;
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in_pi_real:
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second_pi;
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in_sin_real:
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second_sin_real;
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in_arctan_real:
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second_arctan_real;
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in_abs_real:
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second_abs_real;
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in_abs_long:
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second_abs_long;
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in_round_real:
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second_round_real;
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in_trunc_real:
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second_trunc_real;
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in_int_real:
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second_int_real;
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in_sqr_real:
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second_sqr_real;
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in_sqrt_real:
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second_sqrt_real;
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in_ln_real:
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second_ln_real;
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in_cos_real:
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second_cos_real;
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in_frac_real:
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second_frac_real;
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in_prefetch_var:
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second_prefetch;
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in_assigned_x:
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second_assigned;
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in_get_frame:
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second_get_frame;
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in_get_caller_frame:
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second_get_caller_frame;
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in_get_caller_addr:
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second_get_caller_addr;
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in_unaligned_x:
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begin
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secondpass(tcallparanode(left).left);
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location:=tcallparanode(left).left.location;
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if location.loc in [LOC_CREFERENCE,LOC_REFERENCE] then
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location.reference.alignment:=1;
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end;
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in_aligned_x:
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begin
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secondpass(tcallparanode(left).left);
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location:=tcallparanode(left).left.location;
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if location.loc in [LOC_CREFERENCE,LOC_REFERENCE] then
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location.reference.alignment:=resultdef.alignment;
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end;
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in_volatile_x:
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begin
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secondpass(tcallparanode(left).left);
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location:=tcallparanode(left).left.location;
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if location.loc in [LOC_CREFERENCE,LOC_REFERENCE,LOC_SUBSETREF,LOC_CSUBSETREF] then
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location.reference.volatility:=[vol_read,vol_write];
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end;
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{$ifdef SUPPORT_MMX}
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in_mmx_pcmpeqb..in_mmx_pcmpgtw:
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begin
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location_reset(location,LOC_MMXREGISTER,OS_NO);
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if left.location.loc=LOC_REGISTER then
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begin
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{!!!!!!!}
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end
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else if tcallparanode(left).left.location.loc=LOC_REGISTER then
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begin
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{!!!!!!!}
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end
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else
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begin
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{!!!!!!!}
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end;
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end;
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{$endif SUPPORT_MMX}
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in_rol_x,
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in_rol_x_y,
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in_ror_x,
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in_ror_x_y,
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in_sar_x,
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in_sar_x_y:
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second_rox_sar;
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in_bsf_x,
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in_bsr_x:
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second_BsfBsr;
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in_new_x:
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second_new;
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in_setlength_x:
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second_setlength;
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in_box_x:
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second_box;
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in_popcnt_x:
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second_popcnt;
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in_seg_x:
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second_seg;
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in_fma_single,
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in_fma_double,
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in_fma_extended,
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in_fma_float128:
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second_fma;
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in_max_longint,
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in_max_dword,
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in_min_longint,
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in_min_dword,
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in_min_single,
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in_min_double,
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in_max_single,
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in_max_double:
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second_minmax;
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in_and_assign_x_y,
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in_or_assign_x_y,
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in_xor_assign_x_y,
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in_sar_assign_x_y,
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in_shl_assign_x_y,
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in_shr_assign_x_y,
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in_rol_assign_x_y,
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in_ror_assign_x_y:
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second_AndOrXorShiftRot_assign;
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in_neg_assign_x,
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in_not_assign_x:
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second_NegNot_assign;
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in_high_x:
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second_high;
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else
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pass_generate_code_cpu;
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end;
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end;
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procedure tcginlinenode.pass_generate_code_cpu;
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begin
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Internalerror(2017110103);
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end;
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{*****************************************************************************
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SIZEOF / TYPEOF GENERIC HANDLING
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*****************************************************************************}
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{ second_handle_ the sizeof and typeof routines }
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procedure tcginlinenode.second_SizeOfTypeOf;
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begin
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{ handled in pass 1 }
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internalerror(2015122701);
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end;
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{*****************************************************************************
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LENGTH GENERIC HANDLING
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*****************************************************************************}
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procedure tcginlinenode.second_Length;
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var
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lengthlab : tasmlabel;
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hregister : tregister;
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lendef : tdef;
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href : treference;
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begin
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secondpass(left);
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if is_shortstring(left.resultdef) then
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begin
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location_copy(location,left.location);
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location.size:=OS_8;
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end
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else
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begin
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{ length in ansi/wide strings and high in dynamic arrays is at offset -sizeof(pint) }
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,false);
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current_asmdata.getjumplabel(lengthlab);
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hlcg.a_cmp_const_reg_label(current_asmdata.CurrAsmList,left.resultdef,OC_EQ,0,left.location.register,lengthlab);
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{ the length of a widestring is a 32 bit unsigned int. Since every
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character occupies 2 bytes, on a 32 bit platform you can express
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the maximum length using 31 bits. On a 64 bit platform, it may be
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32 bits. This means that regardless of the platform, a location
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with size OS_SINT/ossinttype can hold the length without
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overflowing (this code returns an ossinttype value) }
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if is_widestring(left.resultdef) then
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lendef:=u32inttype
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else
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lendef:=ossinttype;
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{ volatility of the ansistring/widestring refers to the volatility of the
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string pointer, not of the string data }
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hlcg.reference_reset_base(href,left.resultdef,left.location.register,-lendef.size,ctempposinvalid,lendef.alignment,[]);
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{ if the string pointer is nil, the length is 0 -> reuse the register
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that originally held the string pointer for the length, so that we
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can keep the original nil/0 as length in that case }
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hregister:=cg.makeregsize(current_asmdata.CurrAsmList,left.location.register,def_cgsize(resultdef));
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hlcg.a_load_ref_reg(current_asmdata.CurrAsmList,lendef,resultdef,href,hregister);
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if is_widestring(left.resultdef) then
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hlcg.a_op_const_reg(current_asmdata.CurrAsmList,OP_SHR,resultdef,1,hregister);
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{ Dynamic arrays do not have their length attached but their maximum index }
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if is_dynamic_array(left.resultdef) then
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hlcg.a_op_const_reg(current_asmdata.CurrAsmList,OP_ADD,resultdef,1,hregister);
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cg.a_label(current_asmdata.CurrAsmList,lengthlab);
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location_reset(location,LOC_REGISTER,def_cgsize(resultdef));
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location.register:=hregister;
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end;
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end;
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{*****************************************************************************
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HIGH(<dyn. array>) GENERIC HANDLING
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*****************************************************************************}
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procedure tcginlinenode.second_high;
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var
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loadlab, nillab, donelab: tasmlabel;
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hregister : tregister;
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href : treference;
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begin
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secondpass(left);
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if not(is_dynamic_array(left.resultdef)) then
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Internalerror(2019122801);
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{ length in dynamic arrays is at offset -sizeof(pint) }
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,false);
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current_asmdata.getjumplabel(loadlab);
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current_asmdata.getjumplabel(nillab);
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current_asmdata.getjumplabel(donelab);
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hlcg.a_cmp_const_reg_label(current_asmdata.CurrAsmList,left.resultdef,OC_EQ,0,left.location.register,nillab);
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{ volatility of the dyn. array refers to the volatility of the
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string pointer, not of the string data }
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hlcg.reference_reset_base(href,left.resultdef,left.location.register,-ossinttype.size,ctempposinvalid,ossinttype.alignment,[]);
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{ if the string pointer is nil, the length is 0 -> reuse the register
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that originally held the string pointer for the length, so that we
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can keep the original nil/0 as length in that case }
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hregister:=cg.makeregsize(current_asmdata.CurrAsmList,left.location.register,def_cgsize(resultdef));
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hlcg.a_load_ref_reg(current_asmdata.CurrAsmList,ossinttype,resultdef,href,hregister);
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hlcg.a_jmp_always(current_asmdata.CurrAsmList,donelab);
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cg.a_label(current_asmdata.CurrAsmList,nillab);
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hlcg.a_op_const_reg(current_asmdata.CurrAsmList,OP_SUB,resultdef,1,hregister);
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cg.a_label(current_asmdata.CurrAsmList,donelab);
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location_reset(location,LOC_REGISTER,def_cgsize(resultdef));
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location.register:=hregister;
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end;
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{*****************************************************************************
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PRED/SUCC GENERIC HANDLING
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*****************************************************************************}
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procedure tcginlinenode.second_PredSucc;
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var
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cgop : topcg;
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begin
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secondpass(left);
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if inlinenumber=in_pred_x then
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cgop:=OP_SUB
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else
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cgop:=OP_ADD;
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location_reset(location,LOC_REGISTER,def_cgsize(resultdef));
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if not(left.location.loc in [LOC_REGISTER,LOC_CREGISTER]) then
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,false);
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{$if not defined(cpu64bitalu) and not defined(cpuhighleveltarget)}
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if def_cgsize(resultdef) in [OS_64,OS_S64] then
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begin
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location.register64.reglo:=cg.getintregister(current_asmdata.CurrAsmList,OS_32);
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location.register64.reghi:=cg.getintregister(current_asmdata.CurrAsmList,OS_32);
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cg64.a_op64_const_reg_reg(current_asmdata.CurrAsmList,cgop,def_cgsize(resultdef),1,left.location.register64,location.register64);
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end
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else
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{$endif not cpu64bitalu and not cpuhighleveltarget}
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begin
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location.register:=hlcg.getregisterfordef(current_asmdata.CurrAsmList,resultdef);
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hlcg.a_op_const_reg_reg(current_asmdata.CurrAsmList,cgop,resultdef,1,left.location.register,location.register);
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end;
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end;
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{*****************************************************************************
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INC/DEC GENERIC HANDLING
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*****************************************************************************}
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function tcginlinenode.second_incdec_tempregdef: tdef;
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begin
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second_incdec_tempregdef:=left.resultdef;
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end;
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procedure tcginlinenode.second_IncDec;
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const
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addsubop:array[in_inc_x..in_dec_x] of TOpCG=(OP_ADD,OP_SUB);
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var
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addvalue : TConstExprInt;
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addconstant : boolean;
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{$if not defined(cpu64bitalu) and not defined(cpuhighleveltarget)}
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hregisterhi,
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{$endif not cpu64bitalu and not cpuhighleveltarget}
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hregister : tregister;
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begin
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{ set defaults }
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addconstant:=true;
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hregister:=NR_NO;
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{$if not defined(cpu64bitalu) and not defined(cpuhighleveltarget)}
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hregisterhi:=NR_NO;
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{$endif not cpu64bitalu and not cpuhighleveltarget}
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{ first secondpass second argument, because if the first arg }
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{ is used in that expression then SSL may move it to another }
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{ register }
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if assigned(tcallparanode(left).right) then
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secondpass(tcallparanode(tcallparanode(left).right).left);
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{ load first parameter, must be a reference }
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secondpass(tcallparanode(left).left);
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{ get addvalue }
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case tcallparanode(left).left.resultdef.typ of
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orddef,
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enumdef :
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addvalue:=1;
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pointerdef :
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begin
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if is_void(tpointerdef(tcallparanode(left).left.resultdef).pointeddef) then
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addvalue:=1
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else
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addvalue:=tpointerdef(tcallparanode(left).left.resultdef).pointeddef.size;
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end;
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else
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internalerror(2020100814);
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end;
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{ second_ argument specified?, must be a s32bit in register }
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if assigned(tcallparanode(left).right) then
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begin
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{ when constant, just multiply the addvalue }
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if is_constintnode(tcallparanode(tcallparanode(left).right).left) then
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addvalue:=addvalue*get_ordinal_value(tcallparanode(tcallparanode(left).right).left)
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else if is_constpointernode(tcallparanode(tcallparanode(left).right).left) then
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addvalue:=addvalue*tpointerconstnode(tcallparanode(tcallparanode(left).right).left).value
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else
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begin
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if not(tcallparanode(tcallparanode(left).right).left.location.loc in [LOC_REGISTER,LOC_CREGISTER,LOC_REFERENCE,LOC_CREFERENCE]) or (addvalue>1) or
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not(equal_defs(left.resultdef,tcallparanode(tcallparanode(left).right).left.resultdef)) then
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begin
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hlcg.location_force_reg(current_asmdata.CurrAsmList,tcallparanode(tcallparanode(left).right).left.location,tcallparanode(tcallparanode(left).right).left.resultdef,second_incdec_tempregdef,addvalue<=1);
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hregister:=tcallparanode(tcallparanode(left).right).left.location.register;
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{$if not defined(cpu64bitalu) and not defined(cpuhighleveltarget)}
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hregisterhi:=tcallparanode(tcallparanode(left).right).left.location.register64.reghi;
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{$endif not defined(cpu64bitalu) and not defined(cpuhighleveltarget)}
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{ insert multiply with addvalue if its >1 }
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if addvalue>1 then
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hlcg.a_op_const_reg(current_asmdata.CurrAsmList,OP_IMUL,left.resultdef,addvalue.svalue,hregister);
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end
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else if tcallparanode(tcallparanode(left).right).left.location.loc in [LOC_REGISTER,LOC_CREGISTER] then
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begin
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hregister:=tcallparanode(tcallparanode(left).right).left.location.register;
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{$if not defined(cpu64bitalu) and not defined(cpuhighleveltarget)}
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hregisterhi:=tcallparanode(tcallparanode(left).right).left.location.register64.reghi;
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{$endif not defined(cpu64bitalu) and not defined(cpuhighleveltarget)}
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end;
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addconstant:=false;
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end;
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end;
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{ write the add instruction }
|
|
if addconstant then
|
|
begin
|
|
{$if not defined(cpu64bitalu) and not defined(cpuhighleveltarget)}
|
|
if def_cgsize(left.resultdef) in [OS_64,OS_S64] then
|
|
{ use addvalue.svalue here to avoid an internal error if addvalue is unsigned and overflows int64, see #35298,
|
|
we are only interested in the bit pattern here }
|
|
cg64.a_op64_const_loc(current_asmdata.CurrAsmList,addsubop[inlinenumber],def_cgsize(left.resultdef),addvalue.svalue,tcallparanode(left).left.location)
|
|
else
|
|
{$endif not cpu64bitalu and not cpuhighleveltarget}
|
|
hlcg.a_op_const_loc(current_asmdata.CurrAsmList,addsubop[inlinenumber],left.resultdef,
|
|
{$ifdef cpu64bitalu}
|
|
aint(addvalue.svalue),
|
|
{$else cpu64bitalu}
|
|
longint(addvalue.svalue), // can't use aint, because it breaks 16-bit and 8-bit CPUs
|
|
{$endif cpu64bitalu}
|
|
tcallparanode(left).left.location);
|
|
end
|
|
else
|
|
begin
|
|
{$if not defined(cpu64bitalu) and not defined(cpuhighleveltarget)}
|
|
if def_cgsize(left.resultdef) in [OS_64,OS_S64] then
|
|
case tcallparanode(tcallparanode(left).right).left.location.loc of
|
|
LOC_REFERENCE,LOC_CREFERENCE:
|
|
cg64.a_op64_ref_loc(current_asmdata.CurrAsmList,addsubop[inlinenumber],def_cgsize(left.resultdef),
|
|
tcallparanode(tcallparanode(left).right).left.location.reference,tcallparanode(left).left.location);
|
|
LOC_REGISTER,LOC_CREGISTER:
|
|
cg64.a_op64_reg_loc(current_asmdata.CurrAsmList,addsubop[inlinenumber],def_cgsize(left.resultdef),
|
|
joinreg64(hregister,hregisterhi),tcallparanode(left).left.location);
|
|
else
|
|
Internalerror(2020042801);
|
|
end
|
|
else
|
|
{$endif not cpu64bitalu and not cpuhighleveltarget}
|
|
case tcallparanode(tcallparanode(left).right).left.location.loc of
|
|
LOC_REFERENCE,LOC_CREFERENCE:
|
|
hlcg.a_op_ref_loc(current_asmdata.CurrAsmList,addsubop[inlinenumber],left.resultdef,
|
|
tcallparanode(tcallparanode(left).right).left.location.reference,tcallparanode(left).left.location);
|
|
LOC_REGISTER,LOC_CREGISTER:
|
|
hlcg.a_op_reg_loc(current_asmdata.CurrAsmList,addsubop[inlinenumber],left.resultdef,
|
|
hregister,tcallparanode(left).left.location);
|
|
else
|
|
Internalerror(2020042802);
|
|
end;
|
|
end;
|
|
{ no overflow checking for pointers (see ninl), and range checking }
|
|
{ is not applicable for them }
|
|
if (tcallparanode(left).left.resultdef.typ <> pointerdef) then
|
|
begin
|
|
{ things which can overflow must NOT pass via here, but have to be }
|
|
{ handled via a regular add node (conversion in tinlinenode.pass_1) }
|
|
{ Or someone has to rewrite the above to use a_op_const_reg_reg_ov }
|
|
{ and friends in case of overflow checking, and ask everyone to }
|
|
{ implement these methods since they don't exist for all cpus (JM) }
|
|
{ Similarly, range checking also has to be handled separately, }
|
|
{ see mantis #14841 (JM) }
|
|
if ([cs_check_overflow,cs_check_range] * current_settings.localswitches <> []) then
|
|
internalerror(2006111010);
|
|
// cg.g_overflowcheck(current_asmdata.CurrAsmList,tcallparanode(left).left.location,tcallparanode(left).resultdef);
|
|
// cg.g_rangecheck(current_asmdata.CurrAsmList,tcallparanode(left).left.location,tcallparanode(left).left.resultdef,
|
|
// tcallparanode(left).left.resultdef);
|
|
end;
|
|
end;
|
|
|
|
|
|
{*****************************************************************************
|
|
AND/OR/XOR/SHIFT/ROTATE ASSIGN GENERIC HANDLING
|
|
*****************************************************************************}
|
|
procedure tcginlinenode.second_AndOrXorShiftRot_assign;
|
|
const
|
|
andorxorop:array[in_and_assign_x_y..in_ror_assign_x_y] of TOpCG=
|
|
(OP_AND,OP_OR,OP_XOR,OP_SAR,OP_SHL,OP_SHR,OP_ROL,OP_ROR);
|
|
var
|
|
maskvalue : TConstExprInt;
|
|
maskconstant : boolean;
|
|
{$if not defined(cpu64bitalu) and not defined(cpuhighleveltarget)}
|
|
hregisterhi,
|
|
{$endif not cpu64bitalu and not cpuhighleveltarget}
|
|
hregister : tregister;
|
|
begin
|
|
{ set defaults }
|
|
maskconstant:=true;
|
|
hregister:=NR_NO;
|
|
maskvalue:=0;
|
|
{$if not defined(cpu64bitalu) and not defined(cpuhighleveltarget)}
|
|
hregisterhi:=NR_NO;
|
|
{$endif not cpu64bitalu and not cpuhighleveltarget}
|
|
|
|
{ first secondpass first argument, because if the second arg }
|
|
{ is used in that expression then SSL may move it to another }
|
|
{ register }
|
|
secondpass(tcallparanode(left).left);
|
|
{ load second parameter, must be a reference }
|
|
secondpass(tcallparanode(tcallparanode(left).right).left);
|
|
|
|
{ when constant, just get the maskvalue }
|
|
if is_constintnode(tcallparanode(left).left) then
|
|
maskvalue:=get_ordinal_value(tcallparanode(left).left)
|
|
else
|
|
begin
|
|
{ for shift/rotate the shift count can be of different size than the shifted variable }
|
|
if inlinenumber in [in_sar_assign_x_y,in_shl_assign_x_y,in_shr_assign_x_y,in_rol_assign_x_y,in_ror_assign_x_y] then
|
|
hlcg.location_force_reg(current_asmdata.CurrAsmList,tcallparanode(left).left.location,tcallparanode(left).left.resultdef,tcallparanode(left).left.resultdef,true)
|
|
else
|
|
hlcg.location_force_reg(current_asmdata.CurrAsmList,tcallparanode(left).left.location,tcallparanode(left).left.resultdef,tcallparanode(left).right.resultdef,true);
|
|
hregister:=tcallparanode(left).left.location.register;
|
|
{$if not defined(cpu64bitalu) and not defined(cpuhighleveltarget)}
|
|
hregisterhi:=tcallparanode(left).left.location.register64.reghi;
|
|
{$endif not cpu64bitalu and not cpuhighleveltarget}
|
|
maskconstant:=false;
|
|
end;
|
|
{ write the and/or/xor/sar/shl/shr/rol/ror instruction }
|
|
if maskconstant then
|
|
begin
|
|
if inlinenumber in [in_sar_assign_x_y,in_shl_assign_x_y,in_shr_assign_x_y,in_rol_assign_x_y,in_ror_assign_x_y] then
|
|
if def_cgsize(tcallparanode(left).right.resultdef) in [OS_64,OS_S64] then
|
|
maskvalue:=maskvalue and 63
|
|
else
|
|
maskvalue:=maskvalue and 31;
|
|
{$if not defined(cpu64bitalu) and not defined(cpuhighleveltarget)}
|
|
if (def_cgsize(tcallparanode(left).right.resultdef) in [OS_64,OS_S64]) and
|
|
(tcallparanode(tcallparanode(left).right).left.location.loc in [LOC_REFERENCE,LOC_CREFERENCE,LOC_REGISTER,LOC_CREGISTER]) then
|
|
cg64.a_op64_const_loc(current_asmdata.CurrAsmList,andorxorop[inlinenumber],def_cgsize(tcallparanode(left).right.resultdef),maskvalue.svalue,tcallparanode(tcallparanode(left).right).left.location)
|
|
else
|
|
{$endif not cpu64bitalu and not cpuhighleveltarget}
|
|
hlcg.a_op_const_loc(current_asmdata.CurrAsmList,andorxorop[inlinenumber],tcallparanode(left).right.resultdef,
|
|
{$ifdef cpu64bitalu}
|
|
aint(maskvalue.svalue),
|
|
{$else cpu64bitalu}
|
|
longint(maskvalue.svalue), // can't use aint, because it breaks 16-bit and 8-bit CPUs
|
|
{$endif cpu64bitalu}
|
|
tcallparanode(tcallparanode(left).right).left.location);
|
|
end
|
|
else
|
|
begin
|
|
{$if not defined(cpu64bitalu) and not defined(cpuhighleveltarget)}
|
|
if (def_cgsize(tcallparanode(left).right.resultdef) in [OS_64,OS_S64]) and
|
|
(tcallparanode(tcallparanode(left).right).left.location.loc in [LOC_REFERENCE,LOC_CREFERENCE,LOC_REGISTER,LOC_CREGISTER]) then
|
|
cg64.a_op64_reg_loc(current_asmdata.CurrAsmList,andorxorop[inlinenumber],def_cgsize(tcallparanode(left).right.resultdef),
|
|
joinreg64(hregister,hregisterhi),tcallparanode(tcallparanode(left).right).left.location)
|
|
else
|
|
{$endif not cpu64bitalu and not cpuhighleveltarget}
|
|
hlcg.a_op_reg_loc(current_asmdata.CurrAsmList,andorxorop[inlinenumber],tcallparanode(left).right.resultdef,
|
|
hregister,tcallparanode(tcallparanode(left).right).left.location);
|
|
end;
|
|
end;
|
|
|
|
|
|
{*****************************************************************************
|
|
NEG/NOT ASSIGN GENERIC HANDLING
|
|
*****************************************************************************}
|
|
procedure tcginlinenode.second_NegNot_assign;
|
|
const
|
|
negnotop:array[in_neg_assign_x..in_not_assign_x] of TOpCG=(OP_NEG,OP_NOT);
|
|
begin
|
|
{ load parameter, must be a reference }
|
|
secondpass(left);
|
|
|
|
location_reset(location,LOC_VOID,OS_NO);
|
|
|
|
{$ifndef cpu64bitalu}
|
|
if (def_cgsize(left.resultdef) in [OS_64,OS_S64]) and (left.location.loc in [LOC_REGISTER,LOC_CREGISTER,LOC_REFERENCE,LOC_CREFERENCE]) then
|
|
cg64.a_op64_loc(current_asmdata.CurrAsmList,negnotop[inlinenumber],def_cgsize(left.resultdef),left.location)
|
|
else
|
|
{$endif not cpu64bitalu}
|
|
hlcg.a_op_loc(current_asmdata.CurrAsmList,negnotop[inlinenumber],left.resultdef,left.location);
|
|
end;
|
|
|
|
|
|
{*****************************************************************************
|
|
TYPEINFO GENERIC HANDLING
|
|
*****************************************************************************}
|
|
procedure tcginlinenode.second_typeinfo;
|
|
begin
|
|
internalerror(2013060301);
|
|
end;
|
|
|
|
|
|
{*****************************************************************************
|
|
INCLUDE/EXCLUDE GENERIC HANDLING
|
|
*****************************************************************************}
|
|
|
|
procedure tcginlinenode.second_IncludeExclude;
|
|
var
|
|
setpara, elepara: tnode;
|
|
begin
|
|
{ the set }
|
|
secondpass(tcallparanode(left).left);
|
|
{ the element to set }
|
|
secondpass(tcallparanode(tcallparanode(left).right).left);
|
|
|
|
setpara:=tcallparanode(left).left;
|
|
elepara:=tcallparanode(tcallparanode(left).right).left;
|
|
|
|
if elepara.location.loc=LOC_CONSTANT then
|
|
begin
|
|
hlcg.a_bit_set_const_loc(current_asmdata.CurrAsmList,(inlinenumber=in_include_x_y),
|
|
setpara.resultdef,elepara.location.value-tsetdef(setpara.resultdef).setbase,setpara.location);
|
|
end
|
|
else
|
|
begin
|
|
hlcg.location_force_reg(current_asmdata.CurrAsmList,elepara.location,elepara.resultdef,u32inttype,true);
|
|
register_maybe_adjust_setbase(current_asmdata.CurrAsmList,u32inttype,elepara.location,tsetdef(setpara.resultdef).setbase);
|
|
hlcg.a_bit_set_reg_loc(current_asmdata.CurrAsmList,(inlinenumber=in_include_x_y),
|
|
u32inttype,setpara.resultdef,elepara.location.register,setpara.location);
|
|
end;
|
|
end;
|
|
|
|
|
|
{*****************************************************************************
|
|
FLOAT GENERIC HANDLING
|
|
*****************************************************************************}
|
|
|
|
{
|
|
These routines all call internal RTL routines, so if they are
|
|
called here, they give an internal error
|
|
}
|
|
procedure tcginlinenode.second_pi;
|
|
begin
|
|
internalerror(2002071801);
|
|
end;
|
|
|
|
procedure tcginlinenode.second_arctan_real;
|
|
begin
|
|
internalerror(2002071802);
|
|
end;
|
|
|
|
procedure tcginlinenode.second_abs_real;
|
|
begin
|
|
internalerror(2002071803);
|
|
end;
|
|
|
|
procedure tcginlinenode.second_round_real;
|
|
begin
|
|
internalerror(2002071804);
|
|
end;
|
|
|
|
procedure tcginlinenode.second_trunc_real;
|
|
begin
|
|
internalerror(2002071805);
|
|
end;
|
|
|
|
procedure tcginlinenode.second_int_real;
|
|
begin
|
|
internalerror(2016112702);
|
|
end;
|
|
|
|
procedure tcginlinenode.second_sqr_real;
|
|
begin
|
|
internalerror(2002071806);
|
|
end;
|
|
|
|
procedure tcginlinenode.second_sqrt_real;
|
|
begin
|
|
internalerror(2002071807);
|
|
end;
|
|
|
|
procedure tcginlinenode.second_ln_real;
|
|
begin
|
|
internalerror(2002071808);
|
|
end;
|
|
|
|
procedure tcginlinenode.second_cos_real;
|
|
begin
|
|
internalerror(2002071809);
|
|
end;
|
|
|
|
procedure tcginlinenode.second_sin_real;
|
|
begin
|
|
internalerror(2002071810);
|
|
end;
|
|
|
|
|
|
procedure tcginlinenode.second_prefetch;
|
|
begin
|
|
end;
|
|
|
|
procedure tcginlinenode.second_frac_real;
|
|
begin
|
|
internalerror(2017052104);
|
|
end;
|
|
|
|
procedure tcginlinenode.second_abs_long;
|
|
var
|
|
tempreg1, tempreg2: tregister;
|
|
begin
|
|
secondpass(left);
|
|
hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,true);
|
|
location:=left.location;
|
|
location.register:=hlcg.getintregister(current_asmdata.CurrAsmList,left.resultdef);
|
|
|
|
tempreg1:=hlcg.getintregister(current_asmdata.CurrAsmList,left.resultdef);
|
|
tempreg2:=hlcg.getintregister(current_asmdata.CurrAsmList,left.resultdef);
|
|
|
|
hlcg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SAR,left.resultdef,left.resultdef.size*8-1,left.location.register,tempreg1);
|
|
hlcg.a_op_reg_reg_reg(current_asmdata.CurrAsmList,OP_XOR,left.resultdef,left.location.register,tempreg1,tempreg2);
|
|
hlcg.a_op_reg_reg_reg(current_asmdata.CurrAsmlist,OP_SUB,left.resultdef,tempreg1,tempreg2,location.register);
|
|
end;
|
|
|
|
|
|
{*****************************************************************************
|
|
ASSIGNED GENERIC HANDLING
|
|
*****************************************************************************}
|
|
|
|
procedure tcginlinenode.second_assigned;
|
|
begin
|
|
internalerror(2013091602);
|
|
end;
|
|
|
|
procedure Tcginlinenode.second_get_frame;
|
|
|
|
begin
|
|
{$if defined(x86) or defined(arm)}
|
|
if current_procinfo.framepointer=NR_STACK_POINTER_REG then
|
|
begin
|
|
location_reset(location,LOC_CONSTANT,OS_ADDR);
|
|
location.value:=0;
|
|
end
|
|
else
|
|
{$endif defined(x86) or defined(arm)}
|
|
begin
|
|
location_reset(location,LOC_CREGISTER,OS_ADDR);
|
|
location.register:=current_procinfo.framepointer;
|
|
end;
|
|
end;
|
|
|
|
procedure Tcginlinenode.second_get_caller_frame;
|
|
|
|
var
|
|
frame_reg:Tregister;
|
|
use_frame_pointer:boolean;
|
|
|
|
begin
|
|
frame_reg:=NR_NO;
|
|
|
|
if left<>nil then
|
|
begin
|
|
secondpass(left);
|
|
if left.location.loc=LOC_CONSTANT then
|
|
use_frame_pointer:=true
|
|
else
|
|
begin
|
|
hlcg.location_force_reg(current_asmdata.currasmlist,left.location,left.resultdef,voidpointertype,false);
|
|
frame_reg:=left.location.register;
|
|
use_frame_pointer:=false;
|
|
end
|
|
end
|
|
else
|
|
begin
|
|
use_frame_pointer:=current_procinfo.framepointer=NR_STACK_POINTER_REG;
|
|
frame_reg:=current_procinfo.framepointer;
|
|
end;
|
|
|
|
if use_frame_pointer then
|
|
begin
|
|
location_reset(location,LOC_CREGISTER,OS_ADDR);
|
|
location.register:=NR_FRAME_POINTER_REG;
|
|
end
|
|
else
|
|
begin
|
|
location_reset_ref(location,LOC_REFERENCE,OS_ADDR,sizeof(pint),[]);
|
|
location.reference.base:=frame_reg;
|
|
end;
|
|
end;
|
|
|
|
procedure Tcginlinenode.second_get_caller_addr;
|
|
var
|
|
frame_ref:Treference;
|
|
begin
|
|
if current_procinfo.framepointer=NR_STACK_POINTER_REG then
|
|
begin
|
|
location_reset(location,LOC_REGISTER,OS_ADDR);
|
|
location.register:=cg.getaddressregister(current_asmdata.currasmlist);
|
|
reference_reset_base(frame_ref,NR_STACK_POINTER_REG,{current_procinfo.calc_stackframe_size}tg.lasttemp,ctempposinvalid,sizeof(pint),[]);
|
|
cg.a_load_ref_reg(current_asmdata.currasmlist,OS_ADDR,OS_ADDR,frame_ref,location.register);
|
|
end
|
|
else
|
|
begin
|
|
location_reset(location,LOC_REGISTER,OS_ADDR);
|
|
location.register:=cg.getaddressregister(current_asmdata.currasmlist);
|
|
reference_reset_base(frame_ref,current_procinfo.framepointer,sizeof(pint),ctempposinvalid,sizeof(pint),[]);
|
|
cg.a_load_ref_reg(current_asmdata.currasmlist,OS_ADDR,OS_ADDR,frame_ref,location.register);
|
|
end;
|
|
end;
|
|
|
|
|
|
procedure tcginlinenode.second_rox_sar;
|
|
var
|
|
op : topcg;
|
|
op1,op2 : tnode;
|
|
begin
|
|
{ one or two parameters? }
|
|
if (left.nodetype=callparan) and
|
|
assigned(tcallparanode(left).right) then
|
|
begin
|
|
op1:=tcallparanode(tcallparanode(left).right).left;
|
|
op2:=tcallparanode(left).left;
|
|
secondpass(op2);
|
|
end
|
|
else
|
|
begin
|
|
op1:=left;
|
|
op2:=nil;
|
|
end;
|
|
|
|
secondpass(op1);
|
|
case inlinenumber of
|
|
in_ror_x,
|
|
in_ror_x_y:
|
|
op:=OP_ROR;
|
|
in_rol_x,
|
|
in_rol_x_y:
|
|
op:=OP_ROL;
|
|
in_sar_x,
|
|
in_sar_x_y:
|
|
op:=OP_SAR;
|
|
else
|
|
internalerror(2013120110);
|
|
end;
|
|
|
|
if not(op1.location.loc in [LOC_REGISTER,LOC_CREGISTER]) then
|
|
hlcg.location_force_reg(current_asmdata.CurrAsmList,op1.location,op1.resultdef,resultdef,true);
|
|
|
|
location_reset(location,LOC_REGISTER,def_cgsize(resultdef));
|
|
{$if not defined(cpu64bitalu) and not defined(cpuhighleveltarget)}
|
|
if def_cgsize(resultdef) in [OS_64,OS_S64] then
|
|
begin
|
|
location.register64.reglo:=cg.getintregister(current_asmdata.CurrAsmList,OS_32);
|
|
location.register64.reghi:=cg.getintregister(current_asmdata.CurrAsmList,OS_32);
|
|
end
|
|
else
|
|
{$endif not cpu64bitalu and not cpuhighleveltarget}
|
|
location.register:=hlcg.getintregister(current_asmdata.CurrAsmList,resultdef);
|
|
|
|
if assigned(op2) then
|
|
begin
|
|
{ rotating by a constant directly coded: }
|
|
if op2.nodetype=ordconstn then
|
|
{$if not defined(cpu64bitalu) and not defined(cpuhighleveltarget)}
|
|
if def_cgsize(resultdef) in [OS_64,OS_S64] then
|
|
cg64.a_op64_const_reg_reg(current_asmdata.CurrAsmList,op,def_cgsize(resultdef),
|
|
tordconstnode(op2).value.uvalue and (resultdef.size*8-1),
|
|
op1.location.register64, location.register64)
|
|
else
|
|
{$endif not cpu64bitalu and not cpuhighleveltarget}
|
|
hlcg.a_op_const_reg_reg(current_asmdata.CurrAsmList,op,resultdef,
|
|
tordconstnode(op2).value.uvalue and (resultdef.size*8-1),
|
|
op1.location.register, location.register)
|
|
else
|
|
begin
|
|
{$if not defined(cpu64bitalu) and not defined(cpuhighleveltarget)}
|
|
if def_cgsize(resultdef) in [OS_64,OS_S64] then
|
|
begin
|
|
if not(op2.location.loc in [LOC_REGISTER,LOC_CREGISTER]) or
|
|
not(equal_defs(op2.resultdef,alusinttype)) then
|
|
hlcg.location_force_reg(current_asmdata.CurrAsmList,op2.location,
|
|
op2.resultdef,alusinttype,true);
|
|
cg64.a_op64_reg_reg_reg(current_asmdata.CurrAsmList,op,def_cgsize(resultdef),
|
|
joinreg64(op2.location.register,NR_NO),op1.location.register64,
|
|
location.register64);
|
|
end
|
|
else
|
|
{$endif not cpu64bitalu and not cpuhighleveltarget}
|
|
begin
|
|
if not(op2.location.loc in [LOC_REGISTER,LOC_CREGISTER]) or
|
|
not(equal_defs(op2.resultdef,resultdef)) then
|
|
hlcg.location_force_reg(current_asmdata.CurrAsmList,op2.location,
|
|
op2.resultdef,resultdef,true);
|
|
hlcg.a_op_reg_reg_reg(current_asmdata.CurrAsmList,op,resultdef,
|
|
op2.location.register,op1.location.register,
|
|
location.register);
|
|
end;
|
|
end;
|
|
end
|
|
else
|
|
{$if not defined(cpu64bitalu) and not defined(cpuhighleveltarget)}
|
|
if def_cgsize(resultdef) in [OS_64,OS_S64] then
|
|
cg64.a_op64_const_reg_reg(current_asmdata.CurrAsmList,op,def_cgsize(resultdef),1,
|
|
op1.location.register64,location.register64)
|
|
else
|
|
{$endif not cpu64bitalu and not cpuhighleveltarget}
|
|
hlcg.a_op_const_reg_reg(current_asmdata.CurrAsmList,op,resultdef,1,
|
|
op1.location.register,location.register);
|
|
end;
|
|
|
|
|
|
procedure tcginlinenode.second_BsfBsr;
|
|
var
|
|
reverse: boolean;
|
|
opsize: tcgsize;
|
|
begin
|
|
reverse:=(inlinenumber = in_bsr_x);
|
|
secondpass(left);
|
|
|
|
opsize:=tcgsize2unsigned[left.location.size];
|
|
if not(left.location.loc in [LOC_REGISTER,LOC_CREGISTER]) then
|
|
hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,cgsize_orddef(opsize),true);
|
|
|
|
location_reset(location,LOC_REGISTER,def_cgsize(resultdef));
|
|
location.register:=cg.getintregister(current_asmdata.CurrAsmList,location.size);
|
|
cg.a_bit_scan_reg_reg(current_asmdata.CurrAsmList,reverse,opsize,location.size,left.location.register,location.register);
|
|
end;
|
|
|
|
|
|
procedure tcginlinenode.second_new;
|
|
begin
|
|
internalerror(2011012202);
|
|
end;
|
|
|
|
|
|
procedure tcginlinenode.second_popcnt;
|
|
begin
|
|
internalerror(2012082602);
|
|
end;
|
|
|
|
|
|
procedure tcginlinenode.second_fma;
|
|
begin
|
|
internalerror(2014032701);
|
|
end;
|
|
|
|
|
|
procedure tcginlinenode.second_minmax;
|
|
begin
|
|
internalerror(2020120501);
|
|
end;
|
|
|
|
begin
|
|
cinlinenode:=tcginlinenode;
|
|
end.
|