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https://gitlab.com/freepascal.org/fpc/source.git
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1753 lines
61 KiB
ObjectPascal
1753 lines
61 KiB
ObjectPascal
{
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Copyright (c) 2008 by Florian Klaempfl
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Member of the Free Pascal development team
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This unit implements the code generator for the AVR
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit cgcpu;
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{$i fpcdefs.inc}
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interface
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uses
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globtype,symtype,symdef,
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cgbase,cgutils,cgobj,
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aasmbase,aasmcpu,aasmtai,aasmdata,
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parabase,
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cpubase,cpuinfo,node,cg64f32,rgcpu;
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type
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{ tcgavr }
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tcgavr = class(tcg)
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{ true, if the next arithmetic operation should modify the flags }
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cgsetflags : boolean;
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procedure init_register_allocators;override;
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procedure done_register_allocators;override;
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function getintregister(list:TAsmList;size:Tcgsize):Tregister;override;
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function getaddressregister(list:TAsmList):TRegister;override;
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procedure a_load_const_cgpara(list : TAsmList;size : tcgsize;a : tcgint;const paraloc : TCGPara);override;
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procedure a_load_ref_cgpara(list : TAsmList;size : tcgsize;const r : treference;const paraloc : TCGPara);override;
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procedure a_loadaddr_ref_cgpara(list : TAsmList;const r : treference;const paraloc : TCGPara);override;
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procedure a_call_name(list : TAsmList;const s : string; weak: boolean);override;
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procedure a_call_reg(list : TAsmList;reg: tregister);override;
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procedure a_call_ref(list : TAsmList;ref: treference);override;
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procedure a_op_const_reg(list : TAsmList; Op: TOpCG; size: TCGSize; a: tcgint; reg: TRegister); override;
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procedure a_op_reg_reg(list : TAsmList; Op: TOpCG; size: TCGSize; src, dst: TRegister); override;
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{ move instructions }
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procedure a_load_const_reg(list : TAsmList; size: tcgsize; a : tcgint;reg : tregister);override;
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procedure a_load_reg_ref(list : TAsmList; fromsize, tosize: tcgsize; reg : tregister;const ref : treference);override;
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procedure a_load_ref_reg(list : TAsmList; fromsize, tosize : tcgsize;const Ref : treference;reg : tregister);override;
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procedure a_load_reg_reg(list : TAsmList; fromsize, tosize : tcgsize;reg1,reg2 : tregister);override;
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{ fpu move instructions }
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procedure a_loadfpu_reg_reg(list: TAsmList; fromsize, tosize: tcgsize; reg1, reg2: tregister); override;
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procedure a_loadfpu_ref_reg(list: TAsmList; fromsize, tosize: tcgsize; const ref: treference; reg: tregister); override;
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procedure a_loadfpu_reg_ref(list: TAsmList; fromsize, tosize: tcgsize; reg: tregister; const ref: treference); override;
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{ comparison operations }
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procedure a_cmp_const_reg_label(list : TAsmList;size : tcgsize;cmp_op : topcmp;a : tcgint;reg : tregister;
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l : tasmlabel);override;
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procedure a_cmp_reg_reg_label(list : TAsmList;size : tcgsize;cmp_op : topcmp;reg1,reg2 : tregister;l : tasmlabel); override;
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procedure a_jmp_name(list : TAsmList;const s : string); override;
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procedure a_jmp_always(list : TAsmList;l: tasmlabel); override;
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procedure a_jmp_flags(list : TAsmList;const f : TResFlags;l: tasmlabel); override;
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procedure g_flags2reg(list: TAsmList; size: TCgSize; const f: TResFlags; reg: TRegister); override;
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procedure g_proc_entry(list : TAsmList;localsize : longint;nostackframe:boolean);override;
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procedure g_proc_exit(list : TAsmList;parasize : longint;nostackframe:boolean); override;
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procedure a_loadaddr_ref_reg(list : TAsmList;const ref : treference;r : tregister);override;
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procedure g_concatcopy(list : TAsmList;const source,dest : treference;len : tcgint);override;
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procedure g_concatcopy_move(list : TAsmList;const source,dest : treference;len : tcgint);
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procedure g_overflowcheck(list: TAsmList; const l: tlocation; def: tdef); override;
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procedure g_save_registers(list : TAsmList);override;
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procedure g_restore_registers(list : TAsmList);override;
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procedure a_jmp_cond(list : TAsmList;cond : TOpCmp;l: tasmlabel);
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procedure fixref(list : TAsmList;var ref : treference);
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function normalize_ref(list : TAsmList;ref : treference;
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tmpreg : tregister) : treference;
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procedure g_intf_wrapper(list: TAsmList; procdef: tprocdef; const labelname: string; ioffset: longint);override;
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procedure g_stackpointer_alloc(list : TAsmList;size : longint);override;
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procedure emit_mov(list: TAsmList;reg2: tregister; reg1: tregister);
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procedure a_adjust_sp(list: TAsmList; value: longint);
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function GetLoad(const ref : treference) : tasmop;
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function GetStore(const ref: treference): tasmop;
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procedure a_bit_scan_reg_reg(list: TAsmList; reverse: boolean; size: TCGSize; src, dst: TRegister); override;
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end;
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tcg64favr = class(tcg64f32)
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procedure a_op64_reg_reg(list : TAsmList;op:TOpCG;size : tcgsize;regsrc,regdst : tregister64);override;
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procedure a_op64_const_reg(list : TAsmList;op:TOpCG;size : tcgsize;value : int64;reg : tregister64);override;
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end;
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procedure create_codegen;
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const
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TOpCG2AsmOp: Array[topcg] of TAsmOp = (A_NONE,A_MOV,A_ADD,A_AND,A_NONE,
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A_NONE,A_MUL,A_MULS,A_NEG,A_COM,A_OR,
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A_ASR,A_LSL,A_LSR,A_SUB,A_EOR,A_ROL,A_ROR);
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implementation
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uses
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globals,verbose,systems,cutils,
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fmodule,
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symconst,symsym,
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tgobj,rgobj,
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procinfo,cpupi,
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paramgr;
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procedure tcgavr.init_register_allocators;
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begin
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inherited init_register_allocators;
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rg[R_INTREGISTER]:=trgintcpu.create(R_INTREGISTER,R_SUBWHOLE,
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[RS_R8,RS_R9,
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RS_R10,RS_R11,RS_R12,RS_R13,RS_R14,RS_R15,RS_R16,RS_R17,RS_R18,RS_R19,
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RS_R20,RS_R21,RS_R22,RS_R23,RS_R24,RS_R25,
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RS_R2,RS_R3,RS_R4,RS_R5,RS_R6,RS_R7],first_int_imreg,[]);
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{ rg[R_ADDRESSREGISTER]:=trgintcpu.create(R_ADDRESSREGISTER,R_SUBWHOLE,
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[RS_R26,RS_R30],first_int_imreg,[]); }
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end;
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procedure tcgavr.done_register_allocators;
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begin
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rg[R_INTREGISTER].free;
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// rg[R_ADDRESSREGISTER].free;
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inherited done_register_allocators;
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end;
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function tcgavr.getintregister(list: TAsmList; size: Tcgsize): Tregister;
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var
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tmp1,tmp2,tmp3 : TRegister;
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begin
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case size of
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OS_8,OS_S8:
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Result:=inherited getintregister(list, size);
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OS_16,OS_S16:
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begin
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Result:=inherited getintregister(list, OS_8);
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{ ensure that the high register can be retrieved by
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GetNextReg
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}
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if inherited getintregister(list, OS_8)<>GetNextReg(Result) then
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internalerror(2011021331);
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end;
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OS_32,OS_S32:
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begin
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Result:=inherited getintregister(list, OS_8);
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tmp1:=inherited getintregister(list, OS_8);
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{ ensure that the high register can be retrieved by
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GetNextReg
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}
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if tmp1<>GetNextReg(Result) then
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internalerror(2011021332);
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tmp2:=inherited getintregister(list, OS_8);
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{ ensure that the upper register can be retrieved by
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GetNextReg
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}
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if tmp2<>GetNextReg(tmp1) then
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internalerror(2011021333);
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tmp3:=inherited getintregister(list, OS_8);
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{ ensure that the upper register can be retrieved by
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GetNextReg
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}
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if tmp3<>GetNextReg(tmp2) then
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internalerror(2011021334);
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end;
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else
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internalerror(2011021330);
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end;
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end;
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function tcgavr.getaddressregister(list: TAsmList): TRegister;
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begin
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Result:=getintregister(list,OS_ADDR);
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end;
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procedure tcgavr.a_load_const_cgpara(list : TAsmList;size : tcgsize;a : tcgint;const paraloc : TCGPara);
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var
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ref: treference;
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begin
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paraloc.check_simple_location;
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paramanager.allocparaloc(list,paraloc.location);
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case paraloc.location^.loc of
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LOC_REGISTER,LOC_CREGISTER:
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a_load_const_reg(list,size,a,paraloc.location^.register);
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LOC_REFERENCE:
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begin
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reference_reset(ref,paraloc.alignment);
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ref.base:=paraloc.location^.reference.index;
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ref.offset:=paraloc.location^.reference.offset;
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a_load_const_ref(list,size,a,ref);
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end;
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else
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internalerror(2002081101);
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end;
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end;
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procedure tcgavr.a_load_ref_cgpara(list : TAsmList;size : tcgsize;const r : treference;const paraloc : TCGPara);
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var
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tmpref, ref: treference;
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location: pcgparalocation;
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sizeleft: tcgint;
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begin
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location := paraloc.location;
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tmpref := r;
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sizeleft := paraloc.intsize;
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while assigned(location) do
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begin
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paramanager.allocparaloc(list,location);
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case location^.loc of
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LOC_REGISTER,LOC_CREGISTER:
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a_load_ref_reg(list,location^.size,location^.size,tmpref,location^.register);
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LOC_REFERENCE:
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begin
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reference_reset_base(ref,location^.reference.index,location^.reference.offset,paraloc.alignment);
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{ doubles in softemu mode have a strange order of registers and references }
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if location^.size=OS_32 then
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g_concatcopy(list,tmpref,ref,4)
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else
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begin
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g_concatcopy(list,tmpref,ref,sizeleft);
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if assigned(location^.next) then
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internalerror(2005010710);
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end;
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end;
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LOC_VOID:
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begin
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// nothing to do
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end;
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else
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internalerror(2002081103);
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end;
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inc(tmpref.offset,tcgsize2size[location^.size]);
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dec(sizeleft,tcgsize2size[location^.size]);
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location := location^.next;
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end;
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end;
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procedure tcgavr.a_loadaddr_ref_cgpara(list : TAsmList;const r : treference;const paraloc : TCGPara);
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var
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ref: treference;
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tmpreg: tregister;
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begin
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paraloc.check_simple_location;
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paramanager.allocparaloc(list,paraloc.location);
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case paraloc.location^.loc of
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LOC_REGISTER,LOC_CREGISTER:
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a_loadaddr_ref_reg(list,r,paraloc.location^.register);
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LOC_REFERENCE:
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begin
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reference_reset(ref,paraloc.alignment);
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ref.base := paraloc.location^.reference.index;
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ref.offset := paraloc.location^.reference.offset;
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tmpreg := getintregister(list,OS_ADDR);
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a_loadaddr_ref_reg(list,r,tmpreg);
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a_load_reg_ref(list,OS_ADDR,OS_ADDR,tmpreg,ref);
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end;
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else
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internalerror(2002080701);
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end;
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end;
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procedure tcgavr.a_call_name(list : TAsmList;const s : string; weak: boolean);
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begin
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list.concat(taicpu.op_sym(A_RCALL,current_asmdata.RefAsmSymbol(s)));
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{
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the compiler does not properly set this flag anymore in pass 1, and
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for now we only need it after pass 2 (I hope) (JM)
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if not(pi_do_call in current_procinfo.flags) then
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internalerror(2003060703);
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}
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include(current_procinfo.flags,pi_do_call);
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end;
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procedure tcgavr.a_call_reg(list : TAsmList;reg: tregister);
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begin
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a_reg_alloc(list,NR_ZLO);
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a_reg_alloc(list,NR_ZHI);
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list.concat(taicpu.op_reg_reg(A_MOV,NR_ZLO,reg));
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list.concat(taicpu.op_reg_reg(A_MOV,NR_ZHI,GetHigh(reg)));
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list.concat(taicpu.op_none(A_ICALL));
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a_reg_dealloc(list,NR_ZLO);
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a_reg_dealloc(list,NR_ZHI);
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include(current_procinfo.flags,pi_do_call);
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end;
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procedure tcgavr.a_call_ref(list : TAsmList;ref: treference);
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begin
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a_reg_alloc(list,NR_ZLO);
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a_reg_alloc(list,NR_ZHI);
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a_load_ref_reg(list,OS_ADDR,OS_ADDR,ref,NR_ZLO);
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list.concat(taicpu.op_none(A_ICALL));
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a_reg_dealloc(list,NR_ZLO);
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a_reg_dealloc(list,NR_ZHI);
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include(current_procinfo.flags,pi_do_call);
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end;
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procedure tcgavr.a_op_const_reg(list : TAsmList; Op: TOpCG; size: TCGSize; a: tcgint; reg: TRegister);
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var
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mask : qword;
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shift : byte;
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i : byte;
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tmpreg : tregister;
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begin
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mask:=$ff;
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shift:=0;
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case op of
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OP_OR:
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begin
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for i:=1 to tcgsize2size[size] do
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begin
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list.concat(taicpu.op_reg_const(A_ORI,reg,(a and mask) shr shift));
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reg:=GetNextReg(reg);
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mask:=mask shl 8;
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inc(shift,8);
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end;
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end;
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OP_AND:
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begin
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for i:=1 to tcgsize2size[size] do
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begin
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list.concat(taicpu.op_reg_const(A_ANDI,reg,(a and mask) shr shift));
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reg:=GetNextReg(reg);
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mask:=mask shl 8;
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inc(shift,8);
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end;
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end;
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OP_SUB:
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begin
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list.concat(taicpu.op_reg_const(A_SUBI,reg,a));
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if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
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begin
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for i:=2 to tcgsize2size[size] do
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begin
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reg:=GetNextReg(reg);
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mask:=mask shl 8;
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inc(shift,8);
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list.concat(taicpu.op_reg_const(A_SBCI,reg,(a and mask) shr shift));
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end;
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end;
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end;
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else
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begin
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tmpreg:=getintregister(list,size);
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a_load_const_reg(list,size,a,tmpreg);
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a_op_reg_reg(list,op,size,tmpreg,reg);
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end;
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end;
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end;
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procedure tcgavr.a_op_reg_reg(list : TAsmList; Op: TOpCG; size: TCGSize; src, dst: TRegister);
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var
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countreg,
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tmpreg: tregister;
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i : integer;
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instr : taicpu;
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paraloc1,paraloc2,paraloc3 : TCGPara;
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l1,l2 : tasmlabel;
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begin
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case op of
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OP_ADD:
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begin
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list.concat(taicpu.op_reg_reg(A_ADD,dst,src));
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if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
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begin
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for i:=2 to tcgsize2size[size] do
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begin
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dst:=GetNextReg(dst);
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src:=GetNextReg(src);
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list.concat(taicpu.op_reg_reg(A_ADC,dst,src));
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end;
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end
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else
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end;
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OP_SUB:
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begin
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list.concat(taicpu.op_reg_reg(A_SUB,dst,src));
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if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
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begin
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for i:=2 to tcgsize2size[size] do
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begin
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dst:=GetNextReg(dst);
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src:=GetNextReg(src);
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list.concat(taicpu.op_reg_reg(A_SBC,dst,src));
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end;
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end;
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end;
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OP_NEG:
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begin
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if src<>dst then
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a_load_reg_reg(list,size,size,src,dst);
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if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
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begin
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tmpreg:=GetNextReg(dst);
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for i:=2 to tcgsize2size[size] do
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begin
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list.concat(taicpu.op_reg(A_COM,tmpreg));
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tmpreg:=GetNextReg(tmpreg);
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end;
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list.concat(taicpu.op_reg(A_NEG,dst));
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tmpreg:=GetNextReg(dst);
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for i:=2 to tcgsize2size[size] do
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begin
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list.concat(taicpu.op_reg_const(A_SBCI,dst,-1));
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tmpreg:=GetNextReg(tmpreg);
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end;
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end
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else
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list.concat(taicpu.op_reg(A_NEG,dst));
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end;
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OP_NOT:
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begin
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for i:=1 to tcgsize2size[size] do
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begin
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if src<>dst then
|
|
a_load_reg_reg(list,OS_8,OS_8,src,dst);
|
|
list.concat(taicpu.op_reg(A_COM,dst));
|
|
src:=GetNextReg(src);
|
|
dst:=GetNextReg(dst);
|
|
end;
|
|
end;
|
|
|
|
OP_MUL,OP_IMUL:
|
|
begin
|
|
if size in [OS_8,OS_S8] then
|
|
list.concat(taicpu.op_reg_reg(topcg2asmop[op],dst,src))
|
|
else if size=OS_16 then
|
|
begin
|
|
paraloc1.init;
|
|
paraloc2.init;
|
|
paraloc3.init;
|
|
paramanager.getintparaloc(pocall_default,1,paraloc1);
|
|
paramanager.getintparaloc(pocall_default,2,paraloc2);
|
|
paramanager.getintparaloc(pocall_default,3,paraloc3);
|
|
a_load_const_cgpara(list,OS_8,0,paraloc3);
|
|
a_load_reg_cgpara(list,OS_16,src,paraloc2);
|
|
a_load_reg_cgpara(list,OS_16,dst,paraloc1);
|
|
paramanager.freecgpara(list,paraloc3);
|
|
paramanager.freecgpara(list,paraloc2);
|
|
paramanager.freecgpara(list,paraloc1);
|
|
alloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
|
|
a_call_name(list,'FPC_MUL_WORD',false);
|
|
dealloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
|
|
cg.a_reg_alloc(list,NR_FUNCTION_RESULT_REG);
|
|
cg.a_load_reg_reg(list,OS_16,OS_16,NR_FUNCTION_RESULT_REG,dst);
|
|
paraloc3.done;
|
|
paraloc2.done;
|
|
paraloc1.done;
|
|
end
|
|
else
|
|
internalerror(2011022002);
|
|
end;
|
|
|
|
OP_DIV,OP_IDIV:
|
|
{ special stuff, needs separate handling inside code }
|
|
{ generator }
|
|
internalerror(2011022001);
|
|
|
|
OP_SHR,OP_SHL,OP_SAR,OP_ROL,OP_ROR:
|
|
begin
|
|
current_asmdata.getjumplabel(l1);
|
|
current_asmdata.getjumplabel(l2);
|
|
countreg:=getintregister(list,OS_8);
|
|
a_load_reg_reg(list,size,OS_8,src,countreg);
|
|
list.concat(taicpu.op_reg_const(A_CP,countreg,0));
|
|
a_jmp_flags(list,F_EQ,l2);
|
|
cg.a_label(list,l1);
|
|
case op of
|
|
OP_SHR:
|
|
list.concat(taicpu.op_reg(A_LSR,GetOffsetReg(dst,tcgsize2size[size]-1)));
|
|
OP_SHL:
|
|
list.concat(taicpu.op_reg(A_LSL,dst));
|
|
OP_SAR:
|
|
list.concat(taicpu.op_reg(A_ASR,GetOffsetReg(dst,tcgsize2size[size]-1)));
|
|
OP_ROR:
|
|
begin
|
|
{ load carry? }
|
|
if not(size in [OS_8,OS_S8]) then
|
|
begin
|
|
list.concat(taicpu.op_none(A_CLC));
|
|
list.concat(taicpu.op_reg_const(A_SBRC,src,0));
|
|
list.concat(taicpu.op_none(A_SEC));
|
|
end;
|
|
list.concat(taicpu.op_reg(A_ROR,GetOffsetReg(dst,tcgsize2size[size]-1)));
|
|
end;
|
|
OP_ROL:
|
|
begin
|
|
{ load carry? }
|
|
if not(size in [OS_8,OS_S8]) then
|
|
begin
|
|
list.concat(taicpu.op_none(A_CLC));
|
|
list.concat(taicpu.op_reg_const(A_SBRC,GetOffsetReg(dst,tcgsize2size[size]-1),7));
|
|
list.concat(taicpu.op_none(A_SEC));
|
|
end;
|
|
list.concat(taicpu.op_reg(A_ROL,dst))
|
|
end;
|
|
else
|
|
internalerror(2011030901);
|
|
end;
|
|
if size in [OS_S16,OS_16,OS_S32,OS_32,OS_S64,OS_64] then
|
|
begin
|
|
for i:=2 to tcgsize2size[size] do
|
|
begin
|
|
case op of
|
|
OP_ROR,
|
|
OP_SHR:
|
|
list.concat(taicpu.op_reg(A_ROR,GetOffsetReg(dst,tcgsize2size[size]-i)));
|
|
OP_ROL,
|
|
OP_SHL:
|
|
list.concat(taicpu.op_reg(A_ROL,GetOffsetReg(dst,i-1)));
|
|
OP_SAR:
|
|
list.concat(taicpu.op_reg(A_ROR,GetOffsetReg(dst,tcgsize2size[size]-i)));
|
|
else
|
|
internalerror(2011030902);
|
|
end;
|
|
end;
|
|
end;
|
|
|
|
a_op_const_reg(list,OP_SUB,OS_8,1,countreg);
|
|
a_jmp_flags(list,F_NE,l1);
|
|
// keep registers alive
|
|
list.concat(taicpu.op_reg_reg(A_MOV,countreg,countreg));
|
|
cg.a_label(list,l2);
|
|
end;
|
|
|
|
OP_AND,OP_OR,OP_XOR:
|
|
begin
|
|
for i:=1 to tcgsize2size[size] do
|
|
begin
|
|
list.concat(taicpu.op_reg_reg(topcg2asmop[op],dst,src));
|
|
dst:=GetNextReg(dst);
|
|
src:=GetNextReg(src);
|
|
end;
|
|
end;
|
|
else
|
|
internalerror(2011022004);
|
|
end;
|
|
end;
|
|
|
|
|
|
procedure tcgavr.a_load_const_reg(list : TAsmList; size: tcgsize; a : tcgint;reg : tregister);
|
|
var
|
|
mask : qword;
|
|
shift : byte;
|
|
i : byte;
|
|
begin
|
|
mask:=$ff;
|
|
shift:=0;
|
|
for i:=1 to tcgsize2size[size] do
|
|
begin
|
|
if ((qword(a) and mask) shr shift)=0 then
|
|
emit_mov(list,reg,NR_R1)
|
|
else
|
|
list.concat(taicpu.op_reg_const(A_LDI,reg,(qword(a) and mask) shr shift));
|
|
|
|
mask:=mask shl 8;
|
|
inc(shift,8);
|
|
reg:=GetNextReg(reg);
|
|
end;
|
|
end;
|
|
|
|
|
|
function tcgavr.normalize_ref(list:TAsmList;ref: treference;tmpreg : tregister) : treference;
|
|
|
|
procedure maybegetcpuregister(list:tasmlist;reg : tregister);
|
|
begin
|
|
{ allocate the register only, if a cpu register is passed }
|
|
if getsupreg(reg)<first_int_imreg then
|
|
getcpuregister(list,reg);
|
|
end;
|
|
|
|
var
|
|
tmpref : treference;
|
|
l : tasmlabel;
|
|
begin
|
|
Result:=ref;
|
|
|
|
if ref.addressmode<>AM_UNCHANGED then
|
|
internalerror(2011021701);
|
|
|
|
{ Be sure to have a base register }
|
|
if (ref.base=NR_NO) then
|
|
begin
|
|
{ only symbol+offset? }
|
|
if ref.index=NR_NO then
|
|
exit;
|
|
ref.base:=ref.index;
|
|
ref.index:=NR_NO;
|
|
end;
|
|
if assigned(ref.symbol) or (ref.offset<>0) then
|
|
begin
|
|
reference_reset(tmpref,0);
|
|
tmpref.symbol:=ref.symbol;
|
|
tmpref.offset:=ref.offset;
|
|
tmpref.refaddr:=addr_lo8;
|
|
maybegetcpuregister(list,tmpreg);
|
|
list.concat(taicpu.op_reg_ref(A_LDI,tmpreg,tmpref));
|
|
tmpref.refaddr:=addr_hi8;
|
|
maybegetcpuregister(list,GetNextReg(tmpreg));
|
|
list.concat(taicpu.op_reg_ref(A_LDI,GetNextReg(tmpreg),tmpref));
|
|
if (ref.base<>NR_NO) then
|
|
begin
|
|
list.concat(taicpu.op_reg_reg(A_ADD,tmpreg,ref.base));
|
|
list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(tmpreg),GetNextReg(ref.base)));
|
|
end;
|
|
if (ref.index<>NR_NO) then
|
|
begin
|
|
list.concat(taicpu.op_reg_reg(A_ADD,tmpreg,ref.index));
|
|
list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(tmpreg),GetNextReg(ref.index)));
|
|
end;
|
|
ref.symbol:=nil;
|
|
ref.offset:=0;
|
|
ref.base:=tmpreg;
|
|
ref.index:=NR_NO;
|
|
end
|
|
else if (ref.base<>NR_NO) and (ref.index<>NR_NO) then
|
|
begin
|
|
maybegetcpuregister(list,tmpreg);
|
|
emit_mov(list,tmpreg,ref.index);
|
|
maybegetcpuregister(list,GetNextReg(tmpreg));
|
|
emit_mov(list,GetNextReg(tmpreg),GetNextReg(ref.index));
|
|
list.concat(taicpu.op_reg_reg(A_ADD,tmpreg,ref.base));
|
|
list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(tmpreg),GetNextReg(ref.base)));
|
|
ref.base:=tmpreg;
|
|
ref.index:=NR_NO;
|
|
end
|
|
else if (ref.base<>NR_NO) then
|
|
begin
|
|
maybegetcpuregister(list,tmpreg);
|
|
emit_mov(list,tmpreg,ref.base);
|
|
maybegetcpuregister(list,GetNextReg(tmpreg));
|
|
emit_mov(list,GetNextReg(tmpreg),GetNextReg(ref.base));
|
|
ref.base:=tmpreg;
|
|
ref.index:=NR_NO;
|
|
end
|
|
else if (ref.index<>NR_NO) then
|
|
begin
|
|
maybegetcpuregister(list,tmpreg);
|
|
emit_mov(list,tmpreg,ref.index);
|
|
maybegetcpuregister(list,GetNextReg(tmpreg));
|
|
emit_mov(list,GetNextReg(tmpreg),GetNextReg(ref.index));
|
|
ref.base:=tmpreg;
|
|
ref.index:=NR_NO;
|
|
end;
|
|
Result:=ref;
|
|
end;
|
|
|
|
|
|
procedure tcgavr.a_load_reg_ref(list : TAsmList; fromsize, tosize: tcgsize; reg : tregister;const ref : treference);
|
|
var
|
|
href : treference;
|
|
conv_done: boolean;
|
|
tmpreg : tregister;
|
|
i : integer;
|
|
QuickRef : Boolean;
|
|
begin
|
|
QuickRef:=false;
|
|
if not((Ref.addressmode=AM_UNCHANGED) and
|
|
(Ref.symbol=nil) and
|
|
((Ref.base=NR_R28) or
|
|
(Ref.base=NR_R29)) and
|
|
(Ref.Index=NR_No) and
|
|
(Ref.Offset in [0..64-tcgsize2size[tosize]])) and
|
|
not((Ref.Base=NR_NO) and (Ref.Index=NR_NO)) then
|
|
href:=normalize_ref(list,Ref,NR_R30)
|
|
else
|
|
begin
|
|
QuickRef:=true;
|
|
href:=Ref;
|
|
end;
|
|
|
|
if (tcgsize2size[fromsize]>32) or (tcgsize2size[tosize]>32) or (fromsize=OS_NO) or (tosize=OS_NO) then
|
|
internalerror(2011021307);
|
|
|
|
conv_done:=false;
|
|
if tosize<>fromsize then
|
|
begin
|
|
conv_done:=true;
|
|
if tcgsize2size[tosize]<=tcgsize2size[fromsize] then
|
|
fromsize:=tosize;
|
|
case fromsize of
|
|
OS_8:
|
|
begin
|
|
if not(QuickRef) and (tcgsize2size[tosize]>1) then
|
|
href.addressmode:=AM_POSTINCREMENT;
|
|
|
|
list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
|
|
for i:=2 to tcgsize2size[tosize] do
|
|
begin
|
|
if QuickRef then
|
|
inc(href.offset);
|
|
|
|
if not(QuickRef) and (i<tcgsize2size[fromsize]) then
|
|
href.addressmode:=AM_POSTINCREMENT
|
|
else
|
|
href.addressmode:=AM_UNCHANGED;
|
|
|
|
list.concat(taicpu.op_ref_reg(GetStore(href),href,NR_R1));
|
|
end;
|
|
end;
|
|
OS_S8:
|
|
begin
|
|
if not(QuickRef) and (tcgsize2size[tosize]>1) then
|
|
href.addressmode:=AM_POSTINCREMENT;
|
|
list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
|
|
|
|
if tcgsize2size[tosize]>1 then
|
|
begin
|
|
tmpreg:=getintregister(list,OS_8);
|
|
list.concat(taicpu.op_reg(A_CLR,tmpreg));
|
|
list.concat(taicpu.op_reg_const(A_SBRC,reg,7));
|
|
list.concat(taicpu.op_reg(A_COM,tmpreg));
|
|
for i:=2 to tcgsize2size[tosize] do
|
|
begin
|
|
if QuickRef then
|
|
inc(href.offset);
|
|
|
|
if not(QuickRef) and (i<tcgsize2size[fromsize]) then
|
|
href.addressmode:=AM_POSTINCREMENT
|
|
else
|
|
href.addressmode:=AM_UNCHANGED;
|
|
list.concat(taicpu.op_ref_reg(GetStore(href),href,tmpreg));
|
|
end;
|
|
end;
|
|
end;
|
|
OS_16:
|
|
begin
|
|
if not(QuickRef) and (tcgsize2size[tosize]>1) then
|
|
href.addressmode:=AM_POSTINCREMENT;
|
|
|
|
list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
|
|
if QuickRef then
|
|
inc(href.offset)
|
|
else if not(QuickRef) and (tcgsize2size[fromsize]>2) then
|
|
href.addressmode:=AM_POSTINCREMENT
|
|
else
|
|
href.addressmode:=AM_UNCHANGED;
|
|
|
|
reg:=GetNextReg(reg);
|
|
list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
|
|
|
|
for i:=3 to tcgsize2size[tosize] do
|
|
begin
|
|
if QuickRef then
|
|
inc(href.offset);
|
|
|
|
if not(QuickRef) and (i<tcgsize2size[fromsize]) then
|
|
href.addressmode:=AM_POSTINCREMENT
|
|
else
|
|
href.addressmode:=AM_UNCHANGED;
|
|
|
|
list.concat(taicpu.op_ref_reg(GetStore(href),href,NR_R1));
|
|
end;
|
|
end;
|
|
OS_S16:
|
|
begin
|
|
if not(QuickRef) and (tcgsize2size[tosize]>1) then
|
|
href.addressmode:=AM_POSTINCREMENT;
|
|
|
|
list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
|
|
if QuickRef then
|
|
inc(href.offset)
|
|
else if not(QuickRef) and (tcgsize2size[fromsize]>2) then
|
|
href.addressmode:=AM_POSTINCREMENT
|
|
else
|
|
href.addressmode:=AM_UNCHANGED;
|
|
|
|
reg:=GetNextReg(reg);
|
|
list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
|
|
|
|
if tcgsize2size[tosize]>2 then
|
|
begin
|
|
tmpreg:=getintregister(list,OS_8);
|
|
list.concat(taicpu.op_reg(A_CLR,tmpreg));
|
|
list.concat(taicpu.op_reg_const(A_SBRC,reg,7));
|
|
list.concat(taicpu.op_reg(A_COM,tmpreg));
|
|
for i:=3 to tcgsize2size[tosize] do
|
|
begin
|
|
if QuickRef then
|
|
inc(href.offset);
|
|
|
|
if not(QuickRef) and (i<tcgsize2size[fromsize]) then
|
|
href.addressmode:=AM_POSTINCREMENT
|
|
else
|
|
href.addressmode:=AM_UNCHANGED;
|
|
list.concat(taicpu.op_ref_reg(GetStore(href),href,tmpreg));
|
|
end;
|
|
end;
|
|
end;
|
|
else
|
|
conv_done:=false;
|
|
end;
|
|
end;
|
|
if not conv_done then
|
|
begin
|
|
for i:=1 to tcgsize2size[fromsize] do
|
|
begin
|
|
if not(QuickRef) and (i<tcgsize2size[fromsize]) then
|
|
href.addressmode:=AM_POSTINCREMENT
|
|
else
|
|
href.addressmode:=AM_UNCHANGED;
|
|
|
|
list.concat(taicpu.op_ref_reg(GetStore(href),href,reg));
|
|
|
|
if QuickRef then
|
|
inc(href.offset);
|
|
|
|
reg:=GetNextReg(reg);
|
|
end;
|
|
end;
|
|
|
|
if not(QuickRef) then
|
|
begin
|
|
ungetcpuregister(list,href.base);
|
|
ungetcpuregister(list,GetNextReg(href.base));
|
|
end;
|
|
end;
|
|
|
|
|
|
procedure tcgavr.a_load_ref_reg(list : TAsmList; fromsize, tosize : tcgsize;
|
|
const Ref : treference;reg : tregister);
|
|
var
|
|
href : treference;
|
|
conv_done: boolean;
|
|
tmpreg : tregister;
|
|
i : integer;
|
|
QuickRef : boolean;
|
|
begin
|
|
QuickRef:=false;
|
|
if not((Ref.addressmode=AM_UNCHANGED) and
|
|
(Ref.symbol=nil) and
|
|
((Ref.base=NR_R28) or
|
|
(Ref.base=NR_R29)) and
|
|
(Ref.Index=NR_No) and
|
|
(Ref.Offset in [0..64-tcgsize2size[fromsize]])) and
|
|
not((Ref.Base=NR_NO) and (Ref.Index=NR_NO)) then
|
|
href:=normalize_ref(list,Ref,NR_R30)
|
|
else
|
|
begin
|
|
QuickRef:=true;
|
|
href:=Ref;
|
|
end;
|
|
|
|
if (tcgsize2size[fromsize]>32) or (tcgsize2size[tosize]>32) or (fromsize=OS_NO) or (tosize=OS_NO) then
|
|
internalerror(2011021307);
|
|
|
|
conv_done:=false;
|
|
if tosize<>fromsize then
|
|
begin
|
|
conv_done:=true;
|
|
if tcgsize2size[tosize]<=tcgsize2size[fromsize] then
|
|
fromsize:=tosize;
|
|
case fromsize of
|
|
OS_8:
|
|
begin
|
|
list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
|
|
for i:=2 to tcgsize2size[tosize] do
|
|
begin
|
|
reg:=GetNextReg(reg);
|
|
list.concat(taicpu.op_reg(A_CLR,reg));
|
|
end;
|
|
end;
|
|
OS_S8:
|
|
begin
|
|
list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
|
|
tmpreg:=reg;
|
|
|
|
if tcgsize2size[tosize]>1 then
|
|
begin
|
|
reg:=GetNextReg(reg);
|
|
list.concat(taicpu.op_reg(A_CLR,reg));
|
|
list.concat(taicpu.op_reg_const(A_SBRC,tmpreg,7));
|
|
list.concat(taicpu.op_reg(A_COM,reg));
|
|
tmpreg:=reg;
|
|
for i:=3 to tcgsize2size[tosize] do
|
|
begin
|
|
reg:=GetNextReg(reg);
|
|
emit_mov(list,reg,tmpreg);
|
|
end;
|
|
end;
|
|
end;
|
|
OS_16:
|
|
begin
|
|
if not(QuickRef) then
|
|
href.addressmode:=AM_POSTINCREMENT;
|
|
list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
|
|
|
|
if QuickRef then
|
|
inc(href.offset);
|
|
href.addressmode:=AM_UNCHANGED;
|
|
|
|
reg:=GetNextReg(reg);
|
|
list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
|
|
|
|
for i:=3 to tcgsize2size[tosize] do
|
|
begin
|
|
reg:=GetNextReg(reg);
|
|
list.concat(taicpu.op_reg(A_CLR,reg));
|
|
end;
|
|
end;
|
|
OS_S16:
|
|
begin
|
|
if not(QuickRef) then
|
|
href.addressmode:=AM_POSTINCREMENT;
|
|
list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
|
|
if QuickRef then
|
|
inc(href.offset);
|
|
href.addressmode:=AM_UNCHANGED;
|
|
|
|
reg:=GetNextReg(reg);
|
|
list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
|
|
tmpreg:=reg;
|
|
|
|
reg:=GetNextReg(reg);
|
|
list.concat(taicpu.op_reg(A_CLR,reg));
|
|
list.concat(taicpu.op_reg_const(A_SBRC,tmpreg,7));
|
|
list.concat(taicpu.op_reg(A_COM,reg));
|
|
tmpreg:=reg;
|
|
for i:=4 to tcgsize2size[tosize] do
|
|
begin
|
|
reg:=GetNextReg(reg);
|
|
emit_mov(list,reg,tmpreg);
|
|
end;
|
|
end;
|
|
else
|
|
conv_done:=false;
|
|
end;
|
|
end;
|
|
if not conv_done then
|
|
begin
|
|
for i:=1 to tcgsize2size[fromsize] do
|
|
begin
|
|
if not(QuickRef) and (i<tcgsize2size[fromsize]) then
|
|
href.addressmode:=AM_POSTINCREMENT
|
|
else
|
|
href.addressmode:=AM_UNCHANGED;
|
|
|
|
list.concat(taicpu.op_reg_ref(GetLoad(href),reg,href));
|
|
|
|
if QuickRef then
|
|
inc(href.offset);
|
|
|
|
reg:=GetNextReg(reg);
|
|
end;
|
|
end;
|
|
|
|
if not(QuickRef) then
|
|
begin
|
|
ungetcpuregister(list,href.base);
|
|
ungetcpuregister(list,GetNextReg(href.base));
|
|
end;
|
|
end;
|
|
|
|
|
|
procedure tcgavr.a_load_reg_reg(list : TAsmList; fromsize, tosize : tcgsize;reg1,reg2 : tregister);
|
|
var
|
|
conv_done: boolean;
|
|
tmpreg : tregister;
|
|
i : integer;
|
|
begin
|
|
if (tcgsize2size[fromsize]>32) or (tcgsize2size[tosize]>32) or (fromsize=OS_NO) or (tosize=OS_NO) then
|
|
internalerror(2011021310);
|
|
|
|
conv_done:=false;
|
|
if tosize<>fromsize then
|
|
begin
|
|
conv_done:=true;
|
|
if tcgsize2size[tosize]<=tcgsize2size[fromsize] then
|
|
fromsize:=tosize;
|
|
case fromsize of
|
|
OS_8:
|
|
begin
|
|
emit_mov(list,reg2,reg1);
|
|
for i:=2 to tcgsize2size[tosize] do
|
|
begin
|
|
reg2:=GetNextReg(reg2);
|
|
list.concat(taicpu.op_reg(A_CLR,reg2));
|
|
end;
|
|
end;
|
|
OS_S8:
|
|
begin
|
|
{ dest is always at least 16 bit at this point }
|
|
emit_mov(list,reg2,reg1);
|
|
|
|
reg2:=GetNextReg(reg2);
|
|
list.concat(taicpu.op_reg(A_CLR,reg2));
|
|
list.concat(taicpu.op_reg_const(A_SBRC,reg1,7));
|
|
list.concat(taicpu.op_reg(A_COM,reg2));
|
|
tmpreg:=reg2;
|
|
for i:=3 to tcgsize2size[tosize] do
|
|
begin
|
|
reg2:=GetNextReg(reg2);
|
|
emit_mov(list,reg2,tmpreg);
|
|
end;
|
|
end;
|
|
OS_16:
|
|
begin
|
|
emit_mov(list,reg2,reg1);
|
|
|
|
reg1:=GetNextReg(reg1);
|
|
reg2:=GetNextReg(reg2);
|
|
emit_mov(list,reg2,reg1);
|
|
|
|
for i:=3 to tcgsize2size[tosize] do
|
|
begin
|
|
reg2:=GetNextReg(reg2);
|
|
list.concat(taicpu.op_reg(A_CLR,reg2));
|
|
end;
|
|
end;
|
|
OS_S16:
|
|
begin
|
|
{ dest is always at least 32 bit at this point }
|
|
emit_mov(list,reg2,reg1);
|
|
|
|
reg1:=GetNextReg(reg1);
|
|
reg2:=GetNextReg(reg2);
|
|
emit_mov(list,reg2,reg1);
|
|
|
|
reg2:=GetNextReg(reg2);
|
|
list.concat(taicpu.op_reg(A_CLR,reg2));
|
|
list.concat(taicpu.op_reg_const(A_SBRC,reg1,7));
|
|
list.concat(taicpu.op_reg(A_COM,reg2));
|
|
tmpreg:=reg2;
|
|
for i:=4 to tcgsize2size[tosize] do
|
|
begin
|
|
reg2:=GetNextReg(reg2);
|
|
emit_mov(list,reg2,tmpreg);
|
|
end;
|
|
end;
|
|
else
|
|
conv_done:=false;
|
|
end;
|
|
end;
|
|
if not conv_done and (reg1<>reg2) then
|
|
begin
|
|
for i:=1 to tcgsize2size[fromsize] do
|
|
begin
|
|
emit_mov(list,reg2,reg1);
|
|
reg1:=GetNextReg(reg1);
|
|
reg2:=GetNextReg(reg2);
|
|
end;
|
|
end;
|
|
end;
|
|
|
|
|
|
procedure tcgavr.a_loadfpu_reg_reg(list: TAsmList; fromsize,tosize: tcgsize; reg1, reg2: tregister);
|
|
begin
|
|
internalerror(2012010702);
|
|
end;
|
|
|
|
|
|
procedure tcgavr.a_loadfpu_ref_reg(list: TAsmList; fromsize,tosize: tcgsize; const ref: treference; reg: tregister);
|
|
begin
|
|
internalerror(2012010703);
|
|
end;
|
|
|
|
|
|
procedure tcgavr.a_loadfpu_reg_ref(list: TAsmList; fromsize, tosize: tcgsize; reg: tregister; const ref: treference);
|
|
begin
|
|
internalerror(2012010704);
|
|
end;
|
|
|
|
|
|
{ comparison operations }
|
|
procedure tcgavr.a_cmp_const_reg_label(list : TAsmList;size : tcgsize;
|
|
cmp_op : topcmp;a : tcgint;reg : tregister;l : tasmlabel);
|
|
var
|
|
swapped : boolean;
|
|
tmpreg : tregister;
|
|
i : byte;
|
|
begin
|
|
if a=0 then
|
|
begin
|
|
{ swap parameters? }
|
|
case cmp_op of
|
|
OC_GT:
|
|
begin
|
|
swapped:=true;
|
|
cmp_op:=OC_LT;
|
|
end;
|
|
OC_LTE:
|
|
begin
|
|
swapped:=true;
|
|
cmp_op:=OC_GTE;
|
|
end;
|
|
OC_BE:
|
|
begin
|
|
swapped:=true;
|
|
cmp_op:=OC_AE;
|
|
end;
|
|
OC_A:
|
|
begin
|
|
swapped:=true;
|
|
cmp_op:=OC_A;
|
|
end;
|
|
end;
|
|
|
|
if swapped then
|
|
list.concat(taicpu.op_reg_reg(A_CP,reg,NR_R1))
|
|
else
|
|
list.concat(taicpu.op_reg_reg(A_CP,NR_R1,reg));
|
|
|
|
for i:=2 to tcgsize2size[size] do
|
|
begin
|
|
reg:=GetNextReg(reg);
|
|
if swapped then
|
|
list.concat(taicpu.op_reg_reg(A_CPC,reg,NR_R1))
|
|
else
|
|
list.concat(taicpu.op_reg_reg(A_CPC,NR_R1,reg));
|
|
end;
|
|
|
|
a_jmp_cond(list,cmp_op,l);
|
|
end
|
|
else
|
|
inherited a_cmp_const_reg_label(list,size,cmp_op,a,reg,l);
|
|
end;
|
|
|
|
|
|
procedure tcgavr.a_cmp_reg_reg_label(list : TAsmList;size : tcgsize;
|
|
cmp_op : topcmp;reg1,reg2 : tregister;l : tasmlabel);
|
|
var
|
|
swapped : boolean;
|
|
tmpreg : tregister;
|
|
i : byte;
|
|
begin
|
|
{ swap parameters? }
|
|
case cmp_op of
|
|
OC_GT:
|
|
begin
|
|
swapped:=true;
|
|
cmp_op:=OC_LT;
|
|
end;
|
|
OC_LTE:
|
|
begin
|
|
swapped:=true;
|
|
cmp_op:=OC_GTE;
|
|
end;
|
|
OC_BE:
|
|
begin
|
|
swapped:=true;
|
|
cmp_op:=OC_AE;
|
|
end;
|
|
OC_A:
|
|
begin
|
|
swapped:=true;
|
|
cmp_op:=OC_A;
|
|
end;
|
|
end;
|
|
if swapped then
|
|
begin
|
|
tmpreg:=reg1;
|
|
reg1:=reg2;
|
|
reg2:=tmpreg;
|
|
end;
|
|
list.concat(taicpu.op_reg_reg(A_CP,reg1,reg2));
|
|
|
|
for i:=2 to tcgsize2size[size] do
|
|
begin
|
|
reg1:=GetNextReg(reg1);
|
|
reg2:=GetNextReg(reg2);
|
|
list.concat(taicpu.op_reg_reg(A_CPC,reg1,reg2));
|
|
end;
|
|
|
|
a_jmp_cond(list,cmp_op,l);
|
|
end;
|
|
|
|
|
|
procedure tcgavr.a_bit_scan_reg_reg(list: TAsmList; reverse: boolean; size: TCGSize; src, dst: TRegister);
|
|
begin
|
|
Comment(V_Error,'tcgarm.a_bit_scan_reg_reg method not implemented');
|
|
end;
|
|
|
|
|
|
procedure tcgavr.a_jmp_name(list : TAsmList;const s : string);
|
|
var
|
|
ai : taicpu;
|
|
begin
|
|
ai:=taicpu.op_sym(A_JMP,current_asmdata.RefAsmSymbol(s));
|
|
ai.is_jmp:=true;
|
|
list.concat(ai);
|
|
end;
|
|
|
|
|
|
procedure tcgavr.a_jmp_always(list : TAsmList;l: tasmlabel);
|
|
var
|
|
ai : taicpu;
|
|
begin
|
|
ai:=taicpu.op_sym(A_JMP,l);
|
|
ai.is_jmp:=true;
|
|
list.concat(ai);
|
|
end;
|
|
|
|
|
|
procedure tcgavr.a_jmp_flags(list : TAsmList;const f : TResFlags;l: tasmlabel);
|
|
var
|
|
ai : taicpu;
|
|
begin
|
|
ai:=setcondition(taicpu.op_sym(A_BRxx,l),flags_to_cond(f));
|
|
ai.is_jmp:=true;
|
|
list.concat(ai);
|
|
end;
|
|
|
|
|
|
procedure tcgavr.g_flags2reg(list: TAsmList; size: TCgSize; const f: TResFlags; reg: TRegister);
|
|
var
|
|
l : TAsmLabel;
|
|
tmpflags : TResFlags;
|
|
begin
|
|
current_asmdata.getjumplabel(l);
|
|
{
|
|
if flags_to_cond(f) then
|
|
begin
|
|
tmpflags:=f;
|
|
inverse_flags(tmpflags);
|
|
list.concat(taicpu.op_reg(A_CLR,reg));
|
|
a_jmp_flags(list,tmpflags,l);
|
|
list.concat(taicpu.op_reg_const(A_LDI,reg,1));
|
|
end
|
|
else
|
|
}
|
|
begin
|
|
list.concat(taicpu.op_reg_const(A_LDI,reg,1));
|
|
a_jmp_flags(list,f,l);
|
|
list.concat(taicpu.op_reg(A_CLR,reg));
|
|
end;
|
|
cg.a_label(list,l);
|
|
end;
|
|
|
|
|
|
procedure tcgavr.a_adjust_sp(list : TAsmList; value : longint);
|
|
var
|
|
i : integer;
|
|
begin
|
|
case value of
|
|
0:
|
|
;
|
|
-14..-1:
|
|
begin
|
|
if ((-value) mod 2)<>0 then
|
|
list.concat(taicpu.op_reg(A_PUSH,NR_R0));
|
|
for i:=1 to (-value) div 2 do
|
|
list.concat(taicpu.op_const(A_RCALL,0));
|
|
end;
|
|
1..7:
|
|
begin
|
|
for i:=1 to value do
|
|
list.concat(taicpu.op_reg(A_POP,NR_R0));
|
|
end;
|
|
else
|
|
begin
|
|
list.concat(taicpu.op_reg_const(A_SUBI,NR_R28,lo(word(-value))));
|
|
list.concat(taicpu.op_reg_const(A_SBCI,NR_R29,hi(word(-value))));
|
|
// get SREG
|
|
list.concat(taicpu.op_reg_const(A_IN,NR_R0,NIO_SREG));
|
|
|
|
// block interrupts
|
|
list.concat(taicpu.op_none(A_CLI));
|
|
|
|
// write high SP
|
|
list.concat(taicpu.op_const_reg(A_OUT,NIO_SP_HI,NR_R29));
|
|
|
|
// release interrupts
|
|
list.concat(taicpu.op_const_reg(A_OUT,NIO_SREG,NR_R0));
|
|
|
|
// write low SP
|
|
list.concat(taicpu.op_const_reg(A_OUT,NIO_SP_LO,NR_R28));
|
|
end;
|
|
end;
|
|
end;
|
|
|
|
|
|
function tcgavr.GetLoad(const ref: treference) : tasmop;
|
|
begin
|
|
if (ref.base=NR_NO) and (ref.index=NR_NO) then
|
|
result:=A_LDS
|
|
else if (ref.base<>NR_NO) and (ref.offset<>0) then
|
|
result:=A_LDD
|
|
else
|
|
result:=A_LD;
|
|
end;
|
|
|
|
|
|
function tcgavr.GetStore(const ref: treference) : tasmop;
|
|
begin
|
|
if (ref.base=NR_NO) and (ref.index=NR_NO) then
|
|
result:=A_STS
|
|
else if (ref.base<>NR_NO) and (ref.offset<>0) then
|
|
result:=A_STD
|
|
else
|
|
result:=A_ST;
|
|
end;
|
|
|
|
|
|
procedure tcgavr.g_proc_entry(list : TAsmList;localsize : longint;nostackframe:boolean);
|
|
var
|
|
regs : tcpuregisterset;
|
|
reg : tsuperregister;
|
|
begin
|
|
if not(nostackframe) then
|
|
begin
|
|
{ save int registers }
|
|
regs:=rg[R_INTREGISTER].used_in_proc-paramanager.get_volatile_registers_int(pocall_stdcall);
|
|
if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
|
|
regs:=regs+[RS_R28,RS_R29];
|
|
|
|
for reg:=RS_R31 downto RS_R0 do
|
|
if reg in regs then
|
|
list.concat(taicpu.op_reg(A_PUSH,newreg(R_INTREGISTER,reg,R_SUBWHOLE)));
|
|
|
|
if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
|
|
begin
|
|
list.concat(taicpu.op_reg_const(A_IN,NR_R28,NIO_SP_LO));
|
|
list.concat(taicpu.op_reg_const(A_IN,NR_R29,NIO_SP_HI));
|
|
end
|
|
else
|
|
{ the framepointer cannot be omitted on avr because sp
|
|
is not a register but part of the i/o map
|
|
}
|
|
internalerror(2011021901);
|
|
|
|
a_adjust_sp(list,-localsize);
|
|
end;
|
|
end;
|
|
|
|
|
|
procedure tcgavr.g_proc_exit(list : TAsmList;parasize : longint;nostackframe:boolean);
|
|
var
|
|
regs : tcpuregisterset;
|
|
reg : TSuperRegister;
|
|
LocalSize : longint;
|
|
begin
|
|
if not(nostackframe) then
|
|
begin
|
|
if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
|
|
begin
|
|
LocalSize:=current_procinfo.calc_stackframe_size;
|
|
a_adjust_sp(list,LocalSize);
|
|
regs:=rg[R_INTREGISTER].used_in_proc-paramanager.get_volatile_registers_int(pocall_stdcall);
|
|
|
|
for reg:=RS_R0 to RS_R31 do
|
|
if reg in regs then
|
|
list.concat(taicpu.op_reg(A_POP,newreg(R_INTREGISTER,reg,R_SUBWHOLE)));
|
|
|
|
end
|
|
else
|
|
{ the framepointer cannot be omitted on avr because sp
|
|
is not a register but part of the i/o map
|
|
}
|
|
internalerror(2011021902);
|
|
end;
|
|
list.concat(taicpu.op_none(A_RET));
|
|
end;
|
|
|
|
|
|
procedure tcgavr.a_loadaddr_ref_reg(list : TAsmList;const ref : treference;r : tregister);
|
|
var
|
|
tmpref : treference;
|
|
begin
|
|
if ref.addressmode<>AM_UNCHANGED then
|
|
internalerror(2011021701);
|
|
|
|
if assigned(ref.symbol) or (ref.offset<>0) then
|
|
begin
|
|
reference_reset(tmpref,0);
|
|
tmpref.symbol:=ref.symbol;
|
|
tmpref.offset:=ref.offset;
|
|
tmpref.refaddr:=addr_lo8;
|
|
list.concat(taicpu.op_reg_ref(A_LDI,r,tmpref));
|
|
tmpref.refaddr:=addr_hi8;
|
|
list.concat(taicpu.op_reg_ref(A_LDI,GetNextReg(r),tmpref));
|
|
if (ref.base<>NR_NO) then
|
|
begin
|
|
list.concat(taicpu.op_reg_reg(A_ADD,r,ref.base));
|
|
list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(r),GetNextReg(ref.base)));
|
|
end;
|
|
if (ref.index<>NR_NO) then
|
|
begin
|
|
list.concat(taicpu.op_reg_reg(A_ADD,r,ref.index));
|
|
list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(r),GetNextReg(ref.index)));
|
|
end;
|
|
end
|
|
else if (ref.base<>NR_NO)then
|
|
begin
|
|
emit_mov(list,r,ref.base);
|
|
emit_mov(list,GetNextReg(r),GetNextReg(ref.base));
|
|
if (ref.index<>NR_NO) then
|
|
begin
|
|
list.concat(taicpu.op_reg_reg(A_ADD,r,ref.index));
|
|
list.concat(taicpu.op_reg_reg(A_ADC,GetNextReg(r),GetNextReg(ref.index)));
|
|
end;
|
|
end
|
|
else if (ref.index<>NR_NO) then
|
|
begin
|
|
emit_mov(list,r,ref.index);
|
|
emit_mov(list,GetNextReg(r),GetNextReg(ref.index));
|
|
end;
|
|
end;
|
|
|
|
|
|
procedure tcgavr.fixref(list : TAsmList;var ref : treference);
|
|
begin
|
|
internalerror(2011021320);
|
|
end;
|
|
|
|
|
|
procedure tcgavr.g_concatcopy_move(list : TAsmList;const source,dest : treference;len : tcgint);
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var
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paraloc1,paraloc2,paraloc3 : TCGPara;
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begin
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paraloc1.init;
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paraloc2.init;
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paraloc3.init;
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paramanager.getintparaloc(pocall_default,1,paraloc1);
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paramanager.getintparaloc(pocall_default,2,paraloc2);
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paramanager.getintparaloc(pocall_default,3,paraloc3);
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a_load_const_cgpara(list,OS_INT,len,paraloc3);
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a_loadaddr_ref_cgpara(list,dest,paraloc2);
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a_loadaddr_ref_cgpara(list,source,paraloc1);
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paramanager.freecgpara(list,paraloc3);
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paramanager.freecgpara(list,paraloc2);
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paramanager.freecgpara(list,paraloc1);
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alloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
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a_call_name_static(list,'FPC_MOVE');
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dealloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
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paraloc3.done;
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paraloc2.done;
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paraloc1.done;
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end;
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procedure tcgavr.g_concatcopy(list : TAsmList;const source,dest : treference;len : tcgint);
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var
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countreg,tmpreg : tregister;
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srcref,dstref : treference;
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copysize,countregsize : tcgsize;
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l : TAsmLabel;
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i : longint;
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SrcQuickRef, DestQuickRef : Boolean;
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begin
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if len>16 then
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begin
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current_asmdata.getjumplabel(l);
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reference_reset(srcref,0);
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reference_reset(dstref,0);
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srcref.base:=NR_R30;
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srcref.addressmode:=AM_POSTINCREMENT;
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dstref.base:=NR_R26;
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dstref.addressmode:=AM_POSTINCREMENT;
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copysize:=OS_8;
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if len<256 then
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countregsize:=OS_8
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else if len<65536 then
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countregsize:=OS_16
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else
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internalerror(2011022007);
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countreg:=getintregister(list,countregsize);
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a_load_const_reg(list,countregsize,len,countreg);
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a_loadaddr_ref_reg(list,source,NR_R30);
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tmpreg:=getaddressregister(list);
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a_loadaddr_ref_reg(list,dest,tmpreg);
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{ X is used for spilling code so we can load it
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only by a push/pop sequence, this can be
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optimized later on by the peephole optimizer
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}
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list.concat(taicpu.op_reg(A_PUSH,tmpreg));
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list.concat(taicpu.op_reg(A_PUSH,GetNextReg(tmpreg)));
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list.concat(taicpu.op_reg(A_POP,NR_R27));
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list.concat(taicpu.op_reg(A_POP,NR_R26));
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cg.a_label(list,l);
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list.concat(taicpu.op_reg_ref(GetLoad(srcref),NR_R0,srcref));
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list.concat(taicpu.op_ref_reg(GetStore(dstref),dstref,NR_R0));
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a_op_const_reg(list,OP_SUB,countregsize,1,countreg);
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a_jmp_flags(list,F_NE,l);
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// keep registers alive
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list.concat(taicpu.op_reg_reg(A_MOV,countreg,countreg));
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end
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else
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begin
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SrcQuickRef:=false;
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DestQuickRef:=false;
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if not((source.addressmode=AM_UNCHANGED) and
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(source.symbol=nil) and
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((source.base=NR_R28) or
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(source.base=NR_R29)) and
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(source.Index=NR_NO) and
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(source.Offset in [0..64-len])) and
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not((source.Base=NR_NO) and (source.Index=NR_NO)) then
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srcref:=normalize_ref(list,source,NR_R30)
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else
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begin
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SrcQuickRef:=true;
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srcref:=source;
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end;
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if not((dest.addressmode=AM_UNCHANGED) and
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(dest.symbol=nil) and
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((dest.base=NR_R28) or
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(dest.base=NR_R29)) and
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(dest.Index=NR_No) and
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(dest.Offset in [0..64-len])) and
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not((dest.Base=NR_NO) and (dest.Index=NR_NO)) then
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begin
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if not(SrcQuickRef) then
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begin
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tmpreg:=getaddressregister(list);
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dstref:=normalize_ref(list,dest,tmpreg);
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{ X is used for spilling code so we can load it
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only by a push/pop sequence, this can be
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optimized later on by the peephole optimizer
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}
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list.concat(taicpu.op_reg(A_PUSH,tmpreg));
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list.concat(taicpu.op_reg(A_PUSH,GetNextReg(tmpreg)));
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list.concat(taicpu.op_reg(A_POP,NR_R27));
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list.concat(taicpu.op_reg(A_POP,NR_R26));
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dstref.base:=NR_R26;
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end
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else
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dstref:=normalize_ref(list,dest,NR_R30);
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end
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else
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begin
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DestQuickRef:=true;
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dstref:=dest;
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end;
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for i:=1 to len do
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begin
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if not(SrcQuickRef) and (i<len) then
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srcref.addressmode:=AM_POSTINCREMENT
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else
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srcref.addressmode:=AM_UNCHANGED;
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if not(DestQuickRef) and (i<len) then
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dstref.addressmode:=AM_POSTINCREMENT
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else
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dstref.addressmode:=AM_UNCHANGED;
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list.concat(taicpu.op_reg_ref(GetLoad(srcref),NR_R0,srcref));
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list.concat(taicpu.op_ref_reg(GetStore(dstref),dstref,NR_R0));
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if SrcQuickRef then
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inc(srcref.offset);
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if DestQuickRef then
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inc(dstref.offset);
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end;
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if not(SrcQuickRef) then
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begin
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ungetcpuregister(list,srcref.base);
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ungetcpuregister(list,GetNextReg(srcref.base));
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end;
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end;
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end;
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procedure tcgavr.g_overflowCheck(list : TAsmList;const l : tlocation;def : tdef);
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var
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hl : tasmlabel;
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ai : taicpu;
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cond : TAsmCond;
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begin
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if not(cs_check_overflow in current_settings.localswitches) then
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exit;
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current_asmdata.getjumplabel(hl);
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if not ((def.typ=pointerdef) or
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((def.typ=orddef) and
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(torddef(def).ordtype in [u64bit,u16bit,u32bit,u8bit,uchar,
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pasbool8,pasbool16,pasbool32,pasbool64]))) then
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cond:=C_VC
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else
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cond:=C_CC;
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ai:=Taicpu.Op_Sym(A_BRxx,hl);
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ai.SetCondition(cond);
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ai.is_jmp:=true;
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list.concat(ai);
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a_call_name(list,'FPC_OVERFLOW',false);
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a_label(list,hl);
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end;
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procedure tcgavr.g_save_registers(list: TAsmList);
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begin
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{ this is done by the entry code }
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end;
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procedure tcgavr.g_restore_registers(list: TAsmList);
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begin
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{ this is done by the exit code }
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end;
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procedure tcgavr.a_jmp_cond(list : TAsmList;cond : TOpCmp;l: tasmlabel);
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var
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ai1,ai2 : taicpu;
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hl : TAsmLabel;
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begin
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ai1:=Taicpu.Op_sym(A_BRxx,l);
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ai1.is_jmp:=true;
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hl:=nil;
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case cond of
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OC_EQ:
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ai1.SetCondition(C_EQ);
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OC_GT:
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begin
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{ emulate GT }
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current_asmdata.getjumplabel(hl);
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ai2:=Taicpu.Op_Sym(A_BRxx,hl);
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ai2.SetCondition(C_EQ);
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ai2.is_jmp:=true;
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list.concat(ai2);
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ai1.SetCondition(C_GE);
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end;
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OC_LT:
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ai1.SetCondition(C_LT);
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OC_GTE:
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ai1.SetCondition(C_GE);
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OC_LTE:
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begin
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{ emulate LTE }
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ai2:=Taicpu.Op_Sym(A_BRxx,l);
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ai2.SetCondition(C_EQ);
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ai2.is_jmp:=true;
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list.concat(ai2);
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ai1.SetCondition(C_LT);
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end;
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OC_NE:
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ai1.SetCondition(C_NE);
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OC_BE:
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begin
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{ emulate BE }
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ai2:=Taicpu.Op_Sym(A_BRxx,l);
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ai2.SetCondition(C_EQ);
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ai2.is_jmp:=true;
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list.concat(ai2);
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ai1.SetCondition(C_LO);
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end;
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OC_B:
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ai1.SetCondition(C_LO);
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OC_AE:
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ai1.SetCondition(C_SH);
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OC_A:
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begin
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{ emulate A (unsigned GT) }
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current_asmdata.getjumplabel(hl);
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ai2:=Taicpu.Op_Sym(A_BRxx,hl);
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ai2.SetCondition(C_EQ);
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ai2.is_jmp:=true;
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list.concat(ai2);
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ai1.SetCondition(C_SH);
|
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end;
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else
|
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internalerror(2011082501);
|
|
end;
|
|
list.concat(ai1);
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|
if assigned(hl) then
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|
a_label(list,hl);
|
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end;
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procedure tcgavr.g_stackpointer_alloc(list: TAsmList; size: longint);
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begin
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internalerror(201201071);
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end;
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|
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procedure tcgavr.g_intf_wrapper(list: TAsmList; procdef: tprocdef; const labelname: string; ioffset: longint);
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begin
|
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internalerror(2011021324);
|
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end;
|
|
|
|
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procedure tcgavr.emit_mov(list: TAsmList;reg2: tregister; reg1: tregister);
|
|
var
|
|
instr: taicpu;
|
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begin
|
|
instr:=taicpu.op_reg_reg(A_MOV,reg2,reg1);
|
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list.Concat(instr);
|
|
{ Notify the register allocator that we have written a move instruction so
|
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it can try to eliminate it. }
|
|
add_move_instruction(instr);
|
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end;
|
|
|
|
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procedure tcg64favr.a_op64_reg_reg(list : TAsmList;op:TOpCG;size : tcgsize;regsrc,regdst : tregister64);
|
|
begin
|
|
{ TODO : a_op64_reg_reg }
|
|
end;
|
|
|
|
|
|
procedure tcg64favr.a_op64_const_reg(list : TAsmList;op:TOpCG;size : tcgsize;value : int64;reg : tregister64);
|
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begin
|
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{ TODO : a_op64_const_reg }
|
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end;
|
|
|
|
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procedure create_codegen;
|
|
begin
|
|
cg:=tcgavr.create;
|
|
cg64:=tcg64favr.create;
|
|
end;
|
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|
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end.
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