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662 lines
22 KiB
ObjectPascal
662 lines
22 KiB
ObjectPascal
{
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$Id$
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Copyright (c) 1998-2002 by Florian Klaempfl
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Contains the base types for the SPARC
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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{ This Unit contains the base types for the PowerPC
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}
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unit cpubase;
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{$i fpcdefs.inc}
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interface
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uses
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strings,cutils,cclasses,aasmbase,cpuinfo,cgbase;
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{*****************************************************************************
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Assembler Opcodes
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*****************************************************************************}
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type
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{$WARNING CPU32 opcodes do not fully include the Ultra SPRAC instruction set.}
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{ don't change the order of these opcodes! }
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TAsmOp=({$INCLUDE opcode.inc});
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{# This should define the array of instructions as string }
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op2strtable=array[tasmop] of string[11];
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Const
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{# First value of opcode enumeration }
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firstop = low(tasmop);
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{# Last value of opcode enumeration }
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lastop = high(tasmop);
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std_op2str:op2strtable=({$INCLUDE strinst.inc});
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{*****************************************************************************
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Registers
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*****************************************************************************}
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type
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{ Number of registers used for indexing in tables }
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tregisterindex=0..{$i rspnor.inc}-1;
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totherregisterset = set of tregisterindex;
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const
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{ Available Superregisters }
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{$i rspsup.inc}
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{ No Subregisters }
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R_SUBWHOLE=R_SUBNONE;
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{ Available Registers }
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{$i rspcon.inc}
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first_int_imreg = $20;
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first_fpu_imreg = $20;
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{$warning TODO Calculate bsstart}
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regnumber_count_bsstart = 128;
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regnumber_table : array[tregisterindex] of tregister = (
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{$i rspnum.inc}
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);
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regstabs_table : array[tregisterindex] of ShortInt = (
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{$i rspstab.inc}
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);
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{*****************************************************************************
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Conditions
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*****************************************************************************}
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type
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TAsmCond=(C_None,
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C_A,C_AE,C_B,C_BE,C_C,C_E,C_G,C_GE,C_L,C_LE,C_NA,C_NAE,
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C_NB,C_NBE,C_NC,C_NE,C_NG,C_NGE,C_NL,C_NLE,C_NO,C_NP,
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C_NS,C_NZ,C_O,C_P,C_PE,C_PO,C_S,C_Z,
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C_FE,C_FG,C_FL,C_FGE,C_FLE,C_FNE
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);
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const
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cond2str:array[TAsmCond] of string[3]=('',
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'gu','cc','cs','leu','cs','e','g','ge','l','le','leu','cs',
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'cc','gu','cc','ne','le','l','ge','g','vc','XX',
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'pos','ne','vs','XX','XX','XX','vs','e',
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'e','g','l','ge','le','ne'
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);
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inverse_cond:array[TAsmCond] of TAsmCond=(C_None,
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C_NA,C_NAE,C_NB,C_NBE,C_NC,C_NE,C_NG,C_NGE,C_NL,C_NLE,C_A,C_AE,
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C_B,C_BE,C_C,C_E,C_G,C_GE,C_L,C_LE,C_O,C_P,
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C_S,C_Z,C_NO,C_NP,C_NP,C_P,C_NS,C_NZ,
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C_FNE,C_FLE,C_FGE,C_FL,C_FG,C_FE
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);
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const
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CondAsmOps=2;
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CondAsmOp:array[0..CondAsmOps-1] of TAsmOp=(
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A_Bxx,A_FBxx
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);
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CondAsmOpStr:array[0..CondAsmOps-1] of string[7]=(
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'B','FB'
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);
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{*****************************************************************************
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Flags
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*****************************************************************************}
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type
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TResFlags=(
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{ Integer results }
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F_E, {Equal}
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F_NE, {Not Equal}
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F_G, {Greater}
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F_L, {Less}
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F_GE, {Greater or Equal}
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F_LE, {Less or Equal}
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F_A, {Above}
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F_AE, {Above or Equal}
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F_B, {Below}
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F_BE, {Below or Equal}
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F_C, {Carry}
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F_NC, {Not Carry}
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{ Floating point results }
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F_FE, {Equal}
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F_FNE, {Not Equal}
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F_FG, {Greater}
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F_FL, {Less}
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F_FGE, {Greater or Equal}
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F_FLE {Less or Equal}
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);
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{*****************************************************************************
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Reference
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*****************************************************************************}
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type
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TRefOptions=(ref_none,ref_parafixup,ref_localfixup,ref_selffixup);
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{ since we have no full 32 bit offsets, we need to be able to specify the high
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and low bits of the address of a symbol }
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trefsymaddr = (refs_no,refs_full,refs_hi,refs_lo);
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{ reference record }
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preference = ^treference;
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treference = packed record
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{ base register, R_NO if none }
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base,
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{ index register, R_NO if none }
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index : tregister;
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{ offset, 0 if none }
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offset : longint;
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{ symbol this reference refers to, nil if none }
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symbol : tasmsymbol;
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{ used in conjunction with symbols and offsets: refs_full means }
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{ means a full 32bit reference, refs_hi means the upper 16 bits }
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{ and refs_lo the lower 16 bits of the address }
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symaddr : trefsymaddr;
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{ changed when inlining and possibly in other cases, don't }
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{ set manually }
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offsetfixup : longint;
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{ used in conjunction with the previous field }
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options : trefoptions;
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{ alignment this reference is guaranteed to have }
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alignment : byte;
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end;
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{ reference record }
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pparareference = ^tparareference;
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tparareference = packed record
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index : tregister;
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offset : longint;
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end;
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const
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symaddr2str: array[trefsymaddr] of string[3] = ('','','%hi','%lo');
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{*****************************************************************************
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Operand Sizes
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*****************************************************************************}
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{$ifdef dummy}
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{*****************************************************************************
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Argument Classification
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*****************************************************************************}
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type
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TArgClass = (
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{ the following classes should be defined by all processor implemnations }
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AC_NOCLASS,
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AC_MEMORY,
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AC_INTEGER,
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AC_FPU,
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{ the following argument classes are i386 specific }
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AC_FPUUP,
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AC_SSE,
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AC_SSEUP);
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{$endif dummy}
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{*****************************************************************************
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Generic Location
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*****************************************************************************}
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type
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{ tparamlocation describes where a parameter for a procedure is stored.
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References are given from the caller's point of view. The usual
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TLocation isn't used, because contains a lot of unnessary fields.
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}
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tparalocation = packed record
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size : TCGSize;
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{ The location type where the parameter is passed, usually
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LOC_REFERENCE,LOC_REGISTER or LOC_FPUREGISTER
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}
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loc : TCGLoc;
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{Word alignment on stack 4 --> 32 bit}
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Alignment:Byte;
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case TCGLoc of
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LOC_REFERENCE : (reference : tparareference; low_in_reg: boolean; lowreg : tregister);
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LOC_FPUREGISTER, LOC_CFPUREGISTER, LOC_MMREGISTER, LOC_CMMREGISTER,
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LOC_REGISTER,LOC_CREGISTER : (
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case longint of
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1 : (register,registerhigh : tregister);
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{ overlay a registerlow }
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2 : (registerlow : tregister);
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{ overlay a 64 Bit register type }
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3 : (reg64 : tregister64);
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4 : (register64 : tregister64);
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);
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end;
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treglocation = packed record
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case longint of
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1 : (register,registerhigh : tregister);
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{ overlay a registerlow }
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2 : (registerlow : tregister);
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{ overlay a 64 Bit register type }
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3 : (reg64 : tregister64);
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4 : (register64 : tregister64);
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end;
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tlocation = packed record
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size : TCGSize;
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loc : tcgloc;
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case tcgloc of
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LOC_CREFERENCE,LOC_REFERENCE : (reference : treference);
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LOC_CONSTANT : (
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case longint of
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{$ifdef FPC_BIG_ENDIAN}
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1 : (_valuedummy,value : AWord);
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{$else FPC_BIG_ENDIAN}
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1 : (value : AWord);
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{$endif FPC_BIG_ENDIAN}
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{ can't do this, this layout depends on the host cpu. Use }
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{ lo(valueqword)/hi(valueqword) instead (JM) }
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{ 2 : (valuelow, valuehigh:AWord); }
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{ overlay a complete 64 Bit value }
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3 : (valueqword : qword);
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);
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LOC_FPUREGISTER, LOC_CFPUREGISTER, LOC_MMREGISTER, LOC_CMMREGISTER,
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LOC_REGISTER,LOC_CREGISTER : (
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case longint of
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1 : (registerlow,registerhigh : tregister);
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2 : (register : tregister);
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{ overlay a 64 Bit register type }
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3 : (reg64 : tregister64);
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4 : (register64 : tregister64);
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);
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LOC_FLAGS : (resflags : tresflags);
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end;
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{*****************************************************************************
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Constants
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*****************************************************************************}
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const
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max_operands = 3;
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{# Constant defining possibly all registers which might require saving }
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ALL_OTHERREGISTERS = [];
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general_superregisters = [RS_O0..RS_I7];
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{# Table of registers which can be allocated by the code generator
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internally, when generating the code.
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}
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{ legend: }
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{ xxxregs = set of all possibly used registers of that type in the code }
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{ generator }
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{ usableregsxxx = set of all 32bit components of registers that can be }
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{ possible allocated to a regvar or using getregisterxxx (this }
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{ excludes registers which can be only used for parameter }
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{ passing on ABI's that define this) }
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{ c_countusableregsxxx = amount of registers in the usableregsxxx set }
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maxintregs = 8;
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{ to determine how many registers to use for regvars }
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maxintscratchregs = 3;
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usableregsint = [RS_L0..RS_L7];
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c_countusableregsint = 8;
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maxfpuregs = 8;
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usableregsfpu=[RS_F0..RS_F31];
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c_countusableregsfpu=32;
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mmregs = [];
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usableregsmm = [];
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c_countusableregsmm = 0;
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{ no distinction on this platform }
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maxaddrregs = 0;
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addrregs = [];
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usableregsaddr = [];
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c_countusableregsaddr = 0;
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{$warning firstsaveintreg shall be RS_NO}
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firstsaveintreg = RS_L0; { Temporary, having RS_NO is broken }
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lastsaveintreg = RS_L0; { L0..L7 are already saved, I0..O7 are parameter }
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firstsavefpureg = RS_F2; { F0..F1 is used for return value }
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lastsavefpureg = RS_F31;
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firstsavemmreg = RS_INVALID;
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lastsavemmreg = RS_INVALID;
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maxvarregs = 8;
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varregs : Array [1..maxvarregs] of Tsuperregister =
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(RS_L0,RS_L1,RS_L2,RS_L3,RS_L4,RS_L5,RS_L6,RS_L7);
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maxfpuvarregs = 1;
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fpuvarregs : Array [1..maxfpuvarregs] of TsuperRegister =
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(RS_F2);
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{
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max_param_regs_int = 6;
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param_regs_int: Array[1..max_param_regs_int] of TCpuRegister =
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(R_3,R_4,R_5,R_6,R_7,R_8,R_9,R_10);
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max_param_regs_fpu = 13;
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param_regs_fpu: Array[1..max_param_regs_fpu] of TCpuRegister =
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(R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13);
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max_param_regs_mm = 13;
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param_regs_mm: Array[1..max_param_regs_mm] of TCpuRegister =
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(R_M1,R_M2,R_M3,R_M4,R_M5,R_M6,R_M7,R_M8,R_M9,R_M10,R_M11,R_M12,R_M13);
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}
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{*****************************************************************************
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Default generic sizes
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*****************************************************************************}
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{# Defines the default address size for a processor, }
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OS_ADDR = OS_32;
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{# the natural int size for a processor, }
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OS_INT = OS_32;
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{# the maximum float size for a processor, }
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OS_FLOAT = OS_F64;
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{# the size of a vector register for a processor }
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OS_VECTOR = OS_M64;
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{*****************************************************************************
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Generic Register names
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*****************************************************************************}
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{# Stack pointer register }
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NR_STACK_POINTER_REG = NR_O6;
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RS_STACK_POINTER_REG = RS_O6;
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{# Frame pointer register }
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NR_FRAME_POINTER_REG = NR_I6;
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RS_FRAME_POINTER_REG = RS_I6;
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{# Register for addressing absolute data in a position independant way,
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such as in PIC code. The exact meaning is ABI specific. For
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further information look at GCC source : PIC_OFFSET_TABLE_REGNUM
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Taken from GCC rs6000.h
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}
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{$warning As indicated in rs6000.h, but can't find it anywhere else!}
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{PIC_OFFSET_REG = R_30;}
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{ the return_result_reg, is used inside the called function to store its return
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value when that is a scalar value otherwise a pointer to the address of the
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result is placed inside it }
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{ Results are returned in this register (32-bit values) }
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NR_FUNCTION_RETURN_REG = NR_I0;
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RS_FUNCTION_RETURN_REG = RS_I0;
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{ Low part of 64bit return value }
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NR_FUNCTION_RETURN64_LOW_REG = NR_I1;
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RS_FUNCTION_RETURN64_LOW_REG = RS_I1;
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{ High part of 64bit return value }
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NR_FUNCTION_RETURN64_HIGH_REG = NR_I0;
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RS_FUNCTION_RETURN64_HIGH_REG = RS_I0;
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{ The value returned from a function is available in this register }
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NR_FUNCTION_RESULT_REG = NR_O0;
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RS_FUNCTION_RESULT_REG = RS_O0;
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{ The lowh part of 64bit value returned from a function }
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NR_FUNCTION_RESULT64_LOW_REG = NR_O1;
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RS_FUNCTION_RESULT64_LOW_REG = RS_O1;
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{ The high part of 64bit value returned from a function }
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NR_FUNCTION_RESULT64_HIGH_REG = NR_O0;
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RS_FUNCTION_RESULT64_HIGH_REG = RS_O0;
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NR_FPU_RESULT_REG = NR_F0;
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NR_MM_RESULT_REG = NR_NO;
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PARENT_FRAMEPOINTER_OFFSET = 68; { o0 }
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{*****************************************************************************
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GCC /ABI linking information
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*****************************************************************************}
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{# Registers which must be saved when calling a routine declared as
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cppdecl, cdecl, stdcall, safecall, palmossyscall. The registers
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saved should be the ones as defined in the target ABI and / or GCC.
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This value can be deduced from CALLED_USED_REGISTERS array in the
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GCC source.
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}
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std_saved_registers = [];
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{# Required parameter alignment when calling a routine declared as
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stdcall and cdecl. The alignment value should be the one defined
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by GCC or the target ABI.
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The value of this constant is equal to the constant
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PARM_BOUNDARY / BITS_PER_UNIT in the GCC source.
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}
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std_param_align = 4; { for 32-bit version only }
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{*****************************************************************************
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CPU Dependent Constants
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*****************************************************************************}
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const
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simm13lo=-4096;
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simm13hi=4095;
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{*****************************************************************************
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Helpers
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*****************************************************************************}
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function is_calljmp(o:tasmop):boolean;
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procedure inverse_flags(var f: TResFlags);
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function flags_to_cond(const f: TResFlags) : TAsmCond;
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function cgsize2subreg(s:Tcgsize):Tsubregister;
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function std_regname(r:Tregister):string;
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function std_regnum_search(const s:string):Tregister;
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function findreg_by_number(r:Tregister):tregisterindex;
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implementation
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uses
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rgBase,verbose;
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const
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std_regname_table : TRegNameTAble = (
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{$i rspstd.inc}
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);
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regnumber_index : TRegisterIndexTable = (
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{$i rsprni.inc}
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);
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std_regname_index : TRegisterIndexTable = (
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{$i rspsri.inc}
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);
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{*****************************************************************************
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Helpers
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*****************************************************************************}
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function is_calljmp(o:tasmop):boolean;
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const
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CallJmpOp=[A_JMPL..A_CBccc];
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begin
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is_calljmp:=(o in CallJmpOp);
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end;
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procedure inverse_flags(var f: TResFlags);
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const
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inv_flags: array[TResFlags] of TResFlags =
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(F_NE,F_E,F_LE,F_GE,F_L,F_G,F_BE,F_B,F_AE,F_A,F_NC,F_C,
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F_FNE,F_FE,F_FLE,F_FGE,F_FL,F_FG);
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begin
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f:=inv_flags[f];
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end;
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function flags_to_cond(const f:TResFlags):TAsmCond;
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const
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flags_2_cond:array[TResFlags] of TAsmCond=
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(C_E,C_NE,C_G,C_L,C_GE,C_LE,C_A,C_AE,C_B,C_BE,C_C,C_NC,
|
|
C_FE,C_FNE,C_FG,C_FL,C_FGE,C_FLE);
|
|
begin
|
|
result:=flags_2_cond[f];
|
|
end;
|
|
|
|
|
|
function cgsize2subreg(s:Tcgsize):Tsubregister;
|
|
begin
|
|
cgsize2subreg:=R_SUBWHOLE;
|
|
end;
|
|
|
|
|
|
function std_regname(r:Tregister):string;
|
|
var
|
|
p : tregisterindex;
|
|
begin
|
|
p:=findreg_by_number_table(r,regnumber_index);
|
|
if p<>0 then
|
|
result:=std_regname_table[p]
|
|
else
|
|
result:=generic_regname(r);
|
|
end;
|
|
|
|
|
|
function std_regnum_search(const s:string):Tregister;
|
|
begin
|
|
result:=regnumber_table[findreg_by_name_table(s,std_regname_table,std_regname_index)];
|
|
end;
|
|
|
|
|
|
function findreg_by_number(r:Tregister):tregisterindex;
|
|
begin
|
|
result:=findreg_by_number_table(r,regnumber_index);
|
|
end;
|
|
|
|
|
|
end.
|
|
{
|
|
$Log$
|
|
Revision 1.60 2004-01-12 22:11:39 peter
|
|
* use localalign info for alignment for locals and temps
|
|
* sparc fpu flags branching added
|
|
* moved powerpc copy_valye_openarray to generic
|
|
|
|
Revision 1.59 2004/01/12 16:39:40 peter
|
|
* sparc updates, mostly float related
|
|
|
|
Revision 1.58 2003/12/19 14:38:03 mazen
|
|
* new TRegister definition applied
|
|
|
|
Revision 1.57 2003/11/10 19:05:50 peter
|
|
* fixed alias/colouring > 255
|
|
|
|
Revision 1.56 2003/11/01 19:27:54 peter
|
|
* 1.9.0
|
|
|
|
Revision 1.55 2003/10/31 08:47:13 mazen
|
|
* rgHelper renamed to rgBase
|
|
* using findreg_by_<name|number>_table directly to decrease heap overheading
|
|
|
|
Revision 1.54 2003/10/30 15:03:18 mazen
|
|
* now uses standard routines in rgBase unit to search registers by number and by name
|
|
|
|
Revision 1.53 2003/10/08 14:11:36 mazen
|
|
+ Alignement field added to TParaLocation (=4 as 32 bits archs)
|
|
|
|
Revision 1.52 2003/10/01 20:34:50 peter
|
|
* procinfo unit contains tprocinfo
|
|
* cginfo renamed to cgbase
|
|
* moved cgmessage to verbose
|
|
* fixed ppc and sparc compiles
|
|
|
|
Revision 1.51 2003/09/14 21:35:15 peter
|
|
* new volatile registers proc
|
|
|
|
Revision 1.50 2003/09/14 19:19:05 peter
|
|
* updates for new ra
|
|
|
|
Revision 1.49 2003/09/03 16:29:37 peter
|
|
* superregisters also from .dat file
|
|
|
|
Revision 1.48 2003/09/03 15:55:01 peter
|
|
* NEWRA branch merged
|
|
|
|
Revision 1.47.2.3 2003/09/02 17:49:17 peter
|
|
* newra updates
|
|
|
|
Revision 1.47.2.2 2003/09/01 21:02:55 peter
|
|
* sparc updates for new tregister
|
|
|
|
Revision 1.47.2.1 2003/08/31 21:08:16 peter
|
|
* first batch of sparc fixes
|
|
|
|
Revision 1.47 2003/08/19 13:22:51 mazen
|
|
+ implemented gas_regname based on convert_register_to_enum std_Reg2str
|
|
|
|
Revision 1.46 2003/08/17 16:59:20 jonas
|
|
* fixed regvars so they work with newra (at least for ppc)
|
|
* fixed some volatile register bugs
|
|
+ -dnotranslation option for -dnewra, which causes the registers not to
|
|
be translated from virtual to normal registers. Requires support in
|
|
the assembler writer as well, which is only implemented in aggas/
|
|
agppcgas currently
|
|
|
|
Revision 1.45 2003/07/06 17:58:22 peter
|
|
* framepointer fixes for sparc
|
|
* parent framepointer code more generic
|
|
|
|
Revision 1.44 2003/07/02 22:18:04 peter
|
|
* paraloc splitted in callerparaloc,calleeparaloc
|
|
* sparc calling convention updates
|
|
|
|
Revision 1.43 2003/06/17 16:34:44 jonas
|
|
* lots of newra fixes (need getfuncretparaloc implementation for i386)!
|
|
* renamed all_intregisters to volatile_intregisters and made it
|
|
processor dependent
|
|
|
|
Revision 1.42 2003/06/13 21:08:30 peter
|
|
* supreg_name added
|
|
|
|
Revision 1.41 2003/06/12 19:11:34 jonas
|
|
- removed ALL_INTREGISTERS (only the one in rgobj is valid)
|
|
|
|
Revision 1.40 2003/06/04 21:00:54 mazen
|
|
- making TOldRegister only declared for compatibility and
|
|
no more used in cpubase
|
|
|
|
Revision 1.39 2003/06/01 21:38:06 peter
|
|
* getregisterfpu size parameter added
|
|
* op_const_reg size parameter added
|
|
* sparc updates
|
|
|
|
Revision 1.38 2003/06/01 01:04:35 peter
|
|
* reference fixes
|
|
|
|
Revision 1.37 2003/05/31 15:05:28 peter
|
|
* FUNCTION_RESULT64_LOW/HIGH_REG added for int64 results
|
|
|
|
Revision 1.36 2003/05/31 01:00:51 peter
|
|
* register fixes
|
|
|
|
Revision 1.35 2003/05/30 23:57:08 peter
|
|
* more sparc cleanup
|
|
* accumulator removed, splitted in function_return_reg (called) and
|
|
function_result_reg (caller)
|
|
|
|
}
|