marco 2578514853 * first dragonfly patch (existing most). Mantis #27091 ... git-svn-id: trunk@29213 -		2014-12-07 20:27:02 +00:00
..
aoptcpu.pas
aoptcpub.pas
aoptcpud.pas
cgcpu.pas	* handle the fact that records containing a single extended value are	2014-11-04 21:16:27 +00:00
cpubase.inc
cpuelf.pas	* first dragonfly patch (existing most). Mantis #27091	2014-12-07 20:27:02 +00:00
cpuinfo.pas	+ change always floating point divisions into multiplications if they are a power of two,	2014-11-16 20:47:38 +00:00
cpunode.pas
cpupara.pas	* handle the fact that records containing a single extended value are	2014-11-04 21:16:27 +00:00
cpupi.pas
cputarg.pas
hlcgcpu.pas
nx64add.pas
nx64cal.pas
nx64cnv.pas
nx64flw.pas
nx64inl.pas
nx64mat.pas
nx64set.pas
r8664ari.inc
r8664att.inc
r8664con.inc
r8664dwrf.inc
r8664int.inc
r8664iri.inc
r8664nasm.inc
r8664nor.inc
r8664num.inc
r8664ot.inc
r8664rni.inc
r8664sri.inc
r8664stab.inc
r8664std.inc
rax64att.pas	- Forgot to commit with r29081	2014-11-16 17:29:52 +00:00
rax64int.pas
rgcpu.pas
symcpu.pas	* reimplemented r28329 in a different way, as suggested by Jonas	2014-08-07 19:36:52 +00:00
win64unw.pas
x8664ats.inc	* x86: Completely skip instructions that do not exist for target CPU bit width. The existing behavior of writing mnemonics and properties but no encoding allows an invalid instruction to be recognized by assembler reader or even generated by compiler, but it but won't assemble anyway.	2014-06-11 22:31:40 +00:00
x8664att.inc	* x86: Completely skip instructions that do not exist for target CPU bit width. The existing behavior of writing mnemonics and properties but no encoding allows an invalid instruction to be recognized by assembler reader or even generated by compiler, but it but won't assemble anyway.	2014-06-11 22:31:40 +00:00
x8664int.inc	* x86: Completely skip instructions that do not exist for target CPU bit width. The existing behavior of writing mnemonics and properties but no encoding allows an invalid instruction to be recognized by assembler reader or even generated by compiler, but it but won't assemble anyway.	2014-06-11 22:31:40 +00:00
x8664nop.inc
x8664op.inc	* x86: Completely skip instructions that do not exist for target CPU bit width. The existing behavior of writing mnemonics and properties but no encoding allows an invalid instruction to be recognized by assembler reader or even generated by compiler, but it but won't assemble anyway.	2014-06-11 22:31:40 +00:00
x8664pro.inc	* x86: Completely skip instructions that do not exist for target CPU bit width. The existing behavior of writing mnemonics and properties but no encoding allows an invalid instruction to be recognized by assembler reader or even generated by compiler, but it but won't assemble anyway.	2014-06-11 22:31:40 +00:00
x8664tab.inc