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798 lines
14 KiB
Plaintext
798 lines
14 KiB
Plaintext
;
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; Table of assembler instructions for Free Pascal
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; adapted from Netwide Assembler by Florian Klaempfl
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;
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;
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; The Netwide Assembler is copyright (C) 1996 Simon Tatham and
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; Julian Hall. All rights reserved. The software is
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; redistributable under the licence given in the file "Licence"
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; distributed in the NASM archive.
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;
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; Format of file: all four fields must be present on every functional
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; line. Hence `void' for no-operand instructions, and `\0' for such
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; as EQU. If the last three fields are all `ignore', no action is
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; taken except to register the opcode as being present.
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;
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;
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; 'ignore' means no instruc
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; 'void' means instruc with zero operands
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;
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; Third field has a first byte indicating how to
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; put together the bits, and then some codes
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; that may be used at will (see assemble.c)
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;
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; \1 - 24 bit pc-rel offset [B, BL]
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; \2 - 24 bit imm value [SWI]
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; \3 - 3 byte code [BX]
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;
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; \4 - reg,reg,reg [AND,EOR,SUB,RSB,ADD,ADC,SBC,RSC,ORR,BIC]
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; \5 - reg,reg,reg,<shift>reg [-"-]
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; \6 - reg,reg,reg,<shift>#imm [-"-]
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; \7 - reg,reg,#imm [-"-]
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;
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; \x8 - reg,reg [MOV,MVN]
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; \x9 - reg,reg,<shift>reg [-"-]
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; \xA - reg,reg,<shift>#imm [-"-]
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; \xB - reg,#imm [-"-]
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;
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; \xC - reg,reg [CMP,CMN,TEQ,TST]
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; \xD - reg,reg,<shift>reg [-"-]
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; \xE - reg,reg,<shift>#imm [-"-]
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; \xF - reg,#imm [-"-]
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;
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; \xFx - floating point instructions
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; Floating point instruction format information, taken from the linux kernel,
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; for detailed tables, see aasmcpu.pas
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;
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; ARM Floating Point Instruction Classes
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; | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
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; |c o n d|1 1 0 P|U|u|W|L| Rn |v| Fd |0|0|0|1| o f f s e t | CPDT
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; |c o n d|1 1 0 P|U|w|W|L| Rn |x| Fd |0|0|1|0| o f f s e t | CPDT (copro 2)
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; | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
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; |c o n d|1 1 1 0|a|b|c|d|e| Fn |j| Fd |0|0|0|1|f|g|h|0|i| Fm | CPDO
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; |c o n d|1 1 1 0|a|b|c|L|e| Fn | Rd |0|0|0|1|f|g|h|1|i| Fm | CPRT
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; |c o n d|1 1 1 0|a|b|c|1|e| Fn |1|1|1|1|0|0|0|1|f|g|h|1|i| Fm | comparisons
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; | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
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;
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; CPDT data transfer instructions
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; LDF, STF, LFM (copro 2), SFM (copro 2)
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;
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; CPDO dyadic arithmetic instructions
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; ADF, MUF, SUF, RSF, DVF, RDF,
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; POW, RPW, RMF, FML, FDV, FRD, POL
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;
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; CPDO monadic arithmetic instructions
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; MVF, MNF, ABS, RND, SQT, LOG, LGN, EXP,
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; SIN, COS, TAN, ASN, ACS, ATN, URD, NRM
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;
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; CPRT joint arithmetic/data transfer instructions
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; FIX (arithmetic followed by load/store)
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; FLT (load/store followed by arithmetic)
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; CMF, CNF CMFE, CNFE (comparisons)
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; WFS, RFS (write/read floating point status register)
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; WFC, RFC (write/read floating point control register)
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; \xF0 - CPDT
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; code 1: copro (1/2)
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; code 2: load/store bit
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; \xF1 - CPDO
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; \xF2 - CPDO monadic
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; \xF3 - CPRT
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; \xF4 - CPRT comparison
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;
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; \xFF - fix me
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;
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[NONE]
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void void none
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[ABScc]
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[ACScc]
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[ASNcc]
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[ATNcc]
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[ADCcc]
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reg32,reg32,reg32 \4\x0\xA0 ARM7
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reg32,reg32,reg32,reg32 \5\x0\xA0 ARM7
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reg32,reg32,reg32,imm \6\x0\xA0 ARM7
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reg32,reg32,imm \7\x2\xA0 ARM7
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[ADDcc]
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reg32,reg32,reg32 \4\x0\x80 ARM7
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reg32,reg32,reg32,reg32 \5\x0\x80 ARM7
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reg32,reg32,reg32,imm \6\x0\x80 ARM7
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reg32,reg32,imm \7\x2\x80 ARM7
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[ADFcc]
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[ADRcc]
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[ANDcc]
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reg32,reg32,reg32 \4\x0\x00 ARM7
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reg32,reg32,reg32,reg32 \5\x0\x00 ARM7
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reg32,reg32,reg32,imm \6\x0\x00 ARM7
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reg32,reg32,imm \7\x2\x00 ARM7
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[Bcc]
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mem32 \1\x0A ARM7
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imm24 \1\x0A ARM7
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[BICcc]
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reg32,reg32,reg32 \4\x1\xC0 ARM7
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reg32,reg32,reg32,reg32 \5\x1\xC0 ARM7
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reg32,reg32,reg32,imm \6\x1\xC0 ARM7
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reg32,reg32,imm \7\x3\xC0 ARM7
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[BLcc]
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mem32 \1\x0B ARM7
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imm24 \1\x0B ARM7
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[BLX]
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mem32 \xff ARM7
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imm24 \xff ARM7
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[BKPTcc]
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[BXcc]
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reg32 \3\x01\x2F\xFF\x10 ARM7
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[CDP]
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reg8,reg8 \300\1\x10\101 ARM7
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[CMFcc]
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[CMFEcc]
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[CMNcc]
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reg32,reg32 \xC\x1\x60 ARM7
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reg32,reg32,reg32 \xD\x1\x60 ARM7
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reg32,reg32,imm \xE\x1\x60 ARM7
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reg32,imm \xF\x3\x60 ARM7
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[CMPcc]
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reg32,reg32 \xC\x1\x40 ARM7
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reg32,reg32,reg32 \xD\x1\x40 ARM7
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reg32,reg32,imm \xE\x1\x40 ARM7
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reg32,imm \xF\x3\x40 ARM7
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[CLZcc]
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reg32,reg32 \x27\x01\x01 ARM7
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[CNFcc]
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[COScc]
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[CPS]
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[CPSID]
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[CPSIE]
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[DVFcc]
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[EORcc]
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reg32,reg32,reg32 \4\x0\x20 ARM7
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reg32,reg32,reg32,reg32 \5\x0\x20 ARM7
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reg32,reg32,reg32,imm \6\x0\x20 ARM7
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reg32,reg32,imm \7\x2\x20 ARM7
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[EXPcc]
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[FDVcc]
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[FLTcc]
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[FIXcc]
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[FMLcc]
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[FRDcc]
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[LDC]
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reg32,reg32 \321\300\1\x11\101 ARM7
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[LDMcc]
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memam4,reglist \x26\x81 ARM7
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[LDRBTcc]
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[LDRBcc]
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reg32,memam2 \x17\x07\x10 ARM7
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[LDRcc]
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reg32,memam2 \x17\x05\x10 ARM7
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; reg32,imm32 \x17\x05\x10 ARM7
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; reg32,reg32 \x18\x04\x10 ARM7
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; reg32,reg32,imm32 \x19\x04\x10 ARM7
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; reg32,reg32,reg32 \x20\x06\x10 ARM7
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; reg32,reg32,reg32,imm32 \x21\x06\x10 ARM7
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[LDRHcc]
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reg32,imm32 \x22\x50\xB0 ARM7
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reg32,reg32 \x23\x50\xB0 ARM7
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reg32,reg32,imm32 \x24\x50\xB0 ARM7
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reg32,reg32,reg32 \x25\x10\xB0 ARM7
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[LDRSBcc]
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reg32,imm32 \x22\x50\xD0 ARM7
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reg32,reg32 \x23\x50\xD0 ARM7
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reg32,reg32,imm32 \x24\x50\xD0 ARM7
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reg32,reg32,reg32 \x25\x10\xD0 ARM7
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[LDRSHcc]
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reg32,imm32 \x22\x50\xF0 ARM7
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reg32,reg32 \x23\x50\xF0 ARM7
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reg32,reg32,imm32 \x24\x50\xF0 ARM7
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reg32,reg32,reg32 \x25\x10\xF0 ARM7
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[LDRTcc]
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[LDFcc]
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[LFMcc]
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reg32,imm8,fpureg \xF0\x02\x01 FPA
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[LGNcc]
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[LOGcc]
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[MCR]
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; reg32,mem32 \320\301\1\x13\110 ARM7
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[MLAcc]
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reg32,reg32,reg32,reg32 \x15\x00\x20\x90 ARM7
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[MOVcc]
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; reg32,shifterop \x8\x0\0xd ARM7
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; reg32,immshifter \x8\x0\0xd ARM7
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; reg32,reg32,reg32 \x9\x1\xA0 ARM7
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; reg32,reg32,imm \xA\x1\xA0 ARM7
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; reg32,imm \xB\x3\xA0 ARM7
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[MRC]
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; reg32,reg32 \321\301\1\x13\110 ARM7
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[MRScc]
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reg32,reg32 \x10\x01\x0F ARM7
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[MSRcc]
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reg32,reg32 \x11\x01\x29\xF0 ARM7
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regf,reg32 \x12\x01\x28\xF0 ARM7
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regf,imm \x13\x03\x28\xF0 ARM7
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[MNFcc]
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[MUFcc]
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[MULcc]
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reg32,reg32,reg32 \x14\x00\x00\x90 ARM7
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[MVFcc]
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fpureg,fpureg \xF2 FPA
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fpureg,immfpu \xF2 FPA
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[MVNcc]
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; reg32,reg32 \x8\x0\0xf ARM7
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; reg32,reg32,reg32 \x9\x1\xE0 ARM7
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; reg32,reg32,imm \xA\x1\xE0 ARM7
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; reg32,imm \xB\x3\xE0 ARM7
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[NOP]
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[ORRcc]
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reg32,reg32,reg32 \4\x1\x80 ARM7
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reg32,reg32,reg32,reg32 \5\x1\x80 ARM7
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reg32,reg32,reg32,imm \6\x1\x80 ARM7
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reg32,reg32,imm \7\x3\x80 ARM7
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[RDFcc]
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[RFScc]
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[RFCcc]
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[RMFcc]
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[RPWcc]
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[RSBcc]
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reg32,reg32,reg32 \4\x0\x60 ARM7
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reg32,reg32,reg32,reg32 \5\x0\x60 ARM7
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reg32,reg32,reg32,imm \6\x0\x60 ARM7
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reg32,reg32,imm \7\x2\x60 ARM7
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[RSCcc]
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reg32,reg32,reg32 \4\x0\xE0 ARM7
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reg32,reg32,reg32,reg32 \5\x0\xE0 ARM7
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reg32,reg32,reg32,imm \6\x0\xE0 ARM7
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reg32,reg32,imm \7\x2\xE0 ARM7
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[RSFcc]
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[RNDcc]
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[POLcc]
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[SBCcc]
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reg32,reg32,reg32 \4\x0\xC0 ARM7
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reg32,reg32,reg32,reg32 \5\x0\xC0 ARM7
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reg32,reg32,reg32,imm \6\x0\xC0 ARM7
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reg32,reg32,imm \7\x2\xC0 ARM7
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[SFMcc]
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reg32,imm8,fpureg \xF0\x02\x00 FPA
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[SINcc]
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[SMLALcc]
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reg32,reg32,reg32,reg32 \x16\x00\xE0\x90 ARM7
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[SMULLcc]
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reg32,reg32,reg32,reg32 \x16\x00\xC0\x90 ARM7
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[SQTcc]
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[SUFcc]
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[STFcc]
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[STMcc]
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memam4,reglist \x26\x80 ARM7
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[STRcc]
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reg32,memam2 \x17\x04\x00 ARM7
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; reg32,imm32 \x17\x05\x00 ARM7
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; reg32,reg32 \x18\x04\x00 ARM7
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; reg32,reg32,imm32 \x19\x04\x00 ARM7
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; reg32,reg32,reg32 \x20\x06\x00 ARM7
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; reg32,reg32,reg32,imm32 \x21\x06\x00 ARM7
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[STRBcc]
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reg32,memam2 \x17\x06\x00 ARM7
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[STRBTcc]
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; A dummy since it is parsed as STR{cond}H
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[STRHcc]
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reg32,imm32 \x22\x40\xB0 ARM7
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reg32,reg32 \x23\x40\xB0 ARM7
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reg32,reg32,imm32 \x24\x40\xB0 ARM7
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reg32,reg32,reg32 \x25\x00\xB0 ARM7
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[STRTcc]
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[SUBcc]
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reg32,reg32,shifterop \4\x0\x40 ARM7
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reg32,reg32,immshifter \4\x0\x40 ARM7
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reg32,reg32,reg32 \4\x0\x40 ARM7
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; reg32,reg32,reg32,reg32 \5\x0\x40 ARM7
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; reg32,reg32,reg32,imm \6\x0\x40 ARM7
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; reg32,reg32,imm \7\x2\x40 ARM7
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[SWIcc]
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imm \2\x0F ARM7
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[SWPcc]
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reg32,reg32,reg32 \x27\x01\x90 ARM7
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[SWPBcc]
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reg32,reg32,reg32 \x27\x01\x90 ARM7
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[TANcc]
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[TEQcc]
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reg32,reg32 \xC\x1\x20 ARM7
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reg32,reg32,reg32 \xD\x1\x20 ARM7
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reg32,reg32,imm \xE\x1\x20 ARM7
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reg32,imm \xF\x3\x20 ARM7
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[TSTcc]
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reg32,reg32 \xC\x1\x00 ARM7
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reg32,reg32,reg32 \xD\x1\x00 ARM7
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reg32,reg32,imm \xE\x1\x00 ARM7
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reg32,imm \xF\x3\x00 ARM7
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[UMLALcc]
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reg32,reg32,reg32,reg32 \x16\x00\xA0\x90 ARM7
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[UMULLcc]
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reg32,reg32,reg32,reg32 \x16\x00\x80\x90 ARM7
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[WFScc]
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; EDSP instructions
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[LDRDcc]
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[MCRRcc]
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[MRRCcc]
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[PLD]
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[QADDcc]
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[QDADDcc]
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[QDSUBcc]
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[QSUBcc]
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[SMLABBcc]
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[SMLABTcc]
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[SMLATBcc]
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[SMLATTcc]
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[SMLALBBcc]
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[SMLALBTcc]
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[SMLALTBcc]
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[SMLALTTcc]
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[SMLAWBcc]
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[SMLAWTcc]
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[SMULBBcc]
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[SMULBTcc]
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[SMULTBcc]
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[SMULTTcc]
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[SMULWBcc]
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[SMULWTcc]
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[STRDcc]
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;
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; vfp instructions
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;
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[FABSDcc]
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[FABSScc]
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[FADDDcc]
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[FADDScc]
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[FCMPDcc]
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[FCMPEDcc]
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[FCMPEScc]
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[FCMPEZDcc]
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[FCMPEZScc]
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[FCMPScc]
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[FCMPZDcc]
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[FCMPZScc]
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[FCPYDcc]
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[FCPYScc]
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[FCVTDScc]
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[FCVTSDcc]
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[FDIVDcc]
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[FDIVScc]
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[FLDDcc]
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[FLDMcc]
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[FLDScc]
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[FMACDcc]
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[FMACScc]
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[FMDHRcc]
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[FMDLRcc]
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[FMRDHcc]
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[FMRDLcc]
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[FMRScc]
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[FMRXcc]
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[FMSCDcc]
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[FMSCScc]
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[FMSRcc]
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[FMSTATcc]
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[FMULDcc]
|
|
|
|
[FMULScc]
|
|
|
|
[FMXRcc]
|
|
|
|
[FNEGDcc]
|
|
|
|
[FNEGScc]
|
|
|
|
[FNMACDcc]
|
|
|
|
[FNMACScc]
|
|
|
|
[FNMSCDcc]
|
|
|
|
[FNMSCScc]
|
|
|
|
[FNMULDcc]
|
|
|
|
[FNMULScc]
|
|
|
|
[FSITODcc]
|
|
|
|
[FSITOScc]
|
|
|
|
[FSQRTDcc]
|
|
|
|
[FSQRTScc]
|
|
|
|
[FSTDcc]
|
|
|
|
[FSTMcc]
|
|
|
|
[FSTScc]
|
|
|
|
[FSUBDcc]
|
|
|
|
[FSUBScc]
|
|
|
|
[FTOSIDcc]
|
|
|
|
[FTOSIScc]
|
|
|
|
[FTOUIDcc]
|
|
|
|
[FTOUIScc]
|
|
|
|
[FUITODcc]
|
|
|
|
[FUITOScc]
|
|
|
|
[FMDRRcc]
|
|
|
|
[FMRRDcc]
|
|
|
|
; ARMv6
|
|
|
|
[BFCcc]
|
|
|
|
[BFIcc]
|
|
|
|
[CLREX]
|
|
|
|
[LDREXcc]
|
|
[LDREXBcc]
|
|
[LDREXDcc]
|
|
[LDREXHcc]
|
|
|
|
[MLScc]
|
|
|
|
[PKHcc]
|
|
|
|
[PLI]
|
|
|
|
[QADD16cc]
|
|
[QADD8cc]
|
|
[QASXcc]
|
|
[QSAXcc]
|
|
[QSUB16cc]
|
|
[QSUB8cc]
|
|
|
|
[RBITcc]
|
|
|
|
[REVcc]
|
|
[REV16cc]
|
|
[REVSHcc]
|
|
|
|
[SADD16cc]
|
|
[SADD8cc]
|
|
[SASXcc]
|
|
|
|
[SBFXcc]
|
|
|
|
[SELcc]
|
|
|
|
[SETEND]
|
|
|
|
[SEVcc]
|
|
|
|
[ASRcc]
|
|
|
|
[LSRcc]
|
|
|
|
[LSLcc]
|
|
|
|
[RORcc]
|
|
|
|
[SHADD16cc]
|
|
[SHADD8cc]
|
|
[SHASXcc]
|
|
[SHSAXcc]
|
|
[SHSUB16cc]
|
|
[SHSUB8cc]
|
|
|
|
[SMLADcc]
|
|
[SMLALDcc]
|
|
[SMLSDcc]
|
|
[SMLSLDcc]
|
|
[SMMLAcc]
|
|
[SMMLScc]
|
|
[SMMULcc]
|
|
[SMUADcc]
|
|
[SMUSDcc]
|
|
|
|
[SRScc]
|
|
|
|
[SSATcc]
|
|
[SSAT16cc]
|
|
[SSAXcc]
|
|
|
|
[SSUB16cc]
|
|
[SSUB8cc]
|
|
|
|
[STREXcc]
|
|
[STREXBcc]
|
|
[STREXDcc]
|
|
[STREXHcc]
|
|
|
|
[SXTABcc]
|
|
[SXTAB16cc]
|
|
[SXTAHcc]
|
|
[SXTBcc]
|
|
[SXTB16cc]
|
|
|
|
[UXTBcc]
|
|
[UXTHcc]
|
|
|
|
[SXTHcc]
|
|
|
|
[UADD16cc]
|
|
[UADD8cc]
|
|
[UASXcc]
|
|
|
|
[UBFXcc]
|
|
|
|
[UHADD16cc]
|
|
[UHADD8cc]
|
|
[UHASXcc]
|
|
[UHSAXcc]
|
|
[UHSUB16cc]
|
|
[UHSUB8cc]
|
|
|
|
[UMAALcc]
|
|
|
|
[UQADD16cc]
|
|
[UQADD8]
|
|
[UQASXcc]
|
|
[UQSAXcc]
|
|
|
|
[UQSUB16cc]
|
|
[UQSUB8cc]
|
|
[UQSAD8cc]
|
|
[UQSADA8cc]
|
|
|
|
[USATcc]
|
|
[USAT16cc]
|
|
[USAXcc]
|
|
|
|
[USUB16cc]
|
|
[USUB8cc]
|
|
|
|
[UXTABcc]
|
|
[UXTAB16cc]
|
|
[UXTAHcc]
|
|
[UXTB16cc]
|
|
|
|
[WFEcc]
|
|
[WFIcc]
|
|
[YIELDcc]
|
|
|
|
; Thumb-2
|
|
|
|
[POP]
|
|
|
|
[PUSH]
|
|
|
|
[SDIVcc]
|
|
|
|
[UDIVcc]
|
|
|
|
[MOVTcc]
|
|
|
|
[IT]
|
|
|
|
[ITE]
|
|
|
|
[ITT]
|
|
|
|
[ITEE]
|
|
|
|
[ITTE]
|
|
|
|
[ITET]
|
|
|
|
[ITTT]
|
|
|
|
[ITEEE]
|
|
|
|
[ITTEE]
|
|
|
|
[ITETE]
|
|
|
|
[ITTTE]
|
|
|
|
[ITEET]
|
|
|
|
[ITTET]
|
|
|
|
[ITETT]
|
|
|
|
[ITTTT]
|
|
|
|
[TBB]
|
|
[TBH]
|
|
|
|
[MOVW]
|
|
|
|
[CBZ]
|
|
[CBNZ]
|
|
|
|
; FPv4-s16 - ARMv7M floating point
|
|
[VABS]
|
|
[VADD]
|
|
[VCMP]
|
|
[VCMPE]
|
|
[VCVT]
|
|
[VDIV]
|
|
[VLDM]
|
|
[VLDR]
|
|
[VMOV]
|
|
[VMRS]
|
|
[VMSR]
|
|
[VMUL]
|
|
[VMLA]
|
|
[VMLS]
|
|
[VNMLA]
|
|
[VNMLS]
|
|
[VFMA]
|
|
[VFMS]
|
|
[VFNMA]
|
|
[VFNMS]
|
|
[VNEG]
|
|
[VNMUL]
|
|
[VPOP]
|
|
[VPUSH]
|
|
[VSQRT]
|
|
[VSTM]
|
|
[VSTR]
|
|
[VSUB]
|
|
|
|
; Thumb armv6-m (gcc)
|
|
[NEG]
|
|
[SVC]
|
|
|