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592df7fa59
that itself, our LLVM code generator can't handle it, and if it did then
afterwards we would have to spill 90% of those register variables again
to make them SSA)
git-svn-id: trunk@44062 -
128 lines
3.8 KiB
ObjectPascal
128 lines
3.8 KiB
ObjectPascal
{
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Copyright (c) 1998-2002 by the Free Pascal development team
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Basic Processor information for AArch64
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See the file COPYING.FPC, included in this distribution,
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for details about the copyright.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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**********************************************************************}
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Unit CPUInfo;
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{$i fpcdefs.inc}
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Interface
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uses
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globtype;
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Type
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bestreal = double;
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{$if FPC_FULLVERSION>20700}
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bestrealrec = TDoubleRec;
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{$endif FPC_FULLVERSION>20700}
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ts32real = single;
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ts64real = double;
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ts80real = type extended;
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ts128real = type extended;
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ts64comp = comp;
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pbestreal=^bestreal;
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{ possible supported processors for this target }
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tcputype =
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(cpu_none,
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cpu_armv8
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);
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Type
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tfputype =
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(fpu_none,
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fpu_vfp
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);
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tcontrollertype =
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(ct_none
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);
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tcontrollerdatatype = record
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controllertypestr, controllerunitstr: string[20];
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cputype: tcputype; fputype: tfputype;
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flashbase, flashsize, srambase, sramsize, eeprombase, eepromsize, bootbase, bootsize: dword;
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end;
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Const
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fputypestrllvm : array[tfputype] of string[6] = ('',
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''
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);
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{ Is there support for dealing with multiple microcontrollers available }
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{ for this platform? }
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ControllerSupport = false; (* Not yet at least ;-) *)
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{# Size of native extended floating point type }
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extended_size = 8;
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{ target cpu string (used by compiler options) }
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target_cpu_string = 'aarch64';
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{ We know that there are fields after sramsize
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but we don't care about this warning }
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{$PUSH}
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{$WARN 3177 OFF}
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embedded_controllers : array [tcontrollertype] of tcontrollerdatatype =
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(
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(controllertypestr:''; controllerunitstr:''; cputype:cpu_none; fputype:fpu_none; flashbase:0; flashsize:0; srambase:0; sramsize:0));
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{$POP}
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{ calling conventions supported by the code generator }
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supported_calling_conventions : tproccalloptions = [
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pocall_internproc,
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pocall_safecall,
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pocall_stdcall,
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{ same as stdcall only different name mangling }
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pocall_cdecl,
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{ same as stdcall only different name mangling }
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pocall_cppdecl,
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{ same as stdcall but floating point numbers are handled like equal sized integers }
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pocall_softfloat,
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{ same as stdcall (requires that all const records are passed by
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reference, but that's already done for stdcall) }
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pocall_mwpascal,
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{ used for interrupt handling }
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pocall_interrupt
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];
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cputypestr : array[tcputype] of string[8] = ('',
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'ARMV8'
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);
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fputypestr : array[tfputype] of string[9] = ('',
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'VFP'
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);
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{ Supported optimizations, only used for information }
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supported_optimizerswitches = genericlevel1optimizerswitches+
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genericlevel2optimizerswitches+
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genericlevel3optimizerswitches-
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{ no need to write info about those }
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[cs_opt_level1,cs_opt_level2,cs_opt_level3]+
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[{$ifndef llvm}cs_opt_regvar,{$endif}cs_opt_loopunroll,cs_opt_tailrecursion,
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cs_opt_nodecse,cs_opt_reorder_fields,cs_opt_fastmath];
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level1optimizerswitches = genericlevel1optimizerswitches;
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level2optimizerswitches = genericlevel2optimizerswitches + level1optimizerswitches +
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[{$ifndef llvm}cs_opt_regvar,{$endif}cs_opt_stackframe,cs_opt_tailrecursion,cs_opt_nodecse];
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level3optimizerswitches = genericlevel3optimizerswitches + level2optimizerswitches + [{,cs_opt_loopunroll}];
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level4optimizerswitches = genericlevel4optimizerswitches + level3optimizerswitches + [];
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Implementation
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end.
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