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638 lines
23 KiB
ObjectPascal
638 lines
23 KiB
ObjectPascal
{
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$Id$
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Copyright (c) 1998-2002 by Florian Klaempfl
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This unit implements the code generator for the i386
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit cgcpu;
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{$i fpcdefs.inc}
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interface
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uses
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globtype,
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cgbase,cgobj,cg64f32,cgx86,
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aasmbase,aasmtai,aasmcpu,
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cpubase,parabase,cgutils,
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symconst
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;
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type
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tcg386 = class(tcgx86)
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procedure init_register_allocators;override;
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{ passing parameter using push instead of mov }
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procedure a_param_reg(list : taasmoutput;size : tcgsize;r : tregister;const cgpara : tcgpara);override;
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procedure a_param_const(list : taasmoutput;size : tcgsize;a : aint;const cgpara : tcgpara);override;
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procedure a_param_ref(list : taasmoutput;size : tcgsize;const r : treference;const cgpara : tcgpara);override;
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procedure a_paramaddr_ref(list : taasmoutput;const r : treference;const cgpara : tcgpara);override;
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procedure g_proc_exit(list : taasmoutput;parasize:longint;nostackframe:boolean);override;
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procedure g_copyvaluepara_openarray(list : taasmoutput;const ref:treference;const lenloc:tlocation;elesize:aint;destreg:tregister);override;
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procedure g_exception_reason_save(list : taasmoutput; const href : treference);override;
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procedure g_exception_reason_save_const(list : taasmoutput; const href : treference; a: aint);override;
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procedure g_exception_reason_load(list : taasmoutput; const href : treference);override;
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end;
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tcg64f386 = class(tcg64f32)
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procedure a_op64_ref_reg(list : taasmoutput;op:TOpCG;const ref : treference;reg : tregister64);override;
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procedure a_op64_reg_reg(list : taasmoutput;op:TOpCG;regsrc,regdst : tregister64);override;
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procedure a_op64_const_reg(list : taasmoutput;op:TOpCG;value : int64;reg : tregister64);override;
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procedure a_op64_const_ref(list : taasmoutput;op:TOpCG;value : int64;const ref : treference);override;
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private
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procedure get_64bit_ops(op:TOpCG;var op1,op2:TAsmOp);
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end;
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implementation
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uses
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globals,verbose,systems,cutils,
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paramgr,procinfo,
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rgcpu,rgx86;
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function use_push(const cgpara:tcgpara):boolean;
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begin
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result:=assigned(cgpara.location) and
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(cgpara.location^.loc=LOC_REFERENCE) and
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(cgpara.location^.reference.index=NR_STACK_POINTER_REG);
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end;
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procedure Tcg386.init_register_allocators;
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begin
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inherited init_register_allocators;
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if cs_create_pic in aktmoduleswitches then
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rg[R_INTREGISTER]:=trgcpu.create(R_INTREGISTER,R_SUBWHOLE,[RS_EAX,RS_EDX,RS_ECX,RS_ESI,RS_EDI],first_int_imreg,[RS_EBP,RS_EBX])
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else
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rg[R_INTREGISTER]:=trgcpu.create(R_INTREGISTER,R_SUBWHOLE,[RS_EAX,RS_EDX,RS_ECX,RS_EBX,RS_ESI,RS_EDI],first_int_imreg,[RS_EBP]);
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rg[R_MMXREGISTER]:=trgcpu.create(R_MMXREGISTER,R_SUBNONE,[RS_XMM0,RS_XMM1,RS_XMM2,RS_XMM3,RS_XMM4,RS_XMM5,RS_XMM6,RS_XMM7],first_mm_imreg,[]);
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rg[R_MMREGISTER]:=trgcpu.create(R_MMREGISTER,R_SUBNONE,[RS_XMM0,RS_XMM1,RS_XMM2,RS_XMM3,RS_XMM4,RS_XMM5,RS_XMM6,RS_XMM7],first_mm_imreg,[]);
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rgfpu:=Trgx86fpu.create;
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end;
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procedure tcg386.a_param_reg(list : taasmoutput;size : tcgsize;r : tregister;const cgpara : tcgpara);
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var
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pushsize : tcgsize;
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begin
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check_register_size(size,r);
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if use_push(cgpara) then
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begin
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cgpara.check_simple_location;
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pushsize:=int_cgsize(cgpara.alignment);
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list.concat(taicpu.op_reg(A_PUSH,tcgsize2opsize[pushsize],makeregsize(list,r,pushsize)));
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end
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else
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inherited a_param_reg(list,size,r,cgpara);
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end;
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procedure tcg386.a_param_const(list : taasmoutput;size : tcgsize;a : aint;const cgpara : tcgpara);
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var
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pushsize : tcgsize;
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begin
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if use_push(cgpara) then
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begin
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cgpara.check_simple_location;
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pushsize:=int_cgsize(cgpara.alignment);
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list.concat(taicpu.op_const(A_PUSH,tcgsize2opsize[pushsize],a));
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end
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else
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inherited a_param_const(list,size,a,cgpara);
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end;
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procedure tcg386.a_param_ref(list : taasmoutput;size : tcgsize;const r : treference;const cgpara : tcgpara);
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procedure pushdata(paraloc:pcgparalocation;ofs:aint);
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var
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pushsize : tcgsize;
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tmpreg : tregister;
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href : treference;
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begin
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if not assigned(paraloc) then
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exit;
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if (paraloc^.loc<>LOC_REFERENCE) or
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(paraloc^.reference.index<>NR_STACK_POINTER_REG) or
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(tcgsize2size[paraloc^.size]>sizeof(aint)) then
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internalerror(200501162);
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{ Pushes are needed in reverse order, add the size of the
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current location to the offset where to load from. This
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prevents wrong calculations for the last location when
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the size is not a power of 2 }
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if assigned(paraloc^.next) then
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pushdata(paraloc^.next,ofs+tcgsize2size[paraloc^.size]);
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{ Push the data starting at ofs }
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href:=r;
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inc(href.offset,ofs);
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if tcgsize2size[paraloc^.size]>cgpara.alignment then
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pushsize:=paraloc^.size
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else
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pushsize:=int_cgsize(cgpara.alignment);
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if tcgsize2size[paraloc^.size]<cgpara.alignment then
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begin
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tmpreg:=getintregister(list,pushsize);
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a_load_ref_reg(list,paraloc^.size,pushsize,href,tmpreg);
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list.concat(taicpu.op_reg(A_PUSH,TCgsize2opsize[pushsize],tmpreg));
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end
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else
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list.concat(taicpu.op_ref(A_PUSH,TCgsize2opsize[pushsize],href));
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end;
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var
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len : aint;
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href : treference;
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begin
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{ cgpara.size=OS_NO requires a copy on the stack }
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if use_push(cgpara) then
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begin
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if tcgsize2size[cgpara.size]<>tcgsize2size[size] then
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internalerror(200501161);
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{ Record copy? }
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if (cgpara.size=OS_NO) then
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begin
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cgpara.check_simple_location;
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len:=align(cgpara.intsize,cgpara.alignment);
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g_stackpointer_alloc(list,len);
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reference_reset_base(href,NR_STACK_POINTER_REG,0);
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g_concatcopy(list,r,href,len);
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end
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else
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begin
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{ We need to push the data in reverse order,
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therefor we use a recursive algorithm }
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pushdata(cgpara.location,0);
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end
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end
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else
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inherited a_param_ref(list,size,r,cgpara);
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end;
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procedure tcg386.a_paramaddr_ref(list : taasmoutput;const r : treference;const cgpara : tcgpara);
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var
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tmpreg : tregister;
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opsize : topsize;
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begin
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with r do
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begin
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if (segment<>NR_NO) then
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cgmessage(cg_e_cant_use_far_pointer_there);
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if use_push(cgpara) then
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begin
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cgpara.check_simple_location;
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opsize:=tcgsize2opsize[OS_ADDR];
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if (base=NR_NO) and (index=NR_NO) then
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begin
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if assigned(symbol) then
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list.concat(Taicpu.Op_sym_ofs(A_PUSH,opsize,symbol,offset))
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else
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list.concat(Taicpu.Op_const(A_PUSH,opsize,offset));
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end
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else if (base=NR_NO) and (index<>NR_NO) and
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(offset=0) and (scalefactor=0) and (symbol=nil) then
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list.concat(Taicpu.Op_reg(A_PUSH,opsize,index))
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else if (base<>NR_NO) and (index=NR_NO) and
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(offset=0) and (symbol=nil) then
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list.concat(Taicpu.Op_reg(A_PUSH,opsize,base))
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else
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begin
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tmpreg:=getaddressregister(list);
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a_loadaddr_ref_reg(list,r,tmpreg);
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list.concat(taicpu.op_reg(A_PUSH,opsize,tmpreg));
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end;
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end
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else
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inherited a_paramaddr_ref(list,r,cgpara);
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end;
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end;
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procedure tcg386.g_proc_exit(list : taasmoutput;parasize:longint;nostackframe:boolean);
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var
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stacksize : longint;
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begin
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{ Release PIC register }
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if cs_create_pic in aktmoduleswitches then
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list.concat(tai_regalloc.dealloc(NR_PIC_OFFSET_REG,nil));
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{ MMX needs to call EMMS }
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if assigned(rg[R_MMXREGISTER]) and
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(rg[R_MMXREGISTER].uses_registers) then
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list.concat(Taicpu.op_none(A_EMMS,S_NO));
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{ remove stackframe }
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if not nostackframe then
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begin
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if (current_procinfo.framepointer=NR_STACK_POINTER_REG) then
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begin
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stacksize:=current_procinfo.calc_stackframe_size;
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if (stacksize<>0) then
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cg.a_op_const_reg(list,OP_ADD,OS_ADDR,stacksize,current_procinfo.framepointer);
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end
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else
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list.concat(Taicpu.op_none(A_LEAVE,S_NO));
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list.concat(tai_regalloc.dealloc(NR_FRAME_POINTER_REG,nil));
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end;
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{ return from proc }
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if (po_interrupt in current_procinfo.procdef.procoptions) then
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begin
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if (current_procinfo.procdef.funcretloc[calleeside].loc<>LOC_VOID) and
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(current_procinfo.procdef.funcretloc[calleeside].loc=LOC_REGISTER) then
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list.concat(Taicpu.Op_const_reg(A_ADD,S_L,4,NR_ESP))
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else
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list.concat(Taicpu.Op_reg(A_POP,S_L,NR_EAX));
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list.concat(Taicpu.Op_reg(A_POP,S_L,NR_EBX));
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list.concat(Taicpu.Op_reg(A_POP,S_L,NR_ECX));
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if (current_procinfo.procdef.funcretloc[calleeside].loc=LOC_REGISTER) and
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(current_procinfo.procdef.funcretloc[calleeside].size in [OS_64,OS_S64]) then
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list.concat(Taicpu.Op_const_reg(A_ADD,S_L,4,NR_ESP))
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else
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list.concat(Taicpu.Op_reg(A_POP,S_L,NR_EDX));
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list.concat(Taicpu.Op_reg(A_POP,S_L,NR_ESI));
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list.concat(Taicpu.Op_reg(A_POP,S_L,NR_EDI));
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{ .... also the segment registers }
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list.concat(Taicpu.Op_reg(A_POP,S_W,NR_DS));
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list.concat(Taicpu.Op_reg(A_POP,S_W,NR_ES));
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list.concat(Taicpu.Op_reg(A_POP,S_W,NR_FS));
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list.concat(Taicpu.Op_reg(A_POP,S_W,NR_GS));
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{ this restores the flags }
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list.concat(Taicpu.Op_none(A_IRET,S_NO));
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end
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{ Routines with the poclearstack flag set use only a ret }
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else if current_procinfo.procdef.proccalloption in clearstack_pocalls then
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begin
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{ complex return values are removed from stack in C code PM }
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if paramanager.ret_in_param(current_procinfo.procdef.rettype.def,
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current_procinfo.procdef.proccalloption) then
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list.concat(Taicpu.Op_const(A_RET,S_NO,sizeof(aint)))
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else
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list.concat(Taicpu.Op_none(A_RET,S_NO));
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end
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{ ... also routines with parasize=0 }
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else if (parasize=0) then
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list.concat(Taicpu.Op_none(A_RET,S_NO))
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else
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begin
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{ parameters are limited to 65535 bytes because ret allows only imm16 }
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if (parasize>65535) then
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CGMessage(cg_e_parasize_too_big);
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list.concat(Taicpu.Op_const(A_RET,S_NO,parasize));
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end;
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end;
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procedure tcg386.g_copyvaluepara_openarray(list : taasmoutput;const ref:treference;const lenloc:tlocation;elesize:aint;destreg:tregister);
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var
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power,len : longint;
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opsize : topsize;
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{$ifndef __NOWINPECOFF__}
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again,ok : tasmlabel;
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{$endif}
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begin
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{ get stack space }
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getcpuregister(list,NR_EDI);
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a_load_loc_reg(list,OS_INT,lenloc,NR_EDI);
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list.concat(Taicpu.op_reg(A_INC,S_L,NR_EDI));
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if (elesize<>1) then
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begin
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if ispowerof2(elesize, power) then
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list.concat(Taicpu.op_const_reg(A_SHL,S_L,power,NR_EDI))
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else
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list.concat(Taicpu.op_const_reg(A_IMUL,S_L,elesize,NR_EDI));
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end;
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{$ifndef __NOWINPECOFF__}
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{ windows guards only a few pages for stack growing, }
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{ so we have to access every page first }
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if target_info.system=system_i386_win32 then
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begin
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objectlibrary.getlabel(again);
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objectlibrary.getlabel(ok);
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a_label(list,again);
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list.concat(Taicpu.op_const_reg(A_CMP,S_L,winstackpagesize,NR_EDI));
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a_jmp_cond(list,OC_B,ok);
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list.concat(Taicpu.op_const_reg(A_SUB,S_L,winstackpagesize-4,NR_ESP));
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list.concat(Taicpu.op_reg(A_PUSH,S_L,NR_EDI));
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list.concat(Taicpu.op_const_reg(A_SUB,S_L,winstackpagesize,NR_EDI));
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a_jmp_always(list,again);
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a_label(list,ok);
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list.concat(Taicpu.op_reg_reg(A_SUB,S_L,NR_EDI,NR_ESP));
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ungetcpuregister(list,NR_EDI);
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{ now reload EDI }
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getcpuregister(list,NR_EDI);
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a_load_loc_reg(list,OS_INT,lenloc,NR_EDI);
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list.concat(Taicpu.op_reg(A_INC,S_L,NR_EDI));
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if (elesize<>1) then
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begin
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if ispowerof2(elesize, power) then
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list.concat(Taicpu.op_const_reg(A_SHL,S_L,power,NR_EDI))
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else
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list.concat(Taicpu.op_const_reg(A_IMUL,S_L,elesize,NR_EDI));
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end;
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end
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else
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{$endif __NOWINPECOFF__}
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list.concat(Taicpu.op_reg_reg(A_SUB,S_L,NR_EDI,NR_ESP));
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{ align stack on 4 bytes }
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list.concat(Taicpu.op_const_reg(A_AND,S_L,aint($fffffff4),NR_ESP));
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{ load destination, don't use a_load_reg_reg, that will add a move instruction
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that can confuse the reg allocator }
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list.concat(Taicpu.Op_reg_reg(A_MOV,S_L,NR_ESP,NR_EDI));
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{ Allocate other registers }
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getcpuregister(list,NR_ECX);
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getcpuregister(list,NR_ESI);
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{ load count }
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a_load_loc_reg(list,OS_INT,lenloc,NR_ECX);
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{ load source }
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a_loadaddr_ref_reg(list,ref,NR_ESI);
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{ scheduled .... }
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list.concat(Taicpu.op_reg(A_INC,S_L,NR_ECX));
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{ calculate size }
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len:=elesize;
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opsize:=S_B;
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if (len and 3)=0 then
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begin
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opsize:=S_L;
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len:=len shr 2;
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end
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else
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if (len and 1)=0 then
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begin
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opsize:=S_W;
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len:=len shr 1;
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end;
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if len<>0 then
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begin
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if ispowerof2(len, power) then
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list.concat(Taicpu.op_const_reg(A_SHL,S_L,power,NR_ECX))
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else
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list.concat(Taicpu.op_const_reg(A_IMUL,S_L,len,NR_ECX));
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end;
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list.concat(Taicpu.op_none(A_REP,S_NO));
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case opsize of
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S_B : list.concat(Taicpu.Op_none(A_MOVSB,S_NO));
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S_W : list.concat(Taicpu.Op_none(A_MOVSW,S_NO));
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S_L : list.concat(Taicpu.Op_none(A_MOVSD,S_NO));
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end;
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ungetcpuregister(list,NR_EDI);
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ungetcpuregister(list,NR_ECX);
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ungetcpuregister(list,NR_ESI);
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{ patch the new address, but don't use a_load_reg_reg, that will add a move instruction
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that can confuse the reg allocator }
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list.concat(Taicpu.Op_reg_reg(A_MOV,S_L,NR_ESP,destreg));
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end;
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procedure tcg386.g_exception_reason_save(list : taasmoutput; const href : treference);
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begin
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list.concat(Taicpu.op_reg(A_PUSH,tcgsize2opsize[OS_INT],NR_FUNCTION_RESULT_REG));
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end;
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procedure tcg386.g_exception_reason_save_const(list : taasmoutput;const href : treference; a: aint);
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begin
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list.concat(Taicpu.op_const(A_PUSH,tcgsize2opsize[OS_INT],a));
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end;
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|
|
|
|
|
procedure tcg386.g_exception_reason_load(list : taasmoutput; const href : treference);
|
|
begin
|
|
list.concat(Taicpu.op_reg(A_POP,tcgsize2opsize[OS_INT],NR_FUNCTION_RESULT_REG));
|
|
end;
|
|
|
|
|
|
{ ************* 64bit operations ************ }
|
|
|
|
procedure tcg64f386.get_64bit_ops(op:TOpCG;var op1,op2:TAsmOp);
|
|
begin
|
|
case op of
|
|
OP_ADD :
|
|
begin
|
|
op1:=A_ADD;
|
|
op2:=A_ADC;
|
|
end;
|
|
OP_SUB :
|
|
begin
|
|
op1:=A_SUB;
|
|
op2:=A_SBB;
|
|
end;
|
|
OP_XOR :
|
|
begin
|
|
op1:=A_XOR;
|
|
op2:=A_XOR;
|
|
end;
|
|
OP_OR :
|
|
begin
|
|
op1:=A_OR;
|
|
op2:=A_OR;
|
|
end;
|
|
OP_AND :
|
|
begin
|
|
op1:=A_AND;
|
|
op2:=A_AND;
|
|
end;
|
|
else
|
|
internalerror(200203241);
|
|
end;
|
|
end;
|
|
|
|
|
|
procedure tcg64f386.a_op64_ref_reg(list : taasmoutput;op:TOpCG;const ref : treference;reg : tregister64);
|
|
var
|
|
op1,op2 : TAsmOp;
|
|
tempref : treference;
|
|
begin
|
|
get_64bit_ops(op,op1,op2);
|
|
list.concat(taicpu.op_ref_reg(op1,S_L,ref,reg.reglo));
|
|
tempref:=ref;
|
|
inc(tempref.offset,4);
|
|
list.concat(taicpu.op_ref_reg(op2,S_L,tempref,reg.reghi));
|
|
end;
|
|
|
|
|
|
procedure tcg64f386.a_op64_reg_reg(list : taasmoutput;op:TOpCG;regsrc,regdst : tregister64);
|
|
var
|
|
op1,op2 : TAsmOp;
|
|
begin
|
|
case op of
|
|
OP_NEG :
|
|
begin
|
|
if (regsrc.reglo<>regdst.reglo) then
|
|
a_load64_reg_reg(list,regsrc,regdst);
|
|
list.concat(taicpu.op_reg(A_NOT,S_L,regdst.reghi));
|
|
list.concat(taicpu.op_reg(A_NEG,S_L,regdst.reglo));
|
|
list.concat(taicpu.op_const_reg(A_SBB,S_L,-1,regdst.reghi));
|
|
exit;
|
|
end;
|
|
OP_NOT :
|
|
begin
|
|
if (regsrc.reglo<>regdst.reglo) then
|
|
a_load64_reg_reg(list,regsrc,regdst);
|
|
list.concat(taicpu.op_reg(A_NOT,S_L,regdst.reghi));
|
|
list.concat(taicpu.op_reg(A_NOT,S_L,regdst.reglo));
|
|
exit;
|
|
end;
|
|
end;
|
|
get_64bit_ops(op,op1,op2);
|
|
list.concat(taicpu.op_reg_reg(op1,S_L,regsrc.reglo,regdst.reglo));
|
|
list.concat(taicpu.op_reg_reg(op2,S_L,regsrc.reghi,regdst.reghi));
|
|
end;
|
|
|
|
|
|
procedure tcg64f386.a_op64_const_reg(list : taasmoutput;op:TOpCG;value : int64;reg : tregister64);
|
|
var
|
|
op1,op2 : TAsmOp;
|
|
begin
|
|
case op of
|
|
OP_AND,OP_OR,OP_XOR:
|
|
begin
|
|
cg.a_op_const_reg(list,op,OS_32,aint(lo(value)),reg.reglo);
|
|
cg.a_op_const_reg(list,op,OS_32,aint(hi(value)),reg.reghi);
|
|
end;
|
|
OP_ADD, OP_SUB:
|
|
begin
|
|
// can't use a_op_const_ref because this may use dec/inc
|
|
get_64bit_ops(op,op1,op2);
|
|
list.concat(taicpu.op_const_reg(op1,S_L,aint(lo(value)),reg.reglo));
|
|
list.concat(taicpu.op_const_reg(op2,S_L,aint(hi(value)),reg.reghi));
|
|
end;
|
|
else
|
|
internalerror(200204021);
|
|
end;
|
|
end;
|
|
|
|
|
|
procedure tcg64f386.a_op64_const_ref(list : taasmoutput;op:TOpCG;value : int64;const ref : treference);
|
|
var
|
|
op1,op2 : TAsmOp;
|
|
tempref : treference;
|
|
begin
|
|
case op of
|
|
OP_AND,OP_OR,OP_XOR:
|
|
begin
|
|
cg.a_op_const_ref(list,op,OS_32,lo(value),ref);
|
|
tempref:=ref;
|
|
inc(tempref.offset,4);
|
|
cg.a_op_const_ref(list,op,OS_32,hi(value),tempref);
|
|
end;
|
|
OP_ADD, OP_SUB:
|
|
begin
|
|
get_64bit_ops(op,op1,op2);
|
|
// can't use a_op_const_ref because this may use dec/inc
|
|
list.concat(taicpu.op_const_ref(op1,S_L,lo(value),ref));
|
|
tempref:=ref;
|
|
inc(tempref.offset,4);
|
|
list.concat(taicpu.op_const_ref(op2,S_L,hi(value),tempref));
|
|
end;
|
|
else
|
|
internalerror(200204022);
|
|
end;
|
|
end;
|
|
|
|
begin
|
|
cg := tcg386.create;
|
|
cg64 := tcg64f386.create;
|
|
end.
|
|
{
|
|
$Log$
|
|
Revision 1.63 2005-01-18 22:19:20 peter
|
|
* multiple location support for i386 a_param_ref
|
|
* remove a_param_copy_ref for i386
|
|
|
|
Revision 1.62 2004/11/21 17:54:59 peter
|
|
* ttempcreatenode.create_reg merged into .create with parameter
|
|
whether a register is allowed
|
|
* funcret_paraloc renamed to funcretloc
|
|
|
|
Revision 1.61 2004/11/21 17:17:04 florian
|
|
* changed funcret location back to tlocation
|
|
|
|
Revision 1.60 2004/10/31 21:45:03 peter
|
|
* generic tlocation
|
|
* move tlocation to cgutils
|
|
|
|
Revision 1.59 2004/10/24 20:01:08 peter
|
|
* remove saveregister calling convention
|
|
|
|
Revision 1.58 2004/10/24 11:44:28 peter
|
|
* small regvar fixes
|
|
* loadref parameter removed from concatcopy,incrrefcount,etc
|
|
|
|
Revision 1.57 2004/10/15 09:16:21 mazen
|
|
- remove $IFDEF DELPHI and related code
|
|
- remove $IFDEF FPCPROCVAR and related code
|
|
|
|
Revision 1.56 2004/10/13 21:12:51 peter
|
|
* -Or fixes for open array
|
|
|
|
Revision 1.55 2004/10/11 15:46:45 peter
|
|
* length parameter for copyvaluearray changed to tlocation
|
|
|
|
Revision 1.54 2004/10/05 20:41:01 peter
|
|
* more spilling rewrites
|
|
|
|
Revision 1.53 2004/09/25 14:23:54 peter
|
|
* ungetregister is now only used for cpuregisters, renamed to
|
|
ungetcpuregister
|
|
* renamed (get|unget)explicitregister(s) to ..cpuregister
|
|
* removed location-release/reference_release
|
|
|
|
Revision 1.52 2004/09/21 17:25:12 peter
|
|
* paraloc branch merged
|
|
|
|
Revision 1.51.4.1 2004/08/31 20:43:06 peter
|
|
* paraloc patch
|
|
|
|
Revision 1.51 2004/07/09 23:30:13 jonas
|
|
* changed first_sse_imreg to first_mm_imreg
|
|
|
|
Revision 1.50 2004/06/20 08:55:31 florian
|
|
* logs truncated
|
|
|
|
Revision 1.49 2004/06/16 20:07:10 florian
|
|
* dwarf branch merged
|
|
|
|
Revision 1.48 2004/04/09 14:36:05 peter
|
|
* A_MOVSL renamed to A_MOVSD
|
|
|
|
Revision 1.47.2.9 2004/05/30 10:45:50 peter
|
|
* merged fixes from main branch
|
|
|
|
Revision 1.47.2.8 2004/05/02 21:34:01 florian
|
|
* i386 compilation fixed
|
|
|
|
Revision 1.47.2.7 2004/05/02 12:45:32 peter
|
|
* enabled cpuhasfixedstack for x86-64 again
|
|
* fixed size of temp allocation for parameters
|
|
|
|
}
|