florian 9e2bcd940a + RiscV: initial OpAddi02Op implementation ... git-svn-id: trunk@49002 -		2021-03-18 21:49:25 +00:00
..
aasmcpu.pas	+ RiscV: initial support of pic generation	2021-03-13 16:18:00 +00:00
agrvgas.pas	+ RiscV: initial support of pic generation	2021-03-13 16:18:00 +00:00
aoptcpurv.pas	+ RiscV: initial OpAddi02Op implementation	2021-03-18 21:49:25 +00:00
cgrv.pas	Rough fix for riscv32 failure	2021-03-14 09:10:29 +00:00
hlcgrv.pas	* patch by Marģers to unify internal error numbers, resolves #37888	2020-10-13 19:59:01 +00:00
itcpugas.pas	* RiscV: unified itcpugas.pas	2021-03-14 10:29:23 +00:00
nrvadd.pas	* do not generate mul instructions if the mul extension is not available	2021-03-06 14:23:54 +00:00
nrvcnv.pas
nrvcon.pas
nrvinl.pas	+ software handling of exceptions on arm	2019-07-28 21:06:36 +00:00
nrvset.pas	* let all the case code generation work with tconstexprint instead of aint,	2019-02-24 19:58:37 +00:00
rarv.pas	* unified RiscV32 and RiscV64 GAS readers	2021-03-07 08:53:03 +00:00
rarvgas.pas	* unified RiscV32 and RiscV64 GAS readers	2021-03-07 08:53:03 +00:00
rgcpu.pas	Add explicit smallint typecast to first marameter of SarSmallint call to avoid range check errors	2019-11-29 23:26:45 +00:00