Jonas Maebe 592df7fa59 * disable cs_opt_regvar on all platforms when compiled for LLVM (LLVM does ... that itself, our LLVM code generator can't handle it, and if it did then afterwards we would have to spill 90% of those register variables again to make them SSA) git-svn-id: trunk@44062 -		2020-01-29 22:21:07 +00:00
..
aoptcpu.pas	- RISC-V: Share optimizations between 32 and 64-bit.	2020-01-13 22:49:23 +00:00
aoptcpub.pas
aoptcpuc.pas
aoptcpud.pas
cgcpu.pas	- RISC-V: Share optimizations between 32 and 64-bit.	2020-01-13 22:49:23 +00:00
cpubase.pas	- RISC-V: Share optimizations between 32 and 64-bit.	2020-01-13 22:49:23 +00:00
cpuinfo.pas	* disable cs_opt_regvar on all platforms when compiled for LLVM (LLVM does	2020-01-29 22:21:07 +00:00
cpunode.pas
cpupara.pas	* renamed getintparaloc to getcgtempparaloc	2019-12-24 22:12:25 +00:00
cpupi.pas	* fix case completeness and unreachable code warnings in compiler that would	2019-05-12 14:29:03 +00:00
cputarg.pas
hlcgcpu.pas
itcpugas.pas
nrv32add.pas
nrv32cal.pas
nrv32cnv.pas	* fix case completeness and unreachable code warnings in compiler that would	2019-05-12 14:29:03 +00:00
nrv32mat.pas	Fix trv32notnode, by using same code as for riscv64 CPU	2019-11-28 22:34:04 +00:00
rarv32.pas
rarv32gas.pas	* correctly handle local reference in the RISC V assembler readers (both 32 and 64 bit)	2019-12-25 15:23:28 +00:00
rrv32con.inc
rrv32dwa.inc
rrv32nor.inc
rrv32num.inc
rrv32rni.inc
rrv32sri.inc
rrv32sta.inc
rrv32std.inc
rrv32sup.inc
rv32reg.dat
symcpu.pas