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372 lines
16 KiB
ObjectPascal
372 lines
16 KiB
ObjectPascal
{
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Copyright (c) 1998-2002 by Florian Klaempfl
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Generate SPARC assembler for type converting nodes
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************}
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unit ncpucnv;
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{$i fpcdefs.inc}
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interface
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uses
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node,ncnv,ncgcnv,defcmp;
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type
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tsparctypeconvnode = class(TCgTypeConvNode)
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protected
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{ procedure second_int_to_int;override; }
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{ procedure second_string_to_string;override; }
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{ procedure second_cstring_to_pchar;override; }
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{ procedure second_string_to_chararray;override; }
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{ procedure second_array_to_pointer;override; }
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function first_int_to_real: tnode; override;
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{ procedure second_pointer_to_array;override; }
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{ procedure second_chararray_to_string;override; }
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{ procedure second_char_to_string;override; }
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procedure second_int_to_real;override;
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{ procedure second_real_to_real;override; }
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{ procedure second_cord_to_pointer;override; }
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{ procedure second_proc_to_procvar;override; }
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{ procedure second_bool_to_int;override; }
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procedure second_int_to_bool;override;
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{ procedure second_load_smallset;override; }
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{ procedure second_ansistring_to_pchar;override; }
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{ procedure second_pchar_to_string;override; }
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{ procedure second_class_to_intf;override; }
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{ procedure second_char_to_char;override; }
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end;
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implementation
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uses
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verbose,globals,systems,globtype,
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symconst,symdef,aasmbase,aasmtai,aasmdata,
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defutil,
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cgbase,cgutils,pass_1,pass_2,
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ncon,ncal,procinfo,
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ncgutil,
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cpuinfo,cpubase,aasmcpu,
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tgobj,cgobj,
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hlcgobj;
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{*****************************************************************************
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FirstTypeConv
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*****************************************************************************}
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function tsparctypeconvnode.first_int_to_real: tnode;
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var
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fname: string[19];
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begin
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{ converting a 64bit integer to a float requires a helper }
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if is_64bitint(left.resultdef) or
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is_currency(left.resultdef) then
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begin
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{ hack to avoid double division by 10000, as it's
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already done by typecheckpass.resultdef_int_to_real }
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if is_currency(left.resultdef) then
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left.resultdef := s64inttype;
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if is_signed(left.resultdef) then
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fname := 'fpc_int64_to_double'
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else
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fname := 'fpc_qword_to_double';
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result := ccallnode.createintern(fname,ccallparanode.create(
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left,nil));
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left:=nil;
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if (tfloatdef(resultdef).floattype=s32real) then
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inserttypeconv(result,s32floattype);
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firstpass(result);
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exit;
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end
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else
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{ other integers are supposed to be 32 bit }
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begin
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if is_signed(left.resultdef) then
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inserttypeconv(left,s32inttype)
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else
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begin
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inserttypeconv(left,u32inttype);
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if (cs_create_pic in current_settings.moduleswitches) and
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(tf_pic_uses_got in target_info.flags) then
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include(current_procinfo.flags,pi_needs_got);
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end;
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firstpass(left);
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end;
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result := nil;
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expectloc:=LOC_FPUREGISTER;
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end;
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{*****************************************************************************
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SecondTypeConv
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*****************************************************************************}
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procedure tsparctypeconvnode.second_int_to_real;
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procedure loadsigned;
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begin
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hlcg.location_force_mem(current_asmdata.CurrAsmList,left.location,left.resultdef);
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{ Load memory in fpu register }
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cg.a_loadfpu_ref_reg(current_asmdata.CurrAsmList,OS_F32,OS_F32,left.location.reference,location.register);
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tg.ungetiftemp(current_asmdata.CurrAsmList,left.location.reference);
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{ Convert value in fpu register from integer to float }
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case tfloatdef(resultdef).floattype of
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s32real:
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_FiTOs,location.register,location.register));
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s64real:
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_FiTOd,location.register,location.register));
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s128real:
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_FiTOq,location.register,location.register));
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else
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internalerror(200408011);
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end;
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end;
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var
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href : treference;
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hregister : tregister;
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l1,l2 : tasmlabel;
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TempFlags : TResFlags;
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begin
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location_reset(location,LOC_FPUREGISTER,def_cgsize(resultdef));
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if is_signed(left.resultdef) then
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begin
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location.register:=cg.getfpuregister(current_asmdata.CurrAsmList,location.size);
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loadsigned;
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end
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else
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begin
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current_asmdata.getglobaldatalabel(l1);
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current_asmdata.getjumplabel(l2);
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reference_reset_symbol(href,l1,0,8,[]);
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hregister:=cg.getintregister(current_asmdata.CurrAsmList,OS_32);
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hlcg.a_load_loc_reg(current_asmdata.CurrAsmList,left.resultdef,u32inttype,left.location,hregister);
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{ here we need always an 64 bit register }
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location.register:=cg.getfpuregister(current_asmdata.CurrAsmList,OS_F64);
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hlcg.location_force_mem(current_asmdata.CurrAsmList,left.location,left.resultdef);
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{ Load memory in fpu register }
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cg.a_loadfpu_ref_reg(current_asmdata.CurrAsmList,OS_F32,OS_F32,left.location.reference,location.register);
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tg.ungetiftemp(current_asmdata.CurrAsmList,left.location.reference);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_FiTOd,location.register,location.register));
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current_asmdata.CurrAsmList.concat(Taicpu.op_reg_reg(A_CMP,hregister,NR_G0));
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TempFlags.Init(NR_ICC,F_GE);
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cg.a_jmp_flags(current_asmdata.CurrAsmList,TempFlags,l2);
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case tfloatdef(resultdef).floattype of
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{ converting dword to s64real first and cut off at the end avoids precision loss }
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s32real,
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s64real:
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begin
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hregister:=cg.getfpuregister(current_asmdata.CurrAsmList,OS_F64);
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new_section(current_asmdata.asmlists[al_typedconsts],sec_rodata_norel,l1.name,const_align(8));
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current_asmdata.asmlists[al_typedconsts].concat(Tai_label.Create(l1));
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{ I got this constant from a test program (FK) }
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current_asmdata.asmlists[al_typedconsts].concat(Tai_const.Create_32bit($41f00000));
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current_asmdata.asmlists[al_typedconsts].concat(Tai_const.Create_32bit(0));
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cg.a_loadfpu_ref_reg(current_asmdata.CurrAsmList,OS_F64,OS_F64,href,hregister);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_FADDD,location.register,hregister,location.register));
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cg.a_label(current_asmdata.CurrAsmList,l2);
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{ cut off if we should convert to single }
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if tfloatdef(resultdef).floattype=s32real then
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begin
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hregister:=location.register;
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location.register:=cg.getfpuregister(current_asmdata.CurrAsmList,location.size);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_FDTOS,hregister,location.register));
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end;
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end;
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else
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internalerror(2004100304);
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end;
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end;
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end;
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(*
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procedure tsparctypeconvnode.second_real_to_real;
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const
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conv_op : array[tfloattype,tfloattype] of tasmop = (
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{ from: s32 s64 s80 sc80 c64 cur f128 }
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{ s32 } ( A_FMOVS,A_FDTOS,A_NONE, A_NONE, A_NONE, A_NONE, A_NONE ),
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{ s64 } ( A_FSTOD,A_FMOVD,A_NONE, A_NONE, A_NONE, A_NONE, A_NONE ),
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{ s80 } ( A_NONE, A_NONE, A_NONE, A_NONE, A_NONE, A_NONE, A_NONE ),
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{ sc80 } ( A_NONE, A_NONE, A_NONE, A_NONE, A_NONE, A_NONE, A_NONE ),
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{ c64 } ( A_NONE, A_NONE, A_NONE, A_NONE, A_NONE, A_NONE, A_NONE ),
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{ cur } ( A_NONE, A_NONE, A_NONE, A_NONE, A_NONE, A_NONE, A_NONE ),
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{ f128 } ( A_NONE, A_NONE, A_NONE, A_NONE, A_NONE, A_NONE, A_NONE )
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);
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var
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op : tasmop;
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begin
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location_reset(location,LOC_FPUREGISTER,def_cgsize(resultdef));
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hlcg.location_force_fpureg(current_asmdata.CurrAsmList,left.location,left.resultdef,false);
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{ Convert value in fpu register from integer to float }
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op:=conv_op[tfloatdef(resultdef).floattype,tfloatdef(left.resultdef).floattype];
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if op=A_NONE then
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internalerror(200401121);
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location.register:=cg.getfpuregister(current_asmdata.CurrAsmList,location.size);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(op,left.location.register,location.register));
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end;
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*)
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procedure tsparctypeconvnode.second_int_to_bool;
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var
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href: treference;
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hreg1,hreg2 : tregister;
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resflags : tresflags;
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opsize : tcgsize;
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hlabel : tasmlabel;
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newsize : tcgsize;
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begin
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secondpass(left);
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if codegenerror then
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exit;
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{ Explicit typecasts from any ordinal type to a boolean type }
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{ must not change the ordinal value }
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if (nf_explicit in flags) and
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not(left.location.loc in [LOC_FLAGS,LOC_JUMP]) then
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begin
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location_copy(location,left.location);
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newsize:=def_cgsize(resultdef);
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{ change of size? change sign only if location is LOC_(C)REGISTER? Then we have to sign/zero-extend }
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if (tcgsize2size[newsize]<>tcgsize2size[left.location.size]) or
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((newsize<>left.location.size) and (location.loc in [LOC_REGISTER,LOC_CREGISTER])) then
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hlcg.location_force_reg(current_asmdata.CurrAsmList,location,left.resultdef,resultdef,true)
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else
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location.size:=newsize;
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exit;
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end;
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location_reset(location,LOC_REGISTER,def_cgsize(resultdef));
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opsize:=def_cgsize(left.resultdef);
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if (left.location.loc in [LOC_SUBSETREG,LOC_CSUBSETREG,LOC_SUBSETREF,LOC_CSUBSETREF]) then
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,true);
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case left.location.loc of
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LOC_CREFERENCE,LOC_REFERENCE,LOC_REGISTER,LOC_CREGISTER:
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begin
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if left.location.loc in [LOC_CREFERENCE,LOC_REFERENCE] then
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begin
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hreg2:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
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{$ifndef cpu64bitalu}
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if left.location.size in [OS_64,OS_S64] then
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begin
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cg.a_load_ref_reg(current_asmdata.CurrAsmList,OS_INT,OS_INT,left.location.reference,hreg2);
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hreg1:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
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href:=left.location.reference;
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inc(href.offset,4);
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cg.a_load_ref_reg(current_asmdata.CurrAsmList,OS_INT,OS_INT,href,hreg1);
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cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList,OP_OR,OS_32,hreg1,hreg2,hreg2);
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end
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else
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{$endif not cpu64bitalu}
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cg.a_load_ref_reg(current_asmdata.CurrAsmList,opsize,opsize,left.location.reference,hreg2);
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end
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else
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begin
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hreg2:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
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{$ifndef cpu64bitalu}
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if left.location.size in [OS_64,OS_S64] then
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begin
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hreg2:=cg.getintregister(current_asmdata.CurrAsmList,OS_32);
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cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList,OP_OR,OS_32,left.location.register64.reghi,left.location.register64.reglo,hreg2);
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end
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else
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{$endif not cpu64bitalu}
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cg.a_load_reg_reg(current_asmdata.CurrAsmList,opsize,opsize,left.location.register,hreg2);
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end;
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hreg1:=cg.getintregister(current_asmdata.CurrAsmList,opsize);
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{$ifdef cpu64bitalu}
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{ there are no ADDC/SUBC instructions working on xcc, i.e. the 64 bit flags }
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if left.location.size in [OS_64,OS_S64] then
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begin
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if current_settings.cputype in [cpu_SPARC_V9] then
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begin
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current_asmdata.CurrAsmList.Concat(taicpu.op_reg_const_reg(A_MOVRZ,hreg2,0,hreg1));
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if is_pasbool(resultdef) then
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current_asmdata.CurrAsmList.Concat(taicpu.op_reg_const_reg(A_MOVRNZ,hreg2,1,hreg1))
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else
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current_asmdata.CurrAsmList.Concat(taicpu.op_reg_const_reg(A_MOVRNZ,hreg2,-1,hreg1));
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end
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else
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Internalerror(2017072101);
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end
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else
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{$endif cpu64bitalu}
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begin
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_SUBCC,NR_G0,hreg2,NR_G0));
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if is_pasbool(resultdef) then
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_ADDX,NR_G0,NR_G0,hreg1))
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else
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_SUBX,NR_G0,NR_G0,hreg1));
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end;
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end;
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LOC_FLAGS :
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begin
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hreg1:=cg.GetIntRegister(current_asmdata.CurrAsmList,location.size);
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resflags:=left.location.resflags;
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cg.g_flags2reg(current_asmdata.CurrAsmList,location.size,resflags,hreg1);
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if (is_cbool(resultdef)) then
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cg.a_op_reg_reg(current_asmdata.CurrAsmList,OP_NEG,location.size,hreg1,hreg1);
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end;
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LOC_JUMP :
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begin
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hreg1:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
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current_asmdata.getjumplabel(hlabel);
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cg.a_label(current_asmdata.CurrAsmList,left.location.truelabel);
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if not(is_cbool(resultdef)) then
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cg.a_load_const_reg(current_asmdata.CurrAsmList,OS_INT,1,hreg1)
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else
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cg.a_load_const_reg(current_asmdata.CurrAsmList,OS_INT,-1,hreg1);
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cg.a_jmp_always(current_asmdata.CurrAsmList,hlabel);
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cg.a_label(current_asmdata.CurrAsmList,left.location.falselabel);
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cg.a_load_const_reg(current_asmdata.CurrAsmList,OS_INT,0,hreg1);
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cg.a_label(current_asmdata.CurrAsmList,hlabel);
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end;
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else
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internalerror(10062);
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end;
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{$ifndef cpu64bitalu}
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if (location.size in [OS_64,OS_S64]) then
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begin
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location.register64.reglo:=hreg1;
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location.register64.reghi:=cg.getintregister(current_asmdata.CurrAsmList,OS_32);
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if (is_cbool(resultdef)) then
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{ reglo is either 0 or -1 -> reghi has to become the same }
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cg.a_load_reg_reg(current_asmdata.CurrAsmList,OS_32,OS_32,location.register64.reglo,location.register64.reghi)
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else
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{ unsigned }
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cg.a_load_const_reg(current_asmdata.CurrAsmList,OS_32,0,location.register64.reghi);
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end
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else
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{$endif not cpu64bitalu}
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location.register:=hreg1;
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end;
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begin
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ctypeconvnode:=tsparctypeconvnode;
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end.
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