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54d3d736f5
and add usermode parsing of LDM/STM ops
This patch basically extends the ARM assembly reader a bit to properly parse CPSR and
SPSR flags for the MSR opcode, and allows the reader to understand
the ^ modifer for register lists for STMxx and LDMxx.
Previously the following combinations weren't possible in straight assembler:
MRS R0, CPSR
MRS R0, SPSR
MSR CPSR_CX, R0
LDMIA SP, {R0-R15}^
etc..
git-svn-id: trunk@22502 -
13 lines
128 B
ObjectPascal
13 lines
128 B
ObjectPascal
{ %norun }
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{ %cpu=arm }
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begin
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asm
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MRS R0, CPSR
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MRS R0, SPSR
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MSR CPSR_CX, R0
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LDMIA SP, {R0-R15}^
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end;
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end.
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