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494 lines
20 KiB
ObjectPascal
494 lines
20 KiB
ObjectPascal
{
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Copyright (c) 1998-2002 by Florian Klaempfl
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This unit implements the x86 specific class for the register
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allocator
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit rgx86;
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{$i fpcdefs.inc}
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interface
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uses
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cclasses,globtype,
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cpubase,cpuinfo,cgbase,cgutils,
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aasmbase,aasmtai,aasmdata,aasmcpu,
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rgobj;
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type
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trgx86 = class(trgobj)
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function get_spill_subreg(r : tregister) : tsubregister;override;
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function do_spill_replace(list:TAsmList;instr:taicpu;orgreg:tsuperregister;const spilltemp:treference):boolean;override;
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end;
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tpushedsavedloc = record
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case byte of
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0: (pushed: boolean);
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1: (ofs: longint);
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end;
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tpushedsavedfpu = array[tsuperregister] of tpushedsavedloc;
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trgx86fpu = class
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{ The "usableregsxxx" contain all registers of type "xxx" that }
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{ aren't currently allocated to a regvar. The "unusedregsxxx" }
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{ contain all registers of type "xxx" that aren't currently }
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{ allocated }
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unusedregsfpu,usableregsfpu : Tsuperregisterset;
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{ these counters contain the number of elements in the }
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{ unusedregsxxx/usableregsxxx sets }
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countunusedregsfpu : byte;
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{ Contains the registers which are really used by the proc itself.
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It doesn't take care of registers used by called procedures
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}
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used_in_proc : tcpuregisterset;
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{reg_pushes_other : regvarother_longintarray;
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is_reg_var_other : regvarother_booleanarray;
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regvar_loaded_other : regvarother_booleanarray;}
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fpuvaroffset : byte;
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constructor create;
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function getregisterfpu(list: TAsmList) : tregister;
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procedure ungetregisterfpu(list: TAsmList; r : tregister);
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{ pushes and restores registers }
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procedure saveusedfpuregisters(list:TAsmList;
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var saved:Tpushedsavedfpu;
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const s:Tcpuregisterset);
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procedure restoreusedfpuregisters(list:TAsmList;
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const saved:Tpushedsavedfpu);
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{ corrects the fpu stack register by ofs }
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function correct_fpuregister(r : tregister;ofs : byte) : tregister;
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end;
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implementation
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uses
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systems,
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verbose;
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const
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{ This value is used in tsaved. If the array value is equal
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to this, then this means that this register is not used.}
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reg_not_saved = $7fffffff;
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{******************************************************************************
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Trgcpu
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******************************************************************************}
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function trgx86.get_spill_subreg(r : tregister) : tsubregister;
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begin
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result:=getsubreg(r);
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end;
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function trgx86.do_spill_replace(list:TAsmList;instr:taicpu;orgreg:tsuperregister;const spilltemp:treference):boolean;
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{Decide wether a "replace" spill is possible, i.e. wether we can replace a register
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in an instruction by a memory reference. For example, in "mov ireg26d,0", the imaginary
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register ireg26d can be replaced by a memory reference.}
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var
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n,replaceoper : longint;
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is_subh: Boolean;
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begin
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result:=false;
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with instr do
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begin
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replaceoper:=-1;
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case ops of
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1 :
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begin
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if (oper[0]^.typ=top_reg) and
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(getregtype(oper[0]^.reg)=regtype) then
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begin
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if get_alias(getsupreg(oper[0]^.reg))<>orgreg then
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internalerror(200410101);
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replaceoper:=0;
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end;
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end;
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2,3 :
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begin
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{ avx instruction?
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currently this rule is sufficient but it might be extended }
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if (ops=3) and (opcode<>A_SHRD) and (opcode<>A_SHLD) and (opcode<>A_IMUL) then
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begin
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{ BMI shifting/rotating instructions have special requirements regarding spilling, only
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the middle operand can be replaced }
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if ((opcode=A_RORX) or (opcode=A_SHRX) or (opcode=A_SARX) or (opcode=A_SHLX)) then
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begin
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if (oper[1]^.typ=top_reg) and (getregtype(oper[1]^.reg)=regtype) and (get_alias(getsupreg(oper[1]^.reg))=orgreg) then
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replaceoper:=1;
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end
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{ avx instructions allow only the first operand (at&t counting) to be a register operand
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all operands must be registers ... }
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else if (oper[0]^.typ=top_reg) and
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(oper[1]^.typ=top_reg) and
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(oper[2]^.typ=top_reg) and
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{ but they must be different }
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((getregtype(oper[1]^.reg)<>regtype) or
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(get_alias(getsupreg(oper[0]^.reg))<>get_alias(getsupreg(oper[1]^.reg)))
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) and
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((getregtype(oper[2]^.reg)<>regtype) or
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(get_alias(getsupreg(oper[0]^.reg))<>get_alias(getsupreg(oper[2]^.reg)))
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) and
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(get_alias(getsupreg(oper[0]^.reg))=orgreg) then
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replaceoper:=0;
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end
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else
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begin
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{ We can handle opcodes with 2 and 3-op imul/shrd/shld the same way, where the 3rd operand is const or CL,
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that doesn't need spilling.
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However, due to AT&T order inside the compiler, the 3rd operand is
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numbered 0, so look at operand no. 1 and 2 if we have 3 operands by
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adding a "n". }
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n:=0;
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if ops=3 then
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n:=1;
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{ lea is tricky: part of operand 0 can be spilled and the instruction can converted into an
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add, if base or index shall be spilled and the other one is equal the destination }
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if (opcode=A_LEA) then
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begin
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if (oper[0]^.ref^.offset=0) and
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(oper[0]^.ref^.scalefactor in [0,1]) and
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(((getregtype(oper[0]^.ref^.base)=regtype) and
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(get_alias(getsupreg(oper[0]^.ref^.base))=orgreg) and
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(getregtype(oper[0]^.ref^.index)=getregtype(oper[1]^.reg)) and
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(get_alias(getsupreg(oper[0]^.ref^.index))=get_alias(getsupreg(oper[1]^.reg)))) or
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((getregtype(oper[0]^.ref^.index)=regtype) and
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(get_alias(getsupreg(oper[0]^.ref^.index))=orgreg) and
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(getregtype(oper[0]^.ref^.base)=getregtype(oper[1]^.reg)) and
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(get_alias(getsupreg(oper[0]^.ref^.base))=get_alias(getsupreg(oper[1]^.reg))))
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) then
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replaceoper:=0;
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end
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else if (oper[n+0]^.typ=top_reg) and
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(oper[n+1]^.typ=top_reg) and
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((getregtype(oper[n+0]^.reg)<>regtype) or
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(getregtype(oper[n+1]^.reg)<>regtype) or
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(get_alias(getsupreg(oper[n+0]^.reg))<>get_alias(getsupreg(oper[n+1]^.reg)))) then
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begin
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if (getregtype(oper[n+0]^.reg)=regtype) and
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(get_alias(getsupreg(oper[n+0]^.reg))=orgreg) then
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replaceoper:=0+n
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else if (getregtype(oper[n+1]^.reg)=regtype) and
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(get_alias(getsupreg(oper[n+1]^.reg))=orgreg) then
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replaceoper:=1+n;
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end
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else if (oper[n+0]^.typ=top_reg) and
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(oper[n+1]^.typ=top_const) then
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begin
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if (getregtype(oper[0+n]^.reg)=regtype) and
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(get_alias(getsupreg(oper[0+n]^.reg))=orgreg) then
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replaceoper:=0+n
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else
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internalerror(200704282);
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end
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else if (oper[n+0]^.typ=top_const) and
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(oper[n+1]^.typ=top_reg) then
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begin
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if (getregtype(oper[1+n]^.reg)=regtype) and
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(get_alias(getsupreg(oper[1+n]^.reg))=orgreg) then
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replaceoper:=1+n
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else
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internalerror(200704283);
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end;
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case replaceoper of
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0 :
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begin
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{ Some instructions don't allow memory references
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for source }
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case instr.opcode of
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A_BT,
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A_BTS,
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A_BTC,
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A_BTR,
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{ shufp* would require 16 byte alignment for memory locations so we force the source
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operand into a register }
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A_SHUFPD,
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A_SHUFPS :
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replaceoper:=-1;
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end;
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end;
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1 :
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begin
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{ Some instructions don't allow memory references
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for destination }
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case instr.opcode of
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A_CMOVcc,
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A_MOVZX,
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A_MOVSX,
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{$ifdef x86_64}
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A_MOVSXD,
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{$endif x86_64}
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A_MULSS,
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A_MULSD,
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A_SUBSS,
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A_SUBSD,
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A_ADDSD,
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A_ADDSS,
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A_DIVSD,
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A_DIVSS,
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A_SQRTSD,
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A_SQRTSS,
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A_SHLD,
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A_SHRD,
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A_COMISD,
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A_COMISS,
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A_CVTDQ2PD,
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A_CVTDQ2PS,
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A_CVTPD2DQ,
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A_CVTPD2PI,
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A_CVTPD2PS,
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A_CVTPI2PD,
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A_CVTPS2DQ,
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A_CVTPS2PD,
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A_CVTSD2SI,
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A_CVTSD2SS,
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A_CVTSI2SD,
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A_CVTSS2SD,
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A_CVTTPD2PI,
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A_CVTTPD2DQ,
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A_CVTTPS2DQ,
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A_CVTTSD2SI,
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A_CVTPI2PS,
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A_CVTPS2PI,
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A_CVTSI2SS,
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A_CVTSS2SI,
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A_CVTTPS2PI,
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A_CVTTSS2SI,
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A_XORPD,
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A_XORPS,
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A_ORPD,
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A_ORPS,
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A_ANDPD,
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A_ANDPS,
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A_UNPCKLPS,
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A_UNPCKHPS,
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A_SHUFPD,
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A_SHUFPS,
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A_VCOMISD,
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A_VCOMISS:
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replaceoper:=-1;
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A_IMUL:
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if ops<>3 then
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replaceoper:=-1;
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{$ifdef x86_64}
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A_MOV:
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{ 64 bit constants can only be moved into registers }
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if (oper[0]^.typ=top_const) and
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(oper[1]^.typ=top_reg) and
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((oper[0]^.val<low(longint)) or
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(oper[0]^.val>high(longint))) then
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replaceoper:=-1;
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{$endif x86_64}
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end;
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end;
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2 :
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begin
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{ Some 3-op instructions don't allow memory references
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for destination }
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case instr.opcode of
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A_IMUL:
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replaceoper:=-1;
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end;
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end;
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end;
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end;
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end;
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end;
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{$ifdef x86_64}
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{ 32 bit operations on 32 bit registers on x86_64 can result in
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zeroing the upper 32 bits of the register. This does not happen
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with memory operations, so we have to perform these calculations
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in registers. }
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if (instr.opsize=S_L) then
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replaceoper:=-1;
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{$endif x86_64}
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{ Replace register with spill reference }
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if replaceoper<>-1 then
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begin
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if opcode=A_LEA then
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begin
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opcode:=A_ADD;
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oper[0]^.ref^:=spilltemp;
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end
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else
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begin
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is_subh:=getsubreg(oper[replaceoper]^.reg)=R_SUBH;
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oper[replaceoper]^.typ:=top_ref;
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new(oper[replaceoper]^.ref);
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oper[replaceoper]^.ref^:=spilltemp;
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if is_subh then
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inc(oper[replaceoper]^.ref^.offset);
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{ memory locations aren't guaranteed to be aligned }
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case opcode of
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A_MOVAPS:
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opcode:=A_MOVSS;
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A_MOVAPD:
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opcode:=A_MOVSD;
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A_VMOVAPS:
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opcode:=A_VMOVSS;
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A_VMOVAPD:
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opcode:=A_VMOVSD;
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end;
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end;
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result:=true;
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end;
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end;
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end;
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{******************************************************************************
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Trgx86fpu
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******************************************************************************}
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constructor Trgx86fpu.create;
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begin
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used_in_proc:=[];
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unusedregsfpu:=usableregsfpu;
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end;
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function trgx86fpu.getregisterfpu(list: TAsmList) : tregister;
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begin
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{ note: don't return R_ST0, see comments above implementation of }
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{ a_loadfpu_* methods in cgcpu (JM) }
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result:=NR_ST;
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end;
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procedure trgx86fpu.ungetregisterfpu(list : TAsmList; r : tregister);
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begin
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{ nothing to do, fpu stack management is handled by the load/ }
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{ store operations in cgcpu (JM) }
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end;
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function trgx86fpu.correct_fpuregister(r : tregister;ofs : byte) : tregister;
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begin
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correct_fpuregister:=r;
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setsupreg(correct_fpuregister,ofs);
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end;
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procedure trgx86fpu.saveusedfpuregisters(list: TAsmList;
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var saved : tpushedsavedfpu;
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const s: tcpuregisterset);
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{ var
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r : tregister;
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hr : treference; }
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begin
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used_in_proc:=used_in_proc+s;
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{ TODO: firstsavefpureg}
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(*
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{ don't try to save the fpu registers if not desired (e.g. for }
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{ the 80x86) }
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if firstsavefpureg <> R_NO then
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for r.enum:=firstsavefpureg to lastsavefpureg do
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begin
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saved[r.enum].ofs:=reg_not_saved;
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{ if the register is used by the calling subroutine and if }
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{ it's not a regvar (those are handled separately) }
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if not is_reg_var_other[r.enum] and
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(r.enum in s) and
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{ and is present in use }
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not(r.enum in unusedregsfpu) then
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begin
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{ then save it }
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tg.GetTemp(list,extended_size,tt_persistent,hr);
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saved[r.enum].ofs:=hr.offset;
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cg.a_loadfpu_reg_ref(list,OS_FLOAT,OS_FLOAT,r,hr);
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cg.a_reg_dealloc(list,r);
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include(unusedregsfpu,r.enum);
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inc(countunusedregsfpu);
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end;
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end;
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*)
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end;
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procedure trgx86fpu.restoreusedfpuregisters(list : TAsmList;
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const saved : tpushedsavedfpu);
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{
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var
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r,r2 : tregister;
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hr : treference;
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}
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begin
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{ TODO: firstsavefpureg}
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(*
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if firstsavefpureg <> R_NO then
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for r.enum:=lastsavefpureg downto firstsavefpureg do
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begin
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if saved[r.enum].ofs <> reg_not_saved then
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begin
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r2.enum:=R_INTREGISTER;
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r2.number:=NR_FRAME_POINTER_REG;
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reference_reset_base(hr,r2,saved[r.enum].ofs);
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cg.a_reg_alloc(list,r);
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cg.a_loadfpu_ref_reg(list,OS_FLOAT,OS_FLOAT,hr,r);
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if not (r.enum in unusedregsfpu) then
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{ internalerror(10)
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in n386cal we always save/restore the reg *state*
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using save/restoreunusedstate -> the current state
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may not be real (JM) }
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else
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begin
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dec(countunusedregsfpu);
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exclude(unusedregsfpu,r.enum);
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end;
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tg.UnGetTemp(list,hr);
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end;
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end;
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*)
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end;
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(*
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procedure Trgx86fpu.saveotherregvars(list: TAsmList; const s: totherregisterset);
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var
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r: Tregister;
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begin
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if not(cs_opt_regvar in current_settings.optimizerswitches) then
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exit;
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if firstsavefpureg <> NR_NO then
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for r.enum := firstsavefpureg to lastsavefpureg do
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if is_reg_var_other[r.enum] and
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(r.enum in s) then
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store_regvar(list,r);
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end;
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*)
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end.
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