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https://gitlab.com/freepascal.org/fpc/source.git
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785 lines
31 KiB
ObjectPascal
785 lines
31 KiB
ObjectPascal
{
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Copyright (c) 2000-2002 by Florian Klaempfl and Jonas Maebe
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Code generation for add nodes on the PowerPC
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit nppcadd;
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{$i fpcdefs.inc}
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interface
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uses
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node,nadd,ncgadd,ngppcadd,cpubase;
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type
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tppcaddnode = class(tgenppcaddnode)
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procedure pass_generate_code;override;
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protected
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function use_generic_mul32to64: boolean; override;
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private
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procedure emit_compare(unsigned : boolean); override;
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{$ifdef SUPPORT_MMX}
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procedure second_addmmx;override;
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{$endif SUPPORT_MMX}
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procedure second_add64bit;override;
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end;
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implementation
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uses
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globtype,systems,
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cutils,verbose,globals,
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symconst,symdef,paramgr,
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aasmbase,aasmtai,aasmdata,aasmcpu,defutil,htypechk,
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cgbase,cpuinfo,pass_1,pass_2,regvars,
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cpupara,cgcpu,cgutils,procinfo,
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ncon,nset,
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ncgutil,tgobj,rgobj,rgcpu,cgobj,hlcgobj,cg64f32;
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{*****************************************************************************
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Pass 1
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*****************************************************************************}
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function tppcaddnode.use_generic_mul32to64: boolean;
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begin
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result := false;
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end;
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{*****************************************************************************
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Helpers
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*****************************************************************************}
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procedure tppcaddnode.emit_compare(unsigned: boolean);
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var
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op : tasmop;
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tmpreg : tregister;
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useconst : boolean;
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begin
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tmpreg:=NR_NO;
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// get the constant on the right if there is one
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if (left.location.loc = LOC_CONSTANT) then
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swapleftright;
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// can we use an immediate, or do we have to load the
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// constant in a register first?
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if (right.location.loc = LOC_CONSTANT) then
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begin
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{$ifdef dummy}
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if (right.location.size in [OS_64,OS_S64]) and (hi(right.location.value64)<>0) and ((hi(right.location.value64)<>$ffffffff) or unsigned) then
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internalerror(2002080301);
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{$endif extdebug}
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if (nodetype in [equaln,unequaln]) then
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if (unsigned and
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(aword(right.location.value) > high(word))) or
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(not unsigned and
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(aint(right.location.value) < low(smallint)) or
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(aint(right.location.value) > high(smallint))) then
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{ we can then maybe use a constant in the 'othersigned' case
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(the sign doesn't matter for // equal/unequal)}
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unsigned := not unsigned;
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if (unsigned and
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(aword(right.location.value) <= high(word))) or
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(not(unsigned) and
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(aint(right.location.value) >= low(smallint)) and
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(aint(right.location.value) <= high(smallint))) then
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useconst := true
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else
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begin
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useconst := false;
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tmpreg := cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
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cg.a_load_const_reg(current_asmdata.CurrAsmList,OS_INT,
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right.location.value,tmpreg);
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end
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end
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else
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useconst := false;
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location.loc := LOC_FLAGS;
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location.resflags := getresflags;
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if not unsigned then
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if useconst then
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op := A_CMPWI
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else
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op := A_CMPW
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else
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if useconst then
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op := A_CMPLWI
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else
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op := A_CMPLW;
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if (right.location.loc = LOC_CONSTANT) then
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begin
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if useconst then
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_const(op,left.location.register,longint(right.location.value)))
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else
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(op,left.location.register,tmpreg));
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end
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else
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(op,
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left.location.register,right.location.register));
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end;
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{*****************************************************************************
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Add64bit
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*****************************************************************************}
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procedure tppcaddnode.second_add64bit;
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var
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op : TOpCG;
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op1,op2 : TAsmOp;
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cmpop,
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unsigned : boolean;
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procedure emit_cmp64_hi;
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var
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oldleft, oldright: tlocation;
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begin
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// put the high part of the location in the low part
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location_copy(oldleft,left.location);
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location_copy(oldright,right.location);
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if left.location.loc = LOC_CONSTANT then
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left.location.value64 := left.location.value64 shr 32
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else
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left.location.register64.reglo := left.location.register64.reghi;
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if right.location.loc = LOC_CONSTANT then
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right.location.value64 := right.location.value64 shr 32
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else
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right.location.register64.reglo := right.location.register64.reghi;
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// and call the normal emit_compare
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emit_compare(unsigned);
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location_copy(left.location,oldleft);
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location_copy(right.location,oldright);
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end;
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procedure emit_cmp64_lo;
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begin
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emit_compare(true);
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end;
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procedure firstjmp64bitcmp;
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var
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oldnodetype: tnodetype;
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begin
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{$ifdef OLDREGVARS}
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load_all_regvars(current_asmdata.CurrAsmList);
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{$endif OLDREGVARS}
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{ the jump the sequence is a little bit hairy }
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case nodetype of
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ltn,gtn:
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begin
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cg.a_jmp_flags(current_asmdata.CurrAsmList,getresflags,current_procinfo.CurrTrueLabel);
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{ cheat a little bit for the negative test }
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toggleflag(nf_swapped);
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cg.a_jmp_flags(current_asmdata.CurrAsmList,getresflags,current_procinfo.CurrFalseLabel);
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toggleflag(nf_swapped);
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end;
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lten,gten:
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begin
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oldnodetype:=nodetype;
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if nodetype=lten then
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nodetype:=ltn
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else
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nodetype:=gtn;
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cg.a_jmp_flags(current_asmdata.CurrAsmList,getresflags,current_procinfo.CurrTrueLabel);
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{ cheat for the negative test }
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if nodetype=ltn then
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nodetype:=gtn
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else
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nodetype:=ltn;
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cg.a_jmp_flags(current_asmdata.CurrAsmList,getresflags,current_procinfo.CurrFalseLabel);
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nodetype:=oldnodetype;
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end;
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equaln:
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begin
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nodetype := unequaln;
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cg.a_jmp_flags(current_asmdata.CurrAsmList,getresflags,current_procinfo.CurrFalseLabel);
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nodetype := equaln;
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end;
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unequaln:
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begin
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cg.a_jmp_flags(current_asmdata.CurrAsmList,getresflags,current_procinfo.CurrTrueLabel);
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end;
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end;
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end;
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procedure secondjmp64bitcmp;
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begin
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{ the jump the sequence is a little bit hairy }
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case nodetype of
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ltn,gtn,lten,gten:
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begin
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{ the comparison of the low dword always has }
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{ to be always unsigned! }
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cg.a_jmp_flags(current_asmdata.CurrAsmList,getresflags,current_procinfo.CurrTrueLabel);
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cg.a_jmp_always(current_asmdata.CurrAsmList,current_procinfo.CurrFalseLabel);
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end;
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equaln:
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begin
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nodetype := unequaln;
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cg.a_jmp_flags(current_asmdata.CurrAsmList,getresflags,current_procinfo.CurrFalseLabel);
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cg.a_jmp_always(current_asmdata.CurrAsmList,current_procinfo.CurrTrueLabel);
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nodetype := equaln;
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end;
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unequaln:
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begin
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cg.a_jmp_flags(current_asmdata.CurrAsmList,getresflags,current_procinfo.CurrTrueLabel);
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cg.a_jmp_always(current_asmdata.CurrAsmList,current_procinfo.CurrFalseLabel);
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end;
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end;
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end;
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var
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tempreg64: tregister64;
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begin
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firstcomplex(self);
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pass_left_and_right;
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cmpop:=false;
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unsigned:=((left.resultdef.typ=orddef) and
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(torddef(left.resultdef).ordtype=u64bit)) or
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((right.resultdef.typ=orddef) and
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(torddef(right.resultdef).ordtype=u64bit));
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case nodetype of
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addn :
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begin
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op:=OP_ADD;
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end;
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subn :
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begin
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op:=OP_SUB;
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if (nf_swapped in flags) then
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swapleftright;
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end;
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ltn,lten,
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gtn,gten,
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equaln,unequaln:
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begin
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op:=OP_NONE;
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cmpop:=true;
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end;
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xorn:
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op:=OP_XOR;
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orn:
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op:=OP_OR;
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andn:
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op:=OP_AND;
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muln:
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begin
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{ should be handled in pass_1 (JM) }
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if not(torddef(left.resultdef).ordtype in [U32bit,s32bit]) or
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(torddef(left.resultdef).typ <> torddef(right.resultdef).typ) then
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internalerror(200109051);
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{ handled separately }
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op := OP_NONE;
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end;
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else
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internalerror(2002072705);
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end;
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if not cmpop then
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location_reset(location,LOC_REGISTER,def_cgsize(resultdef));
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load_left_right(cmpop,((cs_check_overflow in current_settings.localswitches) and
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(nodetype in [addn,subn])) or (nodetype = muln));
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if (nodetype <> muln) and
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(not(cs_check_overflow in current_settings.localswitches) or
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not(nodetype in [addn,subn])) then
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begin
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case nodetype of
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ltn,lten,
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gtn,gten:
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begin
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emit_cmp64_hi;
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firstjmp64bitcmp;
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emit_cmp64_lo;
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secondjmp64bitcmp;
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end;
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equaln,unequaln:
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begin
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// instead of doing a complicated compare, do
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// (left.hi xor right.hi) or (left.lo xor right.lo)
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// (somewhate optimized so that no superfluous 'mr's are
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// generated)
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if (left.location.loc = LOC_CONSTANT) then
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swapleftright;
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if (right.location.loc = LOC_CONSTANT) then
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begin
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if left.location.loc = LOC_REGISTER then
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begin
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tempreg64.reglo := left.location.register64.reglo;
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tempreg64.reghi := left.location.register64.reghi;
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end
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else
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begin
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if (aint(right.location.value64) <> 0) then
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tempreg64.reglo := cg.getintregister(current_asmdata.CurrAsmList,OS_32)
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else
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tempreg64.reglo := left.location.register64.reglo;
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if ((right.location.value64 shr 32) <> 0) then
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tempreg64.reghi := cg.getintregister(current_asmdata.CurrAsmList,OS_32)
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else
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tempreg64.reghi := left.location.register64.reghi;
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end;
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if (aint(right.location.value64) <> 0) then
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{ negative values can be handled using SUB, }
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{ positive values < 65535 using XOR. }
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if (longint(right.location.value64) >= -32767) and
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(longint(right.location.value64) < 0) then
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SUB,OS_INT,
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aint(right.location.value64),
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left.location.register64.reglo,tempreg64.reglo)
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else
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_XOR,OS_INT,
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aint(right.location.value64),
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left.location.register64.reglo,tempreg64.reglo);
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if ((right.location.value64 shr 32) <> 0) then
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if (longint(right.location.value64 shr 32) >= -32767) and
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(longint(right.location.value64 shr 32) < 0) then
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SUB,OS_INT,
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aint(right.location.value64 shr 32),
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left.location.register64.reghi,tempreg64.reghi)
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else
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_XOR,OS_INT,
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aint(right.location.value64 shr 32),
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left.location.register64.reghi,tempreg64.reghi);
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end
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else
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begin
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tempreg64.reglo := cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
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tempreg64.reghi := cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
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cg64.a_op64_reg_reg_reg(current_asmdata.CurrAsmList,OP_XOR,location.size,
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left.location.register64,right.location.register64,
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tempreg64);
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end;
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cg.a_reg_alloc(current_asmdata.CurrAsmList,NR_R0);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_OR_,NR_R0,
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tempreg64.reglo,tempreg64.reghi));
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cg.a_reg_dealloc(current_asmdata.CurrAsmList,NR_R0);
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location_reset(location,LOC_FLAGS,OS_NO);
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location.resflags := getresflags;
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end;
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xorn,orn,andn,addn:
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begin
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location.register64.reglo := cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
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location.register64.reghi := cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
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if (left.location.loc = LOC_CONSTANT) then
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swapleftright;
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if (right.location.loc = LOC_CONSTANT) then
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cg64.a_op64_const_reg_reg(current_asmdata.CurrAsmList,op,location.size,right.location.value64,
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left.location.register64,location.register64)
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else
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cg64.a_op64_reg_reg_reg(current_asmdata.CurrAsmList,op,location.size,right.location.register64,
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left.location.register64,location.register64);
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end;
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subn:
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begin
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location.register64.reglo := cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
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location.register64.reghi := cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
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if left.location.loc <> LOC_CONSTANT then
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begin
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if right.location.loc <> LOC_CONSTANT then
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// reg64 - reg64
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cg64.a_op64_reg_reg_reg(current_asmdata.CurrAsmList,OP_SUB,location.size,
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right.location.register64,left.location.register64,
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location.register64)
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else
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// reg64 - const64
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cg64.a_op64_const_reg_reg(current_asmdata.CurrAsmList,OP_SUB,location.size,
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right.location.value64,left.location.register64,
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location.register64)
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end
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else if ((left.location.value64 shr 32) = 0) then
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begin
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if (int64(left.location.value64) >= low(smallint)) and
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(int64(left.location.value64) <= high(smallint)) then
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begin
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// consts16 - reg64
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_const(A_SUBFIC,
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location.register64.reglo,right.location.register64.reglo,
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left.location.value));
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end
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else
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begin
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// const32 - reg64
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,
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left.resultdef,u32inttype,true);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_SUBC,
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location.register64.reglo,left.location.register64.reglo,
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right.location.register64.reglo));
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end;
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_SUBFZE,
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location.register64.reghi,right.location.register64.reghi));
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end
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else if (aint(left.location.value64) = 0) then
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begin
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// (const32 shl 32) - reg64
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_const(A_SUBFIC,
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location.register64.reglo,right.location.register64.reglo,0));
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left.location.value64 := left.location.value64 shr 32;
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,u32inttype,true);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_SUBFE,
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location.register64.reghi,right.location.register64.reghi,
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left.location.register));
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end
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else
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begin
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// const64 - reg64
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,
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left.resultdef,left.resultdef,false);
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cg64.a_op64_reg_reg_reg(current_asmdata.CurrAsmList,OP_SUB,location.size,
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right.location.register64,left.location.register64,
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location.register64);
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end;
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end;
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else
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internalerror(2002072803);
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end;
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end
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else
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begin
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if is_signed(resultdef) then
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begin
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case nodetype of
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addn:
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begin
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op1 := A_ADDC;
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op2 := A_ADDEO;
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end;
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subn:
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begin
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op1 := A_SUBC;
|
|
op2 := A_SUBFEO;
|
|
end;
|
|
muln:
|
|
begin
|
|
op1 := A_MULLW;
|
|
op2 := A_MULHW
|
|
end;
|
|
else
|
|
internalerror(2002072806);
|
|
end
|
|
end
|
|
else
|
|
begin
|
|
case nodetype of
|
|
addn:
|
|
begin
|
|
op1 := A_ADDC;
|
|
op2 := A_ADDE;
|
|
end;
|
|
subn:
|
|
begin
|
|
op1 := A_SUBC;
|
|
op2 := A_SUBFE;
|
|
end;
|
|
muln:
|
|
begin
|
|
op1 := A_MULLW;
|
|
op2 := A_MULHWU
|
|
end;
|
|
else
|
|
internalerror(2014082040);
|
|
end;
|
|
end;
|
|
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(op1,location.register64.reglo,
|
|
left.location.register64.reglo,right.location.register64.reglo));
|
|
|
|
if (nodetype <> muln) then
|
|
begin
|
|
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(op2,location.register64.reghi,
|
|
right.location.register64.reghi,left.location.register64.reghi));
|
|
if not(is_signed(resultdef)) then
|
|
if nodetype = addn then
|
|
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_CMPLW,location.register64.reghi,left.location.register64.reghi))
|
|
else
|
|
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_CMPLW,left.location.register64.reghi,location.register64.reghi));
|
|
cg.g_overflowcheck(current_asmdata.CurrAsmList,location,resultdef);
|
|
end
|
|
else
|
|
begin
|
|
{ 32 * 32 -> 64 cannot overflow }
|
|
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(op2,location.register64.reghi,
|
|
left.location.register64.reglo,right.location.register64.reglo));
|
|
end
|
|
end;
|
|
|
|
{ set result location }
|
|
{ (emit_compare sets it to LOC_FLAGS for compares, so set the }
|
|
{ real location only now) (JM) }
|
|
if cmpop and
|
|
not(nodetype in [equaln,unequaln]) then
|
|
location_reset(location,LOC_JUMP,OS_NO);
|
|
end;
|
|
|
|
|
|
{*****************************************************************************
|
|
pass_2
|
|
*****************************************************************************}
|
|
|
|
procedure tppcaddnode.pass_generate_code;
|
|
{ is also being used for xor, and "mul", "sub, or and comparative }
|
|
{ operators }
|
|
var
|
|
cgop : topcg;
|
|
op : tasmop;
|
|
tmpreg : tregister;
|
|
hl : tasmlabel;
|
|
cmpop : boolean;
|
|
{ true, if unsigned types are compared }
|
|
unsigned : boolean;
|
|
checkoverflow : boolean;
|
|
|
|
begin
|
|
{ to make it more readable, string and set (not smallset!) have their
|
|
own procedures }
|
|
case left.resultdef.typ of
|
|
orddef :
|
|
begin
|
|
{ handling boolean expressions }
|
|
if is_boolean(left.resultdef) and
|
|
is_boolean(right.resultdef) then
|
|
begin
|
|
second_addboolean;
|
|
exit;
|
|
end
|
|
{ 64bit operations }
|
|
else if is_64bit(resultdef) or
|
|
is_64bit(left.resultdef) then
|
|
begin
|
|
second_add64bit;
|
|
exit;
|
|
end;
|
|
end;
|
|
stringdef :
|
|
begin
|
|
internalerror(2002072402);
|
|
exit;
|
|
end;
|
|
setdef :
|
|
begin
|
|
{ normalsets are already handled in pass1 }
|
|
if not is_smallset(left.resultdef) then
|
|
internalerror(200109042);
|
|
second_addsmallset;
|
|
exit;
|
|
end;
|
|
arraydef :
|
|
begin
|
|
{$ifdef SUPPORT_MMX}
|
|
if is_mmx_able_array(left.resultdef) then
|
|
begin
|
|
second_addmmx;
|
|
exit;
|
|
end;
|
|
{$endif SUPPORT_MMX}
|
|
end;
|
|
floatdef :
|
|
begin
|
|
second_addfloat;
|
|
exit;
|
|
end;
|
|
end;
|
|
|
|
{ defaults }
|
|
cmpop:=nodetype in [ltn,lten,gtn,gten,equaln,unequaln];
|
|
unsigned:=not(is_signed(left.resultdef)) or
|
|
not(is_signed(right.resultdef));
|
|
|
|
pass_left_and_right;
|
|
|
|
{ Convert flags to register first }
|
|
{ can any of these things be in the flags actually?? (JM) }
|
|
|
|
if (left.location.loc = LOC_FLAGS) or
|
|
(right.location.loc = LOC_FLAGS) then
|
|
internalerror(2002072602);
|
|
|
|
{ set result location }
|
|
if not cmpop then
|
|
location_reset(location,LOC_REGISTER,def_cgsize(resultdef))
|
|
else
|
|
location_reset(location,LOC_FLAGS,OS_NO);
|
|
|
|
checkoverflow:=
|
|
(nodetype in [addn,subn,muln]) and
|
|
(cs_check_overflow in current_settings.localswitches) and
|
|
(left.resultdef.typ<>pointerdef) and
|
|
(right.resultdef.typ<>pointerdef);
|
|
|
|
load_left_right(cmpop, checkoverflow);
|
|
|
|
if not(cmpop) then
|
|
location.register := cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
|
|
|
|
if not(checkoverflow) then
|
|
begin
|
|
case nodetype of
|
|
addn, muln, xorn, orn, andn:
|
|
begin
|
|
case nodetype of
|
|
addn:
|
|
cgop := OP_ADD;
|
|
muln:
|
|
if unsigned then
|
|
cgop := OP_MUL
|
|
else
|
|
cgop := OP_IMUL;
|
|
xorn:
|
|
cgop := OP_XOR;
|
|
orn:
|
|
cgop := OP_OR;
|
|
andn:
|
|
cgop := OP_AND;
|
|
else
|
|
internalerror(2014082041);
|
|
end;
|
|
if (left.location.loc = LOC_CONSTANT) then
|
|
swapleftright;
|
|
if (right.location.loc <> LOC_CONSTANT) then
|
|
cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList,cgop,OS_INT,
|
|
left.location.register,right.location.register,
|
|
location.register)
|
|
else
|
|
cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,cgop,OS_INT,
|
|
right.location.value,left.location.register,
|
|
location.register);
|
|
end;
|
|
subn:
|
|
begin
|
|
if (nf_swapped in flags) then
|
|
swapleftright;
|
|
if left.location.loc <> LOC_CONSTANT then
|
|
if right.location.loc <> LOC_CONSTANT then
|
|
cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList,OP_SUB,OS_INT,
|
|
right.location.register,left.location.register,
|
|
location.register)
|
|
else
|
|
cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SUB,OS_INT,
|
|
right.location.value,left.location.register,
|
|
location.register)
|
|
else
|
|
if (longint(left.location.value) >= low(smallint)) and
|
|
(longint(left.location.value) <= high(smallint)) then
|
|
begin
|
|
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_const(A_SUBFIC,
|
|
location.register,right.location.register,
|
|
longint(left.location.value)));
|
|
end
|
|
else
|
|
begin
|
|
tmpreg := cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
|
|
cg.a_load_const_reg(current_asmdata.CurrAsmList,OS_INT,
|
|
left.location.value,tmpreg);
|
|
cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList,OP_SUB,OS_INT,
|
|
right.location.register,tmpreg,location.register);
|
|
end;
|
|
end;
|
|
ltn,lten,gtn,gten,equaln,unequaln :
|
|
begin
|
|
emit_compare(unsigned);
|
|
end;
|
|
end;
|
|
end
|
|
else
|
|
// overflow checking is on and we have an addn, subn or muln
|
|
begin
|
|
if is_signed(resultdef) then
|
|
begin
|
|
case nodetype of
|
|
addn:
|
|
op := A_ADDO;
|
|
subn:
|
|
begin
|
|
op := A_SUBO;
|
|
if (nf_swapped in flags) then
|
|
swapleftright;
|
|
end;
|
|
muln:
|
|
op := A_MULLWO;
|
|
else
|
|
internalerror(2002072601);
|
|
end;
|
|
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(op,location.register,
|
|
left.location.register,right.location.register));
|
|
cg.g_overflowcheck(current_asmdata.CurrAsmList,location,resultdef);
|
|
end
|
|
else
|
|
begin
|
|
case nodetype of
|
|
addn:
|
|
begin
|
|
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_ADD,location.register,
|
|
left.location.register,right.location.register));
|
|
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_CMPLW,location.register,left.location.register));
|
|
cg.g_overflowcheck(current_asmdata.CurrAsmList,location,resultdef);
|
|
end;
|
|
subn:
|
|
begin
|
|
if nf_swapped in flags then
|
|
swapleftright;
|
|
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_SUB,location.register,
|
|
left.location.register,right.location.register));
|
|
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_CMPLW,left.location.register,location.register));
|
|
cg.g_overflowcheck(current_asmdata.CurrAsmList,location,resultdef);
|
|
end;
|
|
muln:
|
|
begin
|
|
{ calculate the upper 32 bits of the product, = 0 if no overflow }
|
|
cg.a_reg_alloc(current_asmdata.CurrAsmList,NR_R0);
|
|
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_MULHWU_,NR_R0,
|
|
left.location.register,right.location.register));
|
|
cg.a_reg_dealloc(current_asmdata.CurrAsmList,NR_R0);
|
|
{ calculate the real result }
|
|
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_MULLW,location.register,
|
|
left.location.register,right.location.register));
|
|
{ g_overflowcheck generates a OC_AE instead of OC_EQ :/ }
|
|
current_asmdata.getjumplabel(hl);
|
|
tcgppc(cg).a_jmp_cond(current_asmdata.CurrAsmList,OC_EQ,hl);
|
|
cg.a_call_name(current_asmdata.CurrAsmList,'FPC_OVERFLOW',false);
|
|
cg.a_label(current_asmdata.CurrAsmList,hl);
|
|
end;
|
|
end;
|
|
end;
|
|
end;
|
|
end;
|
|
|
|
begin
|
|
caddnode:=tppcaddnode;
|
|
end.
|