mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-10-31 03:53:57 +01:00
55669f62b1
Made absolutevarsym use PUint instead of AWord for its offset to fix range errors. git-svn-id: trunk@31242 -
309 lines
12 KiB
ObjectPascal
309 lines
12 KiB
ObjectPascal
unit ATtiny2313;
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{$goto on}
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interface
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var
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// PORTB
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PORTB : byte absolute $00+$38; // Port B Data Register
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DDRB : byte absolute $00+$37; // Port B Data Direction Register
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PINB : byte absolute $00+$36; // Port B Input Pins
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// TIMER_COUNTER_0
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TIMSK : byte absolute $00+$59; // Timer/Counter Interrupt Mask Register
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TIFR : byte absolute $00+$58; // Timer/Counter Interrupt Flag register
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OCR0B : byte absolute $00+$5C; // Timer/Counter0 Output Compare Register
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OCR0A : byte absolute $00+$56; // Timer/Counter0 Output Compare Register
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TCCR0A : byte absolute $00+$50; // Timer/Counter Control Register A
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TCNT0 : byte absolute $00+$52; // Timer/Counter0
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TCCR0B : byte absolute $00+$53; // Timer/Counter Control Register B
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// TIMER_COUNTER_1
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TCCR1A : byte absolute $00+$4F; // Timer/Counter1 Control Register A
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TCCR1B : byte absolute $00+$4E; // Timer/Counter1 Control Register B
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TCCR1C : byte absolute $00+$42; // Timer/Counter1 Control Register C
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TCNT1 : word absolute $00+$4C; // Timer/Counter1 Bytes
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TCNT1L : byte absolute $00+$4C; // Timer/Counter1 Bytes
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TCNT1H : byte absolute $00+$4C+1; // Timer/Counter1 Bytes
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OCR1A : word absolute $00+$4A; // Timer/Counter1 Output Compare Register Bytes
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OCR1AL : byte absolute $00+$4A; // Timer/Counter1 Output Compare Register Bytes
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OCR1AH : byte absolute $00+$4A+1; // Timer/Counter1 Output Compare Register Bytes
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OCR1B : word absolute $00+$48; // Timer/Counter1 Output Compare Register Bytes
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OCR1BL : byte absolute $00+$48; // Timer/Counter1 Output Compare Register Bytes
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OCR1BH : byte absolute $00+$48+1; // Timer/Counter1 Output Compare Register Bytes
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ICR1 : word absolute $00+$44; // Timer/Counter1 Input Capture Register Bytes
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ICR1L : byte absolute $00+$44; // Timer/Counter1 Input Capture Register Bytes
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ICR1H : byte absolute $00+$44+1; // Timer/Counter1 Input Capture Register Bytes
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// WATCHDOG
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WDTCR : byte absolute $00+$41; // Watchdog Timer Control Register
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// EXTERNAL_INTERRUPT
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GIMSK : byte absolute $00+$5B; // General Interrupt Mask Register
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EIFR : byte absolute $00+$5A; // Extended Interrupt Flag Register
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// USART
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UDR : byte absolute $00+$2C; // USART I/O Data Register
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UCSRA : byte absolute $00+$02B; // USART Control and Status Register A
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UCSRB : byte absolute $00+$02A; // USART Control and Status Register B
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UCSRC : byte absolute $00+$23; // USART Control and Status Register C
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UBRRH : byte absolute $00+$22; // USART Baud Rate Register High Byte
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UBRRL : byte absolute $00+$29; // USART Baud Rate Register Low Byte
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// ANALOG_COMPARATOR
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ACSR : byte absolute $00+$28; // Analog Comparator Control And Status Register
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DIDR : byte absolute $00+$21; // Digital Input Disable Register 1
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// PORTD
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PORTD : byte absolute $00+$32; // Data Register, Port D
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DDRD : byte absolute $00+$31; // Data Direction Register, Port D
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PIND : byte absolute $00+$30; // Input Pins, Port D
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// EEPROM
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EEAR : byte absolute $00+$3E; // EEPROM Read/Write Access
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EEDR : byte absolute $00+$3D; // EEPROM Data Register
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EECR : byte absolute $00+$3C; // EEPROM Control Register
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// PORTA
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PORTA : byte absolute $00+$3B; // Port A Data Register
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DDRA : byte absolute $00+$3A; // Port A Data Direction Register
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PINA : byte absolute $00+$39; // Port A Input Pins
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// CPU
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SREG : byte absolute $00+$5F; // Status Register
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SPL : byte absolute $00+$5D; // Stack Pointer Low Byte
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SPMCSR : byte absolute $00+$57; // Store Program Memory Control and Status register
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MCUCR : byte absolute $00+$55; // MCU Control Register
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MCUSR : byte absolute $00+$54; // MCU Status register
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OSCCAL : byte absolute $00+$51; // Oscillator Calibration Register
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CLKPR : byte absolute $00+$46; // Clock Prescale Register
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GTCCR : byte absolute $00+$43; // General Timer Counter Control Register
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PCMSK : byte absolute $00+$40; // Pin-Change Mask register
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GPIOR2 : byte absolute $00+$35; // General Purpose I/O Register 2
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GPIOR1 : byte absolute $00+$34; // General Purpose I/O Register 1
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GPIOR0 : byte absolute $00+$33; // General Purpose I/O Register 0
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// USI
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USIDR : byte absolute $00+$2F; // USI Data Register
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USISR : byte absolute $00+$2E; // USI Status Register
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USICR : byte absolute $00+$2D; // USI Control Register
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const
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// TIMSK
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OCIE0B = 2; // Timer/Counter0 Output Compare Match B Interrupt Enable
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TOIE0 = 1; // Timer/Counter0 Overflow Interrupt Enable
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OCIE0A = 0; // Timer/Counter0 Output Compare Match A Interrupt Enable
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// TIFR
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OCF0B = 2; // Timer/Counter0 Output Compare Flag 0B
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TOV0 = 1; // Timer/Counter0 Overflow Flag
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OCF0A = 0; // Timer/Counter0 Output Compare Flag 0A
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// TCCR0A
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COM0A = 6; // Compare Match Output A Mode
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COM0B = 4; // Compare Match Output B Mode
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WGM0 = 0; // Waveform Generation Mode
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// TCCR0B
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FOC0A = 7; // Force Output Compare B
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FOC0B = 6; // Force Output Compare B
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WGM02 = 3; //
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CS0 = 0; // Clock Select
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// TIMSK
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TOIE1 = 7; // Timer/Counter1 Overflow Interrupt Enable
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OCIE1A = 6; // Timer/Counter1 Output CompareA Match Interrupt Enable
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OCIE1B = 5; // Timer/Counter1 Output CompareB Match Interrupt Enable
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ICIE1 = 3; // Timer/Counter1 Input Capture Interrupt Enable
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// TIFR
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TOV1 = 7; // Timer/Counter1 Overflow Flag
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OCF1A = 6; // Output Compare Flag 1A
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OCF1B = 5; // Output Compare Flag 1B
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ICF1 = 3; // Input Capture Flag 1
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// TCCR1A
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COM1A = 6; // Compare Output Mode 1A, bits
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COM1B = 4; // Compare Output Mode 1B, bits
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WGM1 = 0; // Pulse Width Modulator Select Bits
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// TCCR1B
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ICNC1 = 7; // Input Capture 1 Noise Canceler
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ICES1 = 6; // Input Capture 1 Edge Select
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CS1 = 0; // Clock Select1 bits
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// TCCR1C
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FOC1A = 7; // Force Output Compare for Channel A
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FOC1B = 6; // Force Output Compare for Channel B
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// WDTCR
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WDIF = 7; // Watchdog Timeout Interrupt Flag
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WDIE = 6; // Watchdog Timeout Interrupt Enable
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WDP = 0; // Watchdog Timer Prescaler Bits
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WDCE = 4; // Watchdog Change Enable
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WDE = 3; // Watch Dog Enable
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// GIMSK
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INT = 6; // External Interrupt Request 1 Enable
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PCIE = 5; //
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// EIFR
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INTF = 6; // External Interrupt Flags
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PCIF = 5; //
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// UCSRA
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RXC = 7; // USART Receive Complete
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TXC = 6; // USART Transmitt Complete
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UDRE = 5; // USART Data Register Empty
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FE = 4; // Framing Error
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DOR = 3; // Data overRun
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UPE = 2; // USART Parity Error
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U2X = 1; // Double the USART Transmission Speed
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MPCM = 0; // Multi-processor Communication Mode
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// UCSRB
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RXCIE = 7; // RX Complete Interrupt Enable
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TXCIE = 6; // TX Complete Interrupt Enable
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UDRIE = 5; // USART Data register Empty Interrupt Enable
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RXEN = 4; // Receiver Enable
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TXEN = 3; // Transmitter Enable
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UCSZ2 = 2; // Character Size
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RXB8 = 1; // Receive Data Bit 8
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TXB8 = 0; // Transmit Data Bit 8
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// UCSRC
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UMSEL = 6; // USART Mode Select
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UPM = 4; // Parity Mode Bits
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USBS = 3; // Stop Bit Select
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UCSZ = 1; // Character Size Bits
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UCPOL = 0; // Clock Polarity
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// ACSR
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ACD = 7; // Analog Comparator Disable
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ACBG = 6; // Analog Comparator Bandgap Select
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ACO = 5; // Analog Compare Output
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ACI = 4; // Analog Comparator Interrupt Flag
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ACIE = 3; // Analog Comparator Interrupt Enable
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ACIC = 2; //
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ACIS = 0; // Analog Comparator Interrupt Mode Select bits
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// EECR
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EEPM = 4; //
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EERIE = 3; // EEProm Ready Interrupt Enable
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EEMPE = 2; // EEPROM Master Write Enable
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EEPE = 1; // EEPROM Write Enable
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EERE = 0; // EEPROM Read Enable
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// SREG
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I = 7; // Global Interrupt Enable
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T = 6; // Bit Copy Storage
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H = 5; // Half Carry Flag
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S = 4; // Sign Bit
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V = 3; // Two's Complement Overflow Flag
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N = 2; // Negative Flag
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Z = 1; // Zero Flag
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C = 0; // Carry Flag
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// SPMCSR
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CTPB = 4; // Clear Temporary Page Buffer
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RFLB = 3; // Read Fuse and Lock Bits
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PGWRT = 2; // Page Write
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PGERS = 1; // Page Erase
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SPMEN = 0; // Store Program Memory Enable
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// MCUCR
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PUD = 7; // Pull-up Disable
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SM = 4; // Sleep Mode Select Bits
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SE = 5; // Sleep Enable
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ISC1 = 2; // Interrupt Sense Control 1 bits
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ISC0 = 0; // Interrupt Sense Control 0 bits
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// MCUSR
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WDRF = 3; // Watchdog Reset Flag
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BORF = 2; // Brown-out Reset Flag
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EXTRF = 1; // External Reset Flag
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PORF = 0; // Power-On Reset Flag
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// CLKPR
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CLKPCE = 7; // Clock Prescaler Change Enable
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CLKPS = 0; // Clock Prescaler Select Bits
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// GTCCR
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PSR10 = 0; //
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// USISR
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USISIF = 7; // Start Condition Interrupt Flag
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USIOIF = 6; // Counter Overflow Interrupt Flag
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USIPF = 5; // Stop Condition Flag
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USIDC = 4; // Data Output Collision
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USICNT = 0; // USI Counter Value Bits
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// USICR
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USISIE = 7; // Start Condition Interrupt Enable
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USIOIE = 6; // Counter Overflow Interrupt Enable
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USIWM = 4; // USI Wire Mode Bits
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USICS = 2; // USI Clock Source Select Bits
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USICLK = 1; // Clock Strobe
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USITC = 0; // Toggle Clock Port Pin
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implementation
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{$define RELBRANCHES}
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{$i avrcommon.inc}
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procedure INT0_ISR; external name 'INT0_ISR'; // Interrupt 1 External Interrupt Request 0
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procedure INT1_ISR; external name 'INT1_ISR'; // Interrupt 2 External Interrupt Request 1
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procedure TIMER1_CAPT_ISR; external name 'TIMER1_CAPT_ISR'; // Interrupt 3 Timer/Counter1 Capture Event
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procedure TIMER1_COMPA_ISR; external name 'TIMER1_COMPA_ISR'; // Interrupt 4 Timer/Counter1 Compare Match A
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procedure TIMER1_OVF_ISR; external name 'TIMER1_OVF_ISR'; // Interrupt 5 Timer/Counter1 Overflow
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procedure TIMER0_OVF_ISR; external name 'TIMER0_OVF_ISR'; // Interrupt 6 Timer/Counter0 Overflow
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procedure USART__RX_ISR; external name 'USART__RX_ISR'; // Interrupt 7 USART, Rx Complete
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procedure USART__UDRE_ISR; external name 'USART__UDRE_ISR'; // Interrupt 8 USART Data Register Empty
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procedure USART__TX_ISR; external name 'USART__TX_ISR'; // Interrupt 9 USART, Tx Complete
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procedure ANA_COMP_ISR; external name 'ANA_COMP_ISR'; // Interrupt 10 Analog Comparator
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procedure PCINT_ISR; external name 'PCINT_ISR'; // Interrupt 11
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procedure TIMER1_COMPB_ISR; external name 'TIMER1_COMPB_ISR'; // Interrupt 12
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procedure TIMER0_COMPA_ISR; external name 'TIMER0_COMPA_ISR'; // Interrupt 13
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procedure TIMER0_COMPB_ISR; external name 'TIMER0_COMPB_ISR'; // Interrupt 14
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procedure USI_START_ISR; external name 'USI_START_ISR'; // Interrupt 15 USI Start Condition
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procedure USI_OVERFLOW_ISR; external name 'USI_OVERFLOW_ISR'; // Interrupt 16 USI Overflow
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procedure EEPROM_Ready_ISR; external name 'EEPROM_Ready_ISR'; // Interrupt 17
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procedure WDT_OVERFLOW_ISR; external name 'WDT_OVERFLOW_ISR'; // Interrupt 18 Watchdog Timer Overflow
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procedure _FPC_start; assembler; nostackframe;
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label
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_start;
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asm
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.init
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.globl _start
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rjmp _start
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rjmp INT0_ISR
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rjmp INT1_ISR
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rjmp TIMER1_CAPT_ISR
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rjmp TIMER1_COMPA_ISR
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rjmp TIMER1_OVF_ISR
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rjmp TIMER0_OVF_ISR
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rjmp USART__RX_ISR
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rjmp USART__UDRE_ISR
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rjmp USART__TX_ISR
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rjmp ANA_COMP_ISR
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rjmp PCINT_ISR
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rjmp TIMER1_COMPB_ISR
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rjmp TIMER0_COMPA_ISR
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rjmp TIMER0_COMPB_ISR
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rjmp USI_START_ISR
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rjmp USI_OVERFLOW_ISR
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rjmp EEPROM_Ready_ISR
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rjmp WDT_OVERFLOW_ISR
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{$i start.inc}
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.weak INT0_ISR
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.weak INT1_ISR
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.weak TIMER1_CAPT_ISR
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.weak TIMER1_COMPA_ISR
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.weak TIMER1_OVF_ISR
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.weak TIMER0_OVF_ISR
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.weak USART__RX_ISR
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.weak USART__UDRE_ISR
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.weak USART__TX_ISR
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.weak ANA_COMP_ISR
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.weak PCINT_ISR
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.weak TIMER1_COMPB_ISR
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.weak TIMER0_COMPA_ISR
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.weak TIMER0_COMPB_ISR
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.weak USI_START_ISR
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.weak USI_OVERFLOW_ISR
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.weak EEPROM_Ready_ISR
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.weak WDT_OVERFLOW_ISR
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.set INT0_ISR, Default_IRQ_handler
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.set INT1_ISR, Default_IRQ_handler
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.set TIMER1_CAPT_ISR, Default_IRQ_handler
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.set TIMER1_COMPA_ISR, Default_IRQ_handler
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.set TIMER1_OVF_ISR, Default_IRQ_handler
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.set TIMER0_OVF_ISR, Default_IRQ_handler
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.set USART__RX_ISR, Default_IRQ_handler
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.set USART__UDRE_ISR, Default_IRQ_handler
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.set USART__TX_ISR, Default_IRQ_handler
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.set ANA_COMP_ISR, Default_IRQ_handler
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.set PCINT_ISR, Default_IRQ_handler
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.set TIMER1_COMPB_ISR, Default_IRQ_handler
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.set TIMER0_COMPA_ISR, Default_IRQ_handler
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.set TIMER0_COMPB_ISR, Default_IRQ_handler
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.set USI_START_ISR, Default_IRQ_handler
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.set USI_OVERFLOW_ISR, Default_IRQ_handler
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.set EEPROM_Ready_ISR, Default_IRQ_handler
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.set WDT_OVERFLOW_ISR, Default_IRQ_handler
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end;
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end.
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