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528 lines
17 KiB
ObjectPascal
528 lines
17 KiB
ObjectPascal
{
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Copyright (c) 1998-2002 by Florian Klaempfl and Peter Vreman
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Contains the base types for the ARM
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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{# Base unit for processor information. This unit contains
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enumerations of registers, opcodes, sizes, and other
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such things which are processor specific.
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}
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unit cpubase;
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{$i fpcdefs.inc}
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interface
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uses
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cutils,cclasses,
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globtype,globals,
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cpuinfo,
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aasmbase,
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cgbase
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;
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{*****************************************************************************
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Assembler Opcodes
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*****************************************************************************}
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type
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TAsmOp= {$i armop.inc}
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{ This should define the array of instructions as string }
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op2strtable=array[tasmop] of string[11];
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const
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{ First value of opcode enumeration }
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firstop = low(tasmop);
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{ Last value of opcode enumeration }
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lastop = high(tasmop);
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{*****************************************************************************
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Registers
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*****************************************************************************}
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type
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{ Number of registers used for indexing in tables }
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tregisterindex=0..{$i rarmnor.inc}-1;
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const
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{ Available Superregisters }
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{$i rarmsup.inc}
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RS_PC = RS_R15;
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{ No Subregisters }
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R_SUBWHOLE = R_SUBNONE;
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{ Available Registers }
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{$i rarmcon.inc}
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{ aliases }
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NR_PC = NR_R15;
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{ Integer Super registers first and last }
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first_int_supreg = RS_R0;
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first_int_imreg = $10;
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{ Float Super register first and last }
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first_fpu_supreg = RS_F0;
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first_fpu_imreg = $08;
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{ MM Super register first and last }
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first_mm_supreg = RS_S0;
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first_mm_imreg = $20;
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{$warning TODO Calculate bsstart}
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regnumber_count_bsstart = 64;
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regnumber_table : array[tregisterindex] of tregister = (
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{$i rarmnum.inc}
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);
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regstabs_table : array[tregisterindex] of shortint = (
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{$i rarmsta.inc}
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);
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regdwarf_table : array[tregisterindex] of shortint = (
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{$i rarmdwa.inc}
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);
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{ registers which may be destroyed by calls }
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VOLATILE_INTREGISTERS = [RS_R0..RS_R3,RS_R12..RS_R15];
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VOLATILE_FPUREGISTERS = [RS_F0..RS_F3];
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type
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totherregisterset = set of tregisterindex;
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{*****************************************************************************
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Instruction post fixes
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*****************************************************************************}
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type
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{ ARM instructions load/store and arithmetic instructions
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can have several instruction post fixes which are collected
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in this enumeration
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}
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TOpPostfix = (PF_None,
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{ update condition flags
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or floating point single }
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PF_S,
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{ floating point size }
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PF_D,PF_E,PF_P,PF_EP,
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{ load/store }
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PF_B,PF_SB,PF_BT,PF_H,PF_SH,PF_T,
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{ multiple load/store address modes }
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PF_IA,PF_IB,PF_DA,PF_DB,PF_FD,PF_FA,PF_ED,PF_EA
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);
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TRoundingMode = (RM_None,RM_P,RM_M,RM_Z);
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const
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cgsize2fpuoppostfix : array[OS_NO..OS_F128] of toppostfix = (
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PF_None,
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PF_None,PF_None,PF_None,PF_None,PF_None,PF_None,PF_None,PF_None,PF_None,PF_None,
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PF_S,PF_D,PF_E,PF_None,PF_None);
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oppostfix2str : array[TOpPostfix] of string[2] = ('',
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's',
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'd','e','p','ep',
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'b','sb','bt','h','sh','t',
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'ia','ib','da','db','fd','fa','ed','ea');
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roundingmode2str : array[TRoundingMode] of string[1] = ('',
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'p','m','z');
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{*****************************************************************************
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Conditions
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*****************************************************************************}
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type
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TAsmCond=(C_None,
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C_EQ,C_NE,C_CS,C_CC,C_MI,C_PL,C_VS,C_VC,C_HI,C_LS,
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C_GE,C_LT,C_GT,C_LE,C_AL,C_NV
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);
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const
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cond2str : array[TAsmCond] of string[2]=('',
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'eq','ne','cs','cc','mi','pl','vs','vc','hi','ls',
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'ge','lt','gt','le','al','nv'
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);
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uppercond2str : array[TAsmCond] of string[2]=('',
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'EQ','NE','CS','CC','MI','PL','VS','VC','HI','LS',
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'GE','LT','GT','LE','AL','NV'
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);
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{*****************************************************************************
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Flags
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*****************************************************************************}
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type
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TResFlags = (F_EQ,F_NE,F_CS,F_CC,F_MI,F_PL,F_VS,F_VC,F_HI,F_LS,
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F_GE,F_LT,F_GT,F_LE);
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{*****************************************************************************
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Operands
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*****************************************************************************}
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taddressmode = (AM_OFFSET,AM_PREINDEXED,AM_POSTINDEXED);
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tshiftmode = (SM_None,SM_LSL,SM_LSR,SM_ASR,SM_ROR,SM_RRX);
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tupdatereg = (UR_None,UR_Update);
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pshifterop = ^tshifterop;
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tshifterop = record
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shiftmode : tshiftmode;
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rs : tregister;
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shiftimm : byte;
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end;
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{*****************************************************************************
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Constants
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*****************************************************************************}
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const
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max_operands = 4;
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{# Constant defining possibly all registers which might require saving }
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ALL_OTHERREGISTERS = [];
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general_superregisters = [RS_R0..RS_PC];
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{# Table of registers which can be allocated by the code generator
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internally, when generating the code.
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}
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{ legend: }
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{ xxxregs = set of all possibly used registers of that type in the code }
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{ generator }
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{ usableregsxxx = set of all 32bit components of registers that can be }
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{ possible allocated to a regvar or using getregisterxxx (this }
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{ excludes registers which can be only used for parameter }
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{ passing on ABI's that define this) }
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{ c_countusableregsxxx = amount of registers in the usableregsxxx set }
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maxintregs = 15;
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{ to determine how many registers to use for regvars }
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maxintscratchregs = 3;
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usableregsint = [RS_R4..RS_R10];
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c_countusableregsint = 7;
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maxfpuregs = 8;
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fpuregs = [RS_F0..RS_F7];
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usableregsfpu = [RS_F4..RS_F7];
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c_countusableregsfpu = 4;
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mmregs = [RS_D0..RS_D15];
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usableregsmm = [RS_D8..RS_D15];
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c_countusableregsmm = 8;
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maxaddrregs = 0;
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addrregs = [];
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usableregsaddr = [];
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c_countusableregsaddr = 0;
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{*****************************************************************************
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Operand Sizes
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*****************************************************************************}
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type
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topsize = (S_NO,
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S_B,S_W,S_L,S_BW,S_BL,S_WL,
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S_IS,S_IL,S_IQ,
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S_FS,S_FL,S_FX,S_D,S_Q,S_FV,S_FXX
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);
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{*****************************************************************************
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Constants
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*****************************************************************************}
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const
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firstsaveintreg = RS_R4;
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lastsaveintreg = RS_R10;
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firstsavefpureg = RS_F4;
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lastsavefpureg = RS_F7;
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firstsavemmreg = RS_D8;
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lastsavemmreg = RS_D15;
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maxvarregs = 7;
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varregs : Array [1..maxvarregs] of tsuperregister =
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(RS_R4,RS_R5,RS_R6,RS_R7,RS_R8,RS_R9,RS_R10);
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maxfpuvarregs = 4;
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fpuvarregs : Array [1..maxfpuvarregs] of tsuperregister =
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(RS_F4,RS_F5,RS_F6,RS_F7);
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{*****************************************************************************
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Default generic sizes
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*****************************************************************************}
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{ Defines the default address size for a processor, }
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OS_ADDR = OS_32;
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{ the natural int size for a processor, }
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OS_INT = OS_32;
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OS_SINT = OS_S32;
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{ the maximum float size for a processor, }
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OS_FLOAT = OS_F64;
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{ the size of a vector register for a processor }
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OS_VECTOR = OS_M32;
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{*****************************************************************************
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Generic Register names
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*****************************************************************************}
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{ Stack pointer register }
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NR_STACK_POINTER_REG = NR_R13;
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RS_STACK_POINTER_REG = RS_R13;
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{ Frame pointer register }
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RS_FRAME_POINTER_REG = RS_R11;
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NR_FRAME_POINTER_REG = NR_R11;
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{ Register for addressing absolute data in a position independant way,
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such as in PIC code. The exact meaning is ABI specific. For
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further information look at GCC source : PIC_OFFSET_TABLE_REGNUM
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}
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NR_PIC_OFFSET_REG = NR_R9;
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{ Results are returned in this register (32-bit values) }
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NR_FUNCTION_RETURN_REG = NR_R0;
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RS_FUNCTION_RETURN_REG = RS_R0;
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{ Low part of 64bit return value }
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NR_FUNCTION_RETURN64_LOW_REG = NR_R0;
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RS_FUNCTION_RETURN64_LOW_REG = RS_R0;
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{ High part of 64bit return value }
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NR_FUNCTION_RETURN64_HIGH_REG = NR_R1;
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RS_FUNCTION_RETURN64_HIGH_REG = RS_R1;
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{ The value returned from a function is available in this register }
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NR_FUNCTION_RESULT_REG = NR_FUNCTION_RETURN_REG;
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RS_FUNCTION_RESULT_REG = RS_FUNCTION_RETURN_REG;
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{ The lowh part of 64bit value returned from a function }
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NR_FUNCTION_RESULT64_LOW_REG = NR_FUNCTION_RETURN64_LOW_REG;
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RS_FUNCTION_RESULT64_LOW_REG = RS_FUNCTION_RETURN64_LOW_REG;
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{ The high part of 64bit value returned from a function }
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NR_FUNCTION_RESULT64_HIGH_REG = NR_FUNCTION_RETURN64_HIGH_REG;
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RS_FUNCTION_RESULT64_HIGH_REG = RS_FUNCTION_RETURN64_HIGH_REG;
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NR_FPU_RESULT_REG = NR_F0;
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NR_MM_RESULT_REG = NR_NO;
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NR_RETURN_ADDRESS_REG = NR_FUNCTION_RETURN_REG;
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{ Offset where the parent framepointer is pushed }
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PARENT_FRAMEPOINTER_OFFSET = 0;
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{*****************************************************************************
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GCC /ABI linking information
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*****************************************************************************}
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const
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{ Registers which must be saved when calling a routine declared as
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cppdecl, cdecl, stdcall, safecall, palmossyscall. The registers
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saved should be the ones as defined in the target ABI and / or GCC.
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This value can be deduced from the CALLED_USED_REGISTERS array in the
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GCC source.
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}
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saved_standard_registers : array[0..6] of tsuperregister =
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(RS_R4,RS_R5,RS_R6,RS_R7,RS_R8,RS_R9,RS_R10);
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{ Required parameter alignment when calling a routine declared as
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stdcall and cdecl. The alignment value should be the one defined
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by GCC or the target ABI.
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The value of this constant is equal to the constant
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PARM_BOUNDARY / BITS_PER_UNIT in the GCC source.
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}
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std_param_align = 4;
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{*****************************************************************************
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Helpers
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*****************************************************************************}
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{ Returns the tcgsize corresponding with the size of reg.}
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function reg_cgsize(const reg: tregister) : tcgsize;
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function cgsize2subreg(s:Tcgsize):Tsubregister;
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function is_calljmp(o:tasmop):boolean;
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procedure inverse_flags(var f: TResFlags);
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function flags_to_cond(const f: TResFlags) : TAsmCond;
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function findreg_by_number(r:Tregister):tregisterindex;
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function std_regnum_search(const s:string):Tregister;
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function std_regname(r:Tregister):string;
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function inverse_cond(const c: TAsmCond): TAsmCond; {$ifdef USEINLINE}inline;{$endif USEINLINE}
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function conditions_equal(const c1, c2: TAsmCond): boolean; {$ifdef USEINLINE}inline;{$endif USEINLINE}
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procedure shifterop_reset(var so : tshifterop);
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function is_pc(const r : tregister) : boolean;
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function is_shifter_const(d : aint;var imm_shift : byte) : boolean;
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function dwarf_reg(r:tregister):shortint;
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implementation
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uses
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rgBase,verbose;
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const
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std_regname_table : array[tregisterindex] of string[7] = (
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{$i rarmstd.inc}
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);
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regnumber_index : array[tregisterindex] of tregisterindex = (
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{$i rarmrni.inc}
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);
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std_regname_index : array[tregisterindex] of tregisterindex = (
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{$i rarmsri.inc}
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);
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function cgsize2subreg(s:Tcgsize):Tsubregister;
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begin
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cgsize2subreg:=R_SUBWHOLE;
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end;
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function reg_cgsize(const reg: tregister): tcgsize;
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begin
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case getregtype(reg) of
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R_INTREGISTER :
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reg_cgsize:=OS_32;
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R_FPUREGISTER :
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reg_cgsize:=OS_F80;
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else
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internalerror(200303181);
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end;
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end;
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function is_calljmp(o:tasmop):boolean;
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begin
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{ This isn't 100% perfect because the arm allows jumps also by writing to PC=R15.
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To overcome this problem we simply forbid that FPC generates jumps by loading R15 }
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is_calljmp:= o in [A_B,A_BL,A_BX,A_BLX];
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end;
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procedure inverse_flags(var f: TResFlags);
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const
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inv_flags: array[TResFlags] of TResFlags =
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(F_NE,F_EQ,F_CC,F_CS,F_PL,F_MI,F_VC,F_VS,F_LS,F_HI,
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F_LT,F_GE,F_LE,F_GT);
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begin
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f:=inv_flags[f];
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end;
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function flags_to_cond(const f: TResFlags) : TAsmCond;
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const
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flag_2_cond: array[F_EQ..F_LE] of TAsmCond =
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(C_EQ,C_NE,C_CS,C_CC,C_MI,C_PL,C_VS,C_VC,C_HI,C_LS,
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C_GE,C_LT,C_GT,C_LE);
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begin
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if f>high(flag_2_cond) then
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internalerror(200112301);
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result:=flag_2_cond[f];
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end;
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function findreg_by_number(r:Tregister):tregisterindex;
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begin
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result:=rgBase.findreg_by_number_table(r,regnumber_index);
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end;
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function std_regnum_search(const s:string):Tregister;
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begin
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result:=regnumber_table[findreg_by_name_table(s,std_regname_table,std_regname_index)];
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end;
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function std_regname(r:Tregister):string;
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var
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p : tregisterindex;
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begin
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p:=findreg_by_number_table(r,regnumber_index);
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if p<>0 then
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result:=std_regname_table[p]
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else
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result:=generic_regname(r);
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end;
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procedure shifterop_reset(var so : tshifterop);
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begin
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FillChar(so,sizeof(so),0);
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end;
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function is_pc(const r : tregister) : boolean;
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begin
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is_pc:=(r=NR_R15);
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end;
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function inverse_cond(const c: TAsmCond): TAsmCond; {$ifdef USEINLINE}inline;{$endif USEINLINE}
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const
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inverse: array[TAsmCond] of TAsmCond=(C_None,
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C_NE,C_EQ,C_CC,C_CS,C_PL,C_MI,C_VC,C_VS,C_LS,C_HI,
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C_LT,C_GE,C_LE,C_GT,C_None,C_None
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);
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begin
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result := inverse[c];
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end;
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function conditions_equal(const c1, c2: TAsmCond): boolean; {$ifdef USEINLINE}inline;{$endif USEINLINE}
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begin
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result := c1 = c2;
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end;
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function rotl(d : dword;b : byte) : dword;
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begin
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result:=(d shr (32-b)) or (d shl b);
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end;
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function is_shifter_const(d : aint;var imm_shift : byte) : boolean;
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var
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i : longint;
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begin
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for i:=0 to 15 do
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begin
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if (dword(d) and not(rotl($ff,i*2)))=0 then
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begin
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imm_shift:=i*2;
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result:=true;
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exit;
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end;
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end;
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result:=false;
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end;
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function dwarf_reg(r:tregister):shortint;
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begin
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result:=regdwarf_table[findreg_by_number(r)];
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if result=-1 then
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internalerror(200603251);
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end;
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end.
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