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The sources of the Free Pascal compiler, RTL, packages and utilities.
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c75486db89
Reorder unaligned Load sequence on ARM The old version produced code like that: ldrb rDEST, [rBASE] ldrb rTemp, [rBASE, #1] orr rDEST, rDEST, rTEMP lsl #8 (2 stall cycles) ldrb rTemp, [rBASE, #2] orr rDEST, rDEST, rTEMP lsl #16 (2 stall cycles) ldrb rTemp, [rBASE, #3] orr rDEST, rDEST, rTEMP lsl #24 (2 stall cycles) This creates a lot of stall-cycles on ARM Implementations with load delay slots like Marvel Kirkwood or Intel XScale. With the usual up to 2 stall-cycles this code requires a total of 13 cycles (7 instructions + 6 stall cycles) in best case. The new code uses a second temp register to avoid the stall cycles. ldrb rDEST, [rBASE] ldrb rTemp1, [rBASE, #1] ldrb rTemp2, [rBASE, #2] orr rDEST, rDEST, rTEMP1 lsl #8 ldrb rTemp1, [rBASE, #3] orr rDEST, rDEST, rTEMP2 lsl #16 orr rDEST, rDEST, rTEMP1 lsl #24 (1 stall cycle) The rescheduling and second register bring the total cycles down to 8. If a later rescheduling should happen for the last orr it even can go down to 7. git-svn-id: trunk@21363 - |
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